KR101591855B1 - 반도체 집적 회로 장치의 제조 방법 - Google Patents

반도체 집적 회로 장치의 제조 방법 Download PDF

Info

Publication number
KR101591855B1
KR101591855B1 KR1020080079538A KR20080079538A KR101591855B1 KR 101591855 B1 KR101591855 B1 KR 101591855B1 KR 1020080079538 A KR1020080079538 A KR 1020080079538A KR 20080079538 A KR20080079538 A KR 20080079538A KR 101591855 B1 KR101591855 B1 KR 101591855B1
Authority
KR
South Korea
Prior art keywords
film
nitride film
oxide film
delete delete
hydrofluoric acid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020080079538A
Other languages
English (en)
Korean (ko)
Other versions
KR20090031216A (ko
Inventor
박상진
리차드 오. 헨리
권오성
권오정
용 시앙 탄
Original Assignee
삼성전자 주식회사
글로벌파운드리즈 싱가포르 피티이 엘티디
인피니언 테크놀로지스 아게
인터내셔널 비즈니스 머신즈 코오퍼레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사, 글로벌파운드리즈 싱가포르 피티이 엘티디, 인피니언 테크놀로지스 아게, 인터내셔널 비즈니스 머신즈 코오퍼레이션 filed Critical 삼성전자 주식회사
Publication of KR20090031216A publication Critical patent/KR20090031216A/ko
Application granted granted Critical
Publication of KR101591855B1 publication Critical patent/KR101591855B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01Manufacture or treatment
    • H10D62/021Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/601Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/601Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/791Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/015Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/021Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167Manufacturing their channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184Manufacturing their gate sidewall spacers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/60Wet etching
    • H10P50/61Electrolytic etching
    • H10P50/613Electrolytic etching of Group IV materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
  • Thin Film Transistor (AREA)
KR1020080079538A 2007-09-20 2008-08-13 반도체 집적 회로 장치의 제조 방법 Active KR101591855B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/858,535 US7902082B2 (en) 2007-09-20 2007-09-20 Method of forming field effect transistors using diluted hydrofluoric acid to remove sacrificial nitride spacers
US11/858,535 2007-09-20

Publications (2)

Publication Number Publication Date
KR20090031216A KR20090031216A (ko) 2009-03-25
KR101591855B1 true KR101591855B1 (ko) 2016-02-05

Family

ID=40472110

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080079538A Active KR101591855B1 (ko) 2007-09-20 2008-08-13 반도체 집적 회로 장치의 제조 방법

Country Status (4)

Country Link
US (1) US7902082B2 (https=)
JP (2) JP5441366B2 (https=)
KR (1) KR101591855B1 (https=)
SG (1) SG151194A1 (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008030854B4 (de) 2008-06-30 2014-03-20 Advanced Micro Devices, Inc. MOS-Transistoren mit abgesenkten Drain- und Source-Bereichen und nicht-konformen Metallsilizidgebieten und Verfahren zum Herstellen der Transistoren
JP2012186187A (ja) * 2009-07-08 2012-09-27 Sharp Corp エッチング方法およびエッチング処理装置
CN102856179B (zh) * 2011-06-29 2015-09-02 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
WO2013085490A1 (en) * 2011-12-06 2013-06-13 Intel Corporation Interlayer dielectric for non-planar transistors
KR101887144B1 (ko) 2012-03-15 2018-08-09 삼성전자주식회사 반도체 소자 및 이를 제조하는 방법
US8652917B2 (en) * 2012-05-23 2014-02-18 GlobalFoundries, Inc. Superior stability of characteristics of transistors having an early formed high-K metal gate
KR101921465B1 (ko) 2012-08-22 2018-11-26 삼성전자 주식회사 반도체 소자 및 이의 제조 방법
US8716136B1 (en) * 2012-10-19 2014-05-06 Globalfoundries Inc. Method of forming a semiconductor structure including a wet etch process for removing silicon nitride
JP6221155B2 (ja) * 2013-12-11 2017-11-01 株式会社Screenホールディングス 基板処理方法および基板処理装置
CN109103253B (zh) * 2017-06-21 2022-05-20 比亚迪半导体股份有限公司 Mos型功率器件及其制备方法
US10355100B1 (en) 2018-05-17 2019-07-16 Sandisk Technologies Llc Field effect transistors having different stress control liners and method of making the same
CN113322071A (zh) * 2021-05-28 2021-08-31 长江存储科技有限责任公司 刻蚀用组合物及其使用方法
JP7429211B2 (ja) * 2021-09-16 2024-02-07 合肥晶合集成電路股▲ふん▼有限公司 半導体デバイス及び半導体デバイスの製造方法
CN119698051A (zh) * 2024-12-20 2025-03-25 武汉新芯集成电路股份有限公司 一种半导体器件的制造方法及半导体器件

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001176839A (ja) * 1999-12-20 2001-06-29 Fujitsu Ltd 半導体装置の製造方法
WO2007054403A1 (en) * 2005-11-14 2007-05-18 International Business Machines Corporation Structure and method to increase strain enhancement with spacerless fet and dual liner process

Family Cites Families (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529297A (ja) * 1991-07-24 1993-02-05 Matsushita Electric Ind Co Ltd ウエツトエツチング装置
JPH06163509A (ja) * 1992-07-27 1994-06-10 Mitsubishi Kasei Corp エッチング処理液の制御方法
US5310457A (en) * 1992-09-30 1994-05-10 At&T Bell Laboratories Method of integrated circuit fabrication including selective etching of silicon and silicon compounds
JP3321864B2 (ja) 1992-11-24 2002-09-09 ヤマハ株式会社 半導体装置とその製法
JP3307489B2 (ja) * 1993-12-09 2002-07-24 三菱電機株式会社 半導体装置およびその製造方法
KR970001869B1 (ko) 1994-11-08 1997-02-17 대우통신 주식회사 휴대용 단말기의 위치데이터 제공방법
KR0183785B1 (ko) 1995-12-22 1999-03-20 윤종용 모스 트랜지스터 제조방법
US6657229B1 (en) * 1996-05-28 2003-12-02 United Microelectronics Corporation Semiconductor device having multiple transistors sharing a common gate
GB9618620D0 (en) 1996-09-06 1996-10-16 Electrotech Equipments Ltd A method of forming a layer
US6184157B1 (en) * 1998-06-01 2001-02-06 Sharp Laboratories Of America, Inc. Stress-loaded film and method for same
KR100327342B1 (ko) 1999-10-27 2002-03-06 윤종용 반도체소자 제조용 식각조성물 및 이 식각조성물을 이용한 식각방법
KR20010076522A (ko) 2000-01-26 2001-08-16 윤종용 반도체 제조 장비
US6372589B1 (en) * 2000-04-19 2002-04-16 Advanced Micro Devices, Inc. Method of forming ultra-shallow source/drain extension by impurity diffusion from doped dielectric spacer
JP4167381B2 (ja) 2000-06-08 2008-10-15 松下電器産業株式会社 半導体装置の製造方法
KR100375229B1 (ko) * 2000-07-10 2003-03-08 삼성전자주식회사 트렌치 소자분리 방법
KR20020017845A (ko) 2000-08-31 2002-03-07 박종섭 반도체소자의 비트라인 형성방법
KR20020074551A (ko) 2001-03-20 2002-10-04 삼성전자 주식회사 반도체 장치의 배선 형성 방법
JP2002289682A (ja) * 2001-03-28 2002-10-04 Nec Corp 半導体装置およびその製造方法
KR100867086B1 (ko) * 2001-04-27 2008-11-04 엔엑스피 비 브이 반도체 장치 제조 방법 및 장치
JP2003060076A (ja) 2001-08-21 2003-02-28 Nec Corp 半導体装置及びその製造方法
JP2003086704A (ja) 2001-09-14 2003-03-20 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP4173672B2 (ja) 2002-03-19 2008-10-29 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US20030209326A1 (en) 2002-05-07 2003-11-13 Mattson Technology, Inc. Process and system for heating semiconductor substrates in a processing chamber containing a susceptor
JP2004047608A (ja) 2002-07-10 2004-02-12 Toshiba Corp 半導体装置及びその製造方法
JP2004071928A (ja) * 2002-08-08 2004-03-04 Renesas Technology Corp 半導体装置の製造方法
JP3980985B2 (ja) 2002-10-04 2007-09-26 株式会社東芝 半導体装置とその製造方法
JP3974028B2 (ja) * 2002-11-29 2007-09-12 株式会社東芝 半導体装置の製造方法
US7022561B2 (en) * 2002-12-02 2006-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device
KR100498644B1 (ko) 2003-02-04 2005-07-01 동부아남반도체 주식회사 Pip 커패시터를 갖는 반도체 소자의 제조 방법
JP4015068B2 (ja) * 2003-06-17 2007-11-28 株式会社東芝 半導体装置の製造方法
JP2005064314A (ja) 2003-08-18 2005-03-10 Seiko Epson Corp 半導体装置及びその製造方法
US20050048732A1 (en) * 2003-08-26 2005-03-03 International Business Machines Corporation Method to produce transistor having reduced gate height
US6869866B1 (en) * 2003-09-22 2005-03-22 International Business Machines Corporation Silicide proximity structures for CMOS device performance improvements
US6939814B2 (en) * 2003-10-30 2005-09-06 International Business Machines Corporation Increasing carrier mobility in NFET and PFET transistors on a common wafer
US7015082B2 (en) * 2003-11-06 2006-03-21 International Business Machines Corporation High mobility CMOS circuits
KR101026472B1 (ko) 2003-11-19 2011-04-01 매그나칩 반도체 유한회사 반도체 소자의 게이트 형성방법
JP3811697B2 (ja) * 2003-11-19 2006-08-23 松下電器産業株式会社 半導体装置の製造方法
KR100616499B1 (ko) 2003-11-21 2006-08-28 주식회사 하이닉스반도체 반도체소자 제조 방법
US7052946B2 (en) * 2004-03-10 2006-05-30 Taiwan Semiconductor Manufacturing Co. Ltd. Method for selectively stressing MOSFETs to improve charge carrier mobility
TWI252539B (en) * 2004-03-12 2006-04-01 Toshiba Corp Semiconductor device and manufacturing method therefor
KR101025761B1 (ko) * 2004-03-30 2011-04-04 삼성전자주식회사 디지탈 회로 및 아날로그 회로를 가지는 반도체 집적회로및 그 제조 방법
US7190033B2 (en) * 2004-04-15 2007-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device and method of manufacture
KR20060000912A (ko) 2004-06-30 2006-01-06 주식회사 하이닉스반도체 반도체 소자 제조 방법
JP4444027B2 (ja) 2004-07-08 2010-03-31 富士通マイクロエレクトロニクス株式会社 nチャネルMOSトランジスタおよびCMOS集積回路装置
US20060011586A1 (en) * 2004-07-14 2006-01-19 Shea Kevin R Method of etching nitrides
JP2006041118A (ja) * 2004-07-26 2006-02-09 Toshiba Corp 半導体装置及びその製造方法
DE102004042167B4 (de) * 2004-08-31 2009-04-02 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Ausbilden einer Halbleiterstruktur, die Transistorelemente mit unterschiedlich verspannten Kanalgebieten umfasst, und entsprechende Halbleiterstruktur
JP4794838B2 (ja) 2004-09-07 2011-10-19 富士通セミコンダクター株式会社 半導体装置およびその製造方法
DE102004052617B4 (de) * 2004-10-29 2010-08-05 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Halbleiterbauelements und Halbleiterbauelement mit Halbleitergebieten, die unterschiedlich verformte Kanalgebiete aufweisen
DE102004052578B4 (de) * 2004-10-29 2009-11-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erzeugen einer unterschiedlichen mechanischen Verformung in unterschiedlichen Kanalgebieten durch Bilden eines Ätzstoppschichtstapels mit unterschiedlich modifizierter innerer Spannung
US7344934B2 (en) * 2004-12-06 2008-03-18 Infineon Technologies Ag CMOS transistor and method of manufacture thereof
JP5002891B2 (ja) 2004-12-17 2012-08-15 富士通セミコンダクター株式会社 半導体装置の製造方法
JP4453572B2 (ja) 2005-02-22 2010-04-21 ソニー株式会社 半導体集積回路の製造方法
US7229869B2 (en) * 2005-03-08 2007-06-12 Texas Instruments Incorporated Method for manufacturing a semiconductor device using a sidewall spacer etchback
JP2006324278A (ja) 2005-05-17 2006-11-30 Sony Corp 半導体装置およびその製造方法
US7569888B2 (en) * 2005-08-10 2009-08-04 Toshiba America Electronic Components, Inc. Semiconductor device with close stress liner film and method of manufacturing the same
US7297584B2 (en) * 2005-10-07 2007-11-20 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices having a dual stress liner
JP5091397B2 (ja) * 2005-10-27 2012-12-05 パナソニック株式会社 半導体装置
US20070099360A1 (en) * 2005-11-03 2007-05-03 International Business Machines Corporation Integrated circuits having strained channel field effect transistors and methods of making
US7759206B2 (en) * 2005-11-29 2010-07-20 International Business Machines Corporation Methods of forming semiconductor devices using embedded L-shape spacers
US7521307B2 (en) * 2006-04-28 2009-04-21 International Business Machines Corporation CMOS structures and methods using self-aligned dual stressed layers
US7719089B2 (en) * 2006-05-05 2010-05-18 Sony Corporation MOSFET having a channel region with enhanced flexure-induced stress
US7585720B2 (en) * 2006-07-05 2009-09-08 Toshiba America Electronic Components, Inc. Dual stress liner device and method
US20080026523A1 (en) * 2006-07-28 2008-01-31 Chartered Semiconductor Manufacturing, Ltd And International Business Machines Corporation (Ibm) Structure and method to implement dual stressor layers with improved silicide control
US7482215B2 (en) * 2006-08-30 2009-01-27 International Business Machines Corporation Self-aligned dual segment liner and method of manufacturing the same
KR100773352B1 (ko) * 2006-09-25 2007-11-05 삼성전자주식회사 스트레스 인가 모스 트랜지스터를 갖는 반도체소자의제조방법 및 그에 의해 제조된 반도체소자
US7534678B2 (en) * 2007-03-27 2009-05-19 Samsung Electronics Co., Ltd. Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby
US7521314B2 (en) * 2007-04-20 2009-04-21 Freescale Semiconductor, Inc. Method for selective removal of a layer
JP2009099724A (ja) * 2007-10-16 2009-05-07 Toshiba Corp 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001176839A (ja) * 1999-12-20 2001-06-29 Fujitsu Ltd 半導体装置の製造方法
WO2007054403A1 (en) * 2005-11-14 2007-05-18 International Business Machines Corporation Structure and method to increase strain enhancement with spacerless fet and dual liner process

Also Published As

Publication number Publication date
KR20090031216A (ko) 2009-03-25
JP2009076857A (ja) 2009-04-09
US7902082B2 (en) 2011-03-08
SG151194A1 (en) 2009-04-30
JP5981385B2 (ja) 2016-08-31
JP5441366B2 (ja) 2014-03-12
JP2013179323A (ja) 2013-09-09
US20090081840A1 (en) 2009-03-26

Similar Documents

Publication Publication Date Title
KR101591855B1 (ko) 반도체 집적 회로 장치의 제조 방법
US7211871B2 (en) Transistors of semiconductor devices and methods of fabricating the same
US6406973B1 (en) Transistor in a semiconductor device and method of manufacturing the same
US7154154B2 (en) MOS transistors having inverted T-shaped gate electrodes
US6403485B1 (en) Method to form a low parasitic capacitance pseudo-SOI CMOS device
EP1470582B1 (en) Reduction of negative bias temperature instability in narrow width pmos using f2 implantation
US20080122017A1 (en) Semiconductor device and fabricating method thereof
JP4514023B2 (ja) ソース/ドレイン拡張部からドーパントが外方拡散しないようにするための、シリコン酸化物ライナーのイオン注入
KR20100078058A (ko) 반도체 소자 제조 방법
US20080171412A1 (en) Fabrication methods for mos device and cmos device
US20080160710A1 (en) Method of fabricating mosfet device
KR100306504B1 (ko) 저가의 미크론 이하의 깊이를 갖는 cmos 제조방법
US7105414B2 (en) Method of manufacturing MOS transistor
KR101044385B1 (ko) 반도체 소자의 제조방법
KR100458770B1 (ko) 반도체 소자의 제조 방법
KR20040057528A (ko) 반도체 소자의 제조 방법
KR20050048125A (ko) 반도체 소자의 제조방법
KR100537269B1 (ko) 반도체 소자의 트랜지스터 제조 방법
JP4770353B2 (ja) 半導体装置の製造方法
KR20050040417A (ko) 반도체 소자의 제조 방법
KR20080023058A (ko) 반도체 소자의 제조방법
KR20050118467A (ko) 게이트 절연막 형성방법 및 이를 이용한 반도체 소자의제조방법
KR20030001067A (ko) 저농도 도핑 드레인 구조의 모스 트랜지스터 제조방법
KR20040007802A (ko) 반도체소자의 제조방법
KR20030049566A (ko) 반도체 장치의 트랜지스터 제조방법

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

FPAY Annual fee payment

Payment date: 20191226

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 11

U11 Full renewal or maintenance fee paid

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U11-OTH-PR1001 (AS PROVIDED BY THE NATIONAL OFFICE)

Year of fee payment: 11

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000