KR100698989B1 - 반도체 집적 회로 장치의 제조 방법 및 반도체 집적 회로장치 - Google Patents

반도체 집적 회로 장치의 제조 방법 및 반도체 집적 회로장치 Download PDF

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Publication number
KR100698989B1
KR100698989B1 KR1020010042259A KR20010042259A KR100698989B1 KR 100698989 B1 KR100698989 B1 KR 100698989B1 KR 1020010042259 A KR1020010042259 A KR 1020010042259A KR 20010042259 A KR20010042259 A KR 20010042259A KR 100698989 B1 KR100698989 B1 KR 100698989B1
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South Korea
Prior art keywords
pattern
hole
patterns
insulating film
wiring
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Expired - Fee Related
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KR1020010042259A
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English (en)
Korean (ko)
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KR20020007195A (ko
Inventor
하야노가쯔야
이마이아끼라
하세가와노리오
Original Assignee
가부시키가이샤 히타치세이사쿠쇼
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Publication of KR20020007195A publication Critical patent/KR20020007195A/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • G03F1/30—Alternating PSM, e.g. Levenson-Shibuya PSM; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/946—Step and repeat

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Semiconductor Memories (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
KR1020010042259A 2000-07-14 2001-07-13 반도체 집적 회로 장치의 제조 방법 및 반도체 집적 회로장치 Expired - Fee Related KR100698989B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2000-00215092 2000-07-14
JP2000215092A JP3983960B2 (ja) 2000-07-14 2000-07-14 半導体集積回路装置の製造方法および半導体集積回路装置

Publications (2)

Publication Number Publication Date
KR20020007195A KR20020007195A (ko) 2002-01-26
KR100698989B1 true KR100698989B1 (ko) 2007-03-26

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KR1020010042259A Expired - Fee Related KR100698989B1 (ko) 2000-07-14 2001-07-13 반도체 집적 회로 장치의 제조 방법 및 반도체 집적 회로장치

Country Status (4)

Country Link
US (2) US6403413B2 (enExample)
JP (1) JP3983960B2 (enExample)
KR (1) KR100698989B1 (enExample)
TW (1) TW558756B (enExample)

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KR100438782B1 (ko) * 2001-12-29 2004-07-05 삼성전자주식회사 반도체 소자의 실린더형 커패시터 제조방법
US7233887B2 (en) * 2002-01-18 2007-06-19 Smith Bruce W Method of photomask correction and its optimization using localized frequency analysis
JP2003273245A (ja) * 2002-03-15 2003-09-26 Hitachi Ltd 半導体記憶装置
US6649945B1 (en) 2002-10-18 2003-11-18 Kabushiki Kaisha Toshiba Wiring layout to weaken an electric field generated between the lines exposed to a high voltage
KR100505656B1 (ko) * 2002-12-10 2005-08-04 삼성전자주식회사 스토리지 전극과의 접촉 면적을 보다 확보하기 위해서비트 라인 방향으로 확장된 콘택체를 포함하는 반도체소자 제조 방법
TWI250558B (en) * 2003-10-23 2006-03-01 Hynix Semiconductor Inc Method for fabricating semiconductor device with fine patterns
US7430731B2 (en) * 2003-12-31 2008-09-30 University Of Southern California Method for electrochemically fabricating three-dimensional structures including pseudo-rasterization of data
KR100656497B1 (ko) * 2004-02-09 2006-12-11 삼성에스디아이 주식회사 유기전계발광표시장치 및 그의 제조방법
US7126182B2 (en) * 2004-08-13 2006-10-24 Micron Technology, Inc. Memory circuitry
JP4936659B2 (ja) * 2004-12-27 2012-05-23 株式会社東芝 半導体装置の製造方法
JP5030131B2 (ja) * 2004-12-28 2012-09-19 エスケーハイニックス株式会社 ナンドフラッシュメモリ素子
KR100577542B1 (ko) * 2005-03-11 2006-05-10 삼성전자주식회사 매몰콘택 플러그를 갖는 반도체소자의 제조방법
JP4750525B2 (ja) * 2005-10-14 2011-08-17 キヤノン株式会社 露光方法及びデバイス製造方法
KR100706817B1 (ko) 2006-03-13 2007-04-12 삼성전자주식회사 비휘발성 메모리 장치 및 그 형성 방법
KR100722769B1 (ko) * 2006-05-19 2007-05-30 삼성전자주식회사 상변화 메모리 장치 및 이의 형성 방법
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JP4352068B2 (ja) * 2006-09-08 2009-10-28 株式会社東芝 露光方法及び半導体装置の製造方法
US7742324B2 (en) * 2008-02-19 2010-06-22 Micron Technology, Inc. Systems and devices including local data lines and methods of using, making, and operating the same
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US8866254B2 (en) 2008-02-19 2014-10-21 Micron Technology, Inc. Devices including fin transistors robust to gate shorts and methods of making the same
JP4834784B2 (ja) * 2008-03-03 2011-12-14 株式会社東芝 半導体装置の製造方法
JP4635085B2 (ja) 2008-03-03 2011-02-16 株式会社東芝 半導体装置の製造方法
US7915659B2 (en) * 2008-03-06 2011-03-29 Micron Technology, Inc. Devices with cavity-defined gates and methods of making the same
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US7808042B2 (en) * 2008-03-20 2010-10-05 Micron Technology, Inc. Systems and devices including multi-gate transistors and methods of using, making, and operating the same
US7969776B2 (en) 2008-04-03 2011-06-28 Micron Technology, Inc. Data cells with drivers and methods of making and operating the same
KR101442175B1 (ko) * 2008-05-23 2014-09-18 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 메모리 셀 어레이의 배치방법
US8076229B2 (en) * 2008-05-30 2011-12-13 Micron Technology, Inc. Methods of forming data cells and connections to data cells
US8148776B2 (en) 2008-09-15 2012-04-03 Micron Technology, Inc. Transistor with a passive gate
KR20100055731A (ko) * 2008-11-18 2010-05-27 삼성전자주식회사 레티클 및 반도체 소자의 형성 방법
JP2010161173A (ja) 2009-01-07 2010-07-22 Renesas Electronics Corp 半導体記憶装置
JP2011159739A (ja) 2010-01-29 2011-08-18 Elpida Memory Inc 半導体装置および半導体装置の製造方法
US8294511B2 (en) 2010-11-19 2012-10-23 Micron Technology, Inc. Vertically stacked fin transistors and methods of fabricating and operating the same
US8372743B2 (en) * 2011-03-02 2013-02-12 Texas Instruments Incorporated Hybrid pitch-split pattern-split lithography process
US8461038B2 (en) * 2011-03-02 2013-06-11 Texas Instruments Incorporated Two-track cross-connects in double-patterned metal layers using a forbidden zone
US8575020B2 (en) * 2011-03-02 2013-11-05 Texas Instruments Incorporated Pattern-split decomposition strategy for double-patterned lithography process
JP2013254815A (ja) * 2012-06-06 2013-12-19 Ps4 Luxco S A R L 半導体装置およびその製造方法
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KR102248436B1 (ko) * 2014-05-23 2021-05-07 삼성전자주식회사 반도체 소자의 제조방법
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KR20000006201A (ko) * 1998-06-17 2000-01-25 가나이 쓰토무 반도체집적회로장치의제조방법및반도체집적회로장치
KR20000035011A (ko) * 1998-11-13 2000-06-26 포만 제프리 엘 배선과 자기 정렬되는 서브임계 콘택 형성 방법
KR20000076456A (ko) * 1999-05-11 2000-12-26 아끼구사 나오유끼 반도체 장치 및 그 제조 방법

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Publication number Publication date
US20020155656A1 (en) 2002-10-24
KR20020007195A (ko) 2002-01-26
US20020005542A1 (en) 2002-01-17
JP3983960B2 (ja) 2007-09-26
US6403413B2 (en) 2002-06-11
US6750496B2 (en) 2004-06-15
TW558756B (en) 2003-10-21
JP2002031883A (ja) 2002-01-31

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