JP3983960B2 - 半導体集積回路装置の製造方法および半導体集積回路装置 - Google Patents

半導体集積回路装置の製造方法および半導体集積回路装置 Download PDF

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Publication number
JP3983960B2
JP3983960B2 JP2000215092A JP2000215092A JP3983960B2 JP 3983960 B2 JP3983960 B2 JP 3983960B2 JP 2000215092 A JP2000215092 A JP 2000215092A JP 2000215092 A JP2000215092 A JP 2000215092A JP 3983960 B2 JP3983960 B2 JP 3983960B2
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Japan
Prior art keywords
pattern
wiring
insulating film
hole
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000215092A
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English (en)
Japanese (ja)
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JP2002031883A (ja
JP2002031883A5 (enExample
Inventor
勝也 早野
彰 今井
昇雄 長谷川
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Renesas Technology Corp
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Renesas Technology Corp
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Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2000215092A priority Critical patent/JP3983960B2/ja
Priority to TW090116490A priority patent/TW558756B/zh
Priority to KR1020010042259A priority patent/KR100698989B1/ko
Priority to US09/904,591 priority patent/US6403413B2/en
Publication of JP2002031883A publication Critical patent/JP2002031883A/ja
Priority to US10/142,063 priority patent/US6750496B2/en
Publication of JP2002031883A5 publication Critical patent/JP2002031883A5/ja
Application granted granted Critical
Publication of JP3983960B2 publication Critical patent/JP3983960B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • G03F1/30—Alternating PSM, e.g. Levenson-Shibuya PSM; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/946—Step and repeat

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Semiconductor Memories (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2000215092A 2000-07-14 2000-07-14 半導体集積回路装置の製造方法および半導体集積回路装置 Expired - Fee Related JP3983960B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2000215092A JP3983960B2 (ja) 2000-07-14 2000-07-14 半導体集積回路装置の製造方法および半導体集積回路装置
TW090116490A TW558756B (en) 2000-07-14 2001-07-05 Method for manufacturing semiconductor integrated circuit device and semiconductor integrated circuit device
KR1020010042259A KR100698989B1 (ko) 2000-07-14 2001-07-13 반도체 집적 회로 장치의 제조 방법 및 반도체 집적 회로장치
US09/904,591 US6403413B2 (en) 2000-07-14 2001-07-16 Manufacturing method of semiconductor integrated circuit device having a capacitor
US10/142,063 US6750496B2 (en) 2000-07-14 2002-05-10 Manufacturing method of semiconductor integrated circuit device, and semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000215092A JP3983960B2 (ja) 2000-07-14 2000-07-14 半導体集積回路装置の製造方法および半導体集積回路装置

Publications (3)

Publication Number Publication Date
JP2002031883A JP2002031883A (ja) 2002-01-31
JP2002031883A5 JP2002031883A5 (enExample) 2005-02-03
JP3983960B2 true JP3983960B2 (ja) 2007-09-26

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JP2000215092A Expired - Fee Related JP3983960B2 (ja) 2000-07-14 2000-07-14 半導体集積回路装置の製造方法および半導体集積回路装置

Country Status (4)

Country Link
US (2) US6403413B2 (enExample)
JP (1) JP3983960B2 (enExample)
KR (1) KR100698989B1 (enExample)
TW (1) TW558756B (enExample)

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US7233887B2 (en) * 2002-01-18 2007-06-19 Smith Bruce W Method of photomask correction and its optimization using localized frequency analysis
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US6649945B1 (en) 2002-10-18 2003-11-18 Kabushiki Kaisha Toshiba Wiring layout to weaken an electric field generated between the lines exposed to a high voltage
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TWI250558B (en) * 2003-10-23 2006-03-01 Hynix Semiconductor Inc Method for fabricating semiconductor device with fine patterns
US7430731B2 (en) * 2003-12-31 2008-09-30 University Of Southern California Method for electrochemically fabricating three-dimensional structures including pseudo-rasterization of data
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KR100577542B1 (ko) * 2005-03-11 2006-05-10 삼성전자주식회사 매몰콘택 플러그를 갖는 반도체소자의 제조방법
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KR100722769B1 (ko) * 2006-05-19 2007-05-30 삼성전자주식회사 상변화 메모리 장치 및 이의 형성 방법
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JP4834784B2 (ja) * 2008-03-03 2011-12-14 株式会社東芝 半導体装置の製造方法
JP4635085B2 (ja) * 2008-03-03 2011-02-16 株式会社東芝 半導体装置の製造方法
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Also Published As

Publication number Publication date
US20020005542A1 (en) 2002-01-17
JP2002031883A (ja) 2002-01-31
US20020155656A1 (en) 2002-10-24
KR100698989B1 (ko) 2007-03-26
US6750496B2 (en) 2004-06-15
TW558756B (en) 2003-10-21
KR20020007195A (ko) 2002-01-26
US6403413B2 (en) 2002-06-11

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