JP6139578B2 - 装置および方法 - Google Patents

装置および方法 Download PDF

Info

Publication number
JP6139578B2
JP6139578B2 JP2015020306A JP2015020306A JP6139578B2 JP 6139578 B2 JP6139578 B2 JP 6139578B2 JP 2015020306 A JP2015020306 A JP 2015020306A JP 2015020306 A JP2015020306 A JP 2015020306A JP 6139578 B2 JP6139578 B2 JP 6139578B2
Authority
JP
Japan
Prior art keywords
solder ball
solder balls
solder
substrate
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015020306A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015170854A (ja
Inventor
ボニス、トーマス ジェイ． デ
ボニス、トーマス ジェイ． デ
メイ、リリア
エス． シズ、ラジェン
エス． シズ、ラジェン
ピー． レナヴィカー、ムクル
ピー． レナヴィカー、ムクル
エー． ダニ、アシャイ
エー． ダニ、アシャイ
アール． プラック、エドワード
アール． プラック、エドワード
エル． デッピシュ、カール
エル． デッピシュ、カール
エム． プラカシュ、アンナ
エム． プラカシュ、アンナ
（ジュニア）、ジェームス シー． マタヤバス
（ジュニア）、ジェームス シー． マタヤバス
ジエピン ザン、ジェイソン
ジエピン ザン、ジェイソン
アール． アラヴァムダン、スリニヴァサ
アール． アラヴァムダン、スリニヴァサ
リン、チャン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of JP2015170854A publication Critical patent/JP2015170854A/ja
Application granted granted Critical
Publication of JP6139578B2 publication Critical patent/JP6139578B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/016—Manufacture or treatment using moulds
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/823—Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
JP2015020306A 2014-03-05 2015-02-04 装置および方法 Active JP6139578B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/198,479 2014-03-05
US14/198,479 US9613933B2 (en) 2014-03-05 2014-03-05 Package structure to enhance yield of TMI interconnections

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2017088851A Division JP6593762B2 (ja) 2014-03-05 2017-04-27 装置および方法

Publications (2)

Publication Number Publication Date
JP2015170854A JP2015170854A (ja) 2015-09-28
JP6139578B2 true JP6139578B2 (ja) 2017-05-31

Family

ID=54018122

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2015020306A Active JP6139578B2 (ja) 2014-03-05 2015-02-04 装置および方法
JP2017088851A Active JP6593762B2 (ja) 2014-03-05 2017-04-27 装置および方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2017088851A Active JP6593762B2 (ja) 2014-03-05 2017-04-27 装置および方法

Country Status (2)

Country Link
US (2) US9613933B2 (https=)
JP (2) JP6139578B2 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110024115B (zh) * 2016-10-04 2024-02-02 天工方案公司 具有包覆模制结构的双侧射频封装
JP6784330B2 (ja) * 2017-06-20 2020-11-11 株式会社村田製作所 モジュールおよびその製造方法
US10573622B2 (en) * 2017-09-29 2020-02-25 Intel Corporation Methods of forming joint structures for surface mount packages
CN108346952B (zh) * 2018-01-25 2020-11-24 番禺得意精密电子工业有限公司 电连接器固持装置
US11201136B2 (en) 2020-03-10 2021-12-14 International Business Machines Corporation High bandwidth module
US11955396B2 (en) * 2020-11-27 2024-04-09 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
US12159850B2 (en) 2020-12-25 2024-12-03 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
US12154884B2 (en) 2021-02-01 2024-11-26 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
US12500203B2 (en) 2021-02-22 2025-12-16 Yibu Semiconductor Co., Ltd. Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly
EP4535481A4 (en) * 2022-06-01 2025-12-24 Inst Of Science Tokyo ALL-SOLID LITHIUM-ION SECONDARY BATTERY AND METHOD FOR MANUFACTURING ALL-SOLID LITHIUM-ION SECONDARY BATTERIES

Family Cites Families (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3334693B2 (ja) * 1999-10-08 2002-10-15 日本電気株式会社 半導体装置の製造方法
SG99331A1 (en) * 2000-01-13 2003-10-27 Hitachi Ltd Method of producing electronic part with bumps and method of producing elctronic part
US6504242B1 (en) 2001-11-15 2003-01-07 Intel Corporation Electronic assembly having a wetting layer on a thermally conductive heat spreader
US6597575B1 (en) 2002-01-04 2003-07-22 Intel Corporation Electronic packages having good reliability comprising low modulus thermal interface materials
US7036573B2 (en) 2002-02-08 2006-05-02 Intel Corporation Polymer with solder pre-coated fillers for thermal interface materials
US7436058B2 (en) 2002-05-09 2008-10-14 Intel Corporation Reactive solder material
JP4086657B2 (ja) * 2002-12-27 2008-05-14 富士通株式会社 積層型半導体装置
US6841867B2 (en) 2002-12-30 2005-01-11 Intel Corporation Gel thermal interface materials comprising fillers having low melting point and electronic packages comprising these gel thermal interface materials
US7252877B2 (en) 2003-02-04 2007-08-07 Intel Corporation Polymer matrices for polymer solder hybrid materials
JP2004349495A (ja) * 2003-03-25 2004-12-09 Seiko Epson Corp 半導体装置、電子デバイス、電子機器および半導体装置の製造方法
US7014093B2 (en) 2003-06-26 2006-03-21 Intel Corporation Multi-layer polymer-solder hybrid thermal interface material for integrated heat spreader and method of making same
US7527090B2 (en) 2003-06-30 2009-05-05 Intel Corporation Heat dissipating device with preselected designed interface for thermal interface materials
US7253523B2 (en) 2003-07-29 2007-08-07 Intel Corporation Reworkable thermal interface material
US7170188B2 (en) 2004-06-30 2007-01-30 Intel Corporation Package stress management
JP4137112B2 (ja) * 2005-10-20 2008-08-20 日本テキサス・インスツルメンツ株式会社 電子部品の製造方法
US7638868B2 (en) * 2006-08-16 2009-12-29 Tessera, Inc. Microelectronic package
US7823762B2 (en) * 2006-09-28 2010-11-02 Ibiden Co., Ltd. Manufacturing method and manufacturing apparatus of printed wiring board
JP5044189B2 (ja) * 2006-10-24 2012-10-10 リンテック株式会社 複合型半導体装置の製造方法、及び複合型半導体装置
JP2009021465A (ja) * 2007-07-13 2009-01-29 Panasonic Corp 半導体装置実装構造体およびその製造方法ならびに半導体装置の剥離方法
KR100923887B1 (ko) * 2008-01-29 2009-10-28 (주)덕산테코피아 반도체 패키지용 솔더볼
JP5581576B2 (ja) * 2008-04-02 2014-09-03 日立化成株式会社 フラックス活性剤、接着剤樹脂組成物、接着ペースト、接着フィルム、半導体装置の製造方法、及び半導体装置
US7851894B1 (en) * 2008-12-23 2010-12-14 Amkor Technology, Inc. System and method for shielding of package on package (PoP) assemblies
JP2010205934A (ja) * 2009-03-03 2010-09-16 Panasonic Corp 回路部品内蔵モジュール、および回路部品内蔵モジュールの製造方法
US9006887B2 (en) * 2009-03-04 2015-04-14 Intel Corporation Forming sacrificial composite materials for package-on-package architectures and structures formed thereby
KR101055509B1 (ko) 2009-03-19 2011-08-08 삼성전기주식회사 전자부품 내장형 인쇄회로기판
KR101077410B1 (ko) 2009-05-15 2011-10-26 삼성전기주식회사 방열부재를 구비한 전자부품 내장형 인쇄회로기판 및 그 제조방법
KR20100132823A (ko) 2009-06-10 2010-12-20 삼성전기주식회사 플립칩용 기판 및 그 제조방법
KR101194549B1 (ko) 2009-06-12 2012-10-25 삼성전기주식회사 인쇄회로기판의 제조방법
US8430969B2 (en) * 2009-07-20 2013-04-30 Texas Instruments Incorporated Method for exposing and cleaning insulating coats from metal contact surfaces
KR20110030152A (ko) 2009-09-17 2011-03-23 삼성전기주식회사 패키지기판 및 그 제조방법
KR101037450B1 (ko) 2009-09-23 2011-05-26 삼성전기주식회사 패키지 기판
US20110076472A1 (en) 2009-09-29 2011-03-31 Jin Ho Kim Package substrate
KR20110039879A (ko) 2009-10-12 2011-04-20 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
KR101084910B1 (ko) 2009-10-12 2011-11-17 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
JP5525793B2 (ja) * 2009-10-19 2014-06-18 パナソニック株式会社 半導体装置
KR101095094B1 (ko) 2009-10-26 2011-12-16 삼성전기주식회사 웨이퍼 레벨 패키지의 제조방법
KR101095130B1 (ko) 2009-12-01 2011-12-16 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
US20110147668A1 (en) 2009-12-23 2011-06-23 Sang Hwa Kim Conductive polymer composition and conductive film prepared using the same
US20110240927A1 (en) 2009-12-23 2011-10-06 Samsung Electro-Mechanics Co., Ltd. Conductive polymer composition and conductive film formed using the same
KR101109214B1 (ko) 2009-12-28 2012-01-30 삼성전기주식회사 패키지 기판 및 그 제조방법
KR101119303B1 (ko) 2010-01-06 2012-03-20 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
KR101077408B1 (ko) 2010-02-05 2011-10-26 서강대학교산학협력단 Ｃｍｏｓ 이미지 센서
KR101067109B1 (ko) 2010-04-26 2011-09-26 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
KR20120026855A (ko) 2010-09-10 2012-03-20 삼성전기주식회사 임베디드 볼 그리드 어레이 기판 및 그 제조 방법
KR101289140B1 (ko) 2010-09-28 2013-07-23 삼성전기주식회사 임베디드 인쇄회로기판 및 그 제조방법
KR20120035673A (ko) 2010-10-06 2012-04-16 삼성전기주식회사 패키지기판
KR101095161B1 (ko) 2010-10-07 2011-12-16 삼성전기주식회사 전자부품 내장형 인쇄회로기판
KR20120050755A (ko) 2010-11-11 2012-05-21 삼성전기주식회사 반도체 패키지 기판 및 그 제조방법
KR101719822B1 (ko) 2010-11-24 2017-03-27 삼성전기주식회사 솔더링 연결핀, 상기 솔더링 연결핀을 이용한 반도체 패키지 기판 및 반도체칩의 실장방법
KR20120069443A (ko) 2010-12-20 2012-06-28 삼성전기주식회사 패키지 기판용 리드핀과 상기 패키지 기판용 리드핀을 포함하는 반도체 패키지 인쇄회로기판
KR101204233B1 (ko) 2010-12-22 2012-11-26 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법
KR101194469B1 (ko) 2010-12-24 2012-10-24 삼성전기주식회사 패키지용 기판 및 그 제조방법
KR101255912B1 (ko) 2010-12-31 2013-04-17 삼성전기주식회사 멀티 칩 패키지
US8162203B1 (en) * 2011-02-18 2012-04-24 International Business Machines Corporation Spherical solder reflow method
KR20140007429A (ko) 2011-03-31 2014-01-17 미쓰비시 가가꾸 가부시키가이샤 삼차원 집적 회로 적층체, 및 삼차원 집적 회로 적층체용 층간 충전재
JP2012216836A (ja) * 2011-03-31 2012-11-08 Mitsubishi Chemicals Corp 三次元集積回路積層体
JP5837339B2 (ja) * 2011-06-20 2015-12-24 新光電気工業株式会社 半導体装置の製造方法及び半導体装置
KR101237668B1 (ko) 2011-08-10 2013-02-26 삼성전기주식회사 반도체 패키지 기판
US9950393B2 (en) 2011-12-23 2018-04-24 Intel Corporation Hybrid low metal loading flux
KR20130082298A (ko) 2012-01-11 2013-07-19 삼성전자주식회사 패키지 온 패키지 장치의 제조 방법 및 이에 의해 제조된 장치
JP2013225638A (ja) 2012-03-23 2013-10-31 Toshiba Corp 半導体装置
US8704354B2 (en) * 2012-03-28 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package structures and methods for forming the same
KR101867955B1 (ko) 2012-04-13 2018-06-15 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
JP2014033084A (ja) * 2012-08-03 2014-02-20 Panasonic Corp 積層パッケージ構造体の製造方法、組み立て装置、および製造システム
US9283641B2 (en) 2012-09-25 2016-03-15 Intel Corporation Flux materials for heated solder placement and associated techniques and configurations
US8809181B2 (en) 2012-11-07 2014-08-19 Intel Corporation Multi-solder techniques and configurations for integrated circuit package assembly
US9105626B2 (en) * 2012-11-21 2015-08-11 Qualcomm Incorporated High-density package-on-package structure
US20140151096A1 (en) 2012-12-04 2014-06-05 Hongjin Jiang Low temperature/high temperature solder hybrid solder interconnects
US9064971B2 (en) 2012-12-20 2015-06-23 Intel Corporation Methods of forming ultra thin package structures including low temperature solder and structures formed therby
US20140175160A1 (en) 2012-12-21 2014-06-26 Rajen S. Sidhu Solder paste material technology for elimination of high warpage surface mount assembly defects
US9394619B2 (en) 2013-03-12 2016-07-19 Intel Corporation Methods of adding dopants to conductive interconnect structures in substrate technologies and structures formed thereby
US8896110B2 (en) 2013-03-13 2014-11-25 Intel Corporation Paste thermal interface materials
US8987918B2 (en) * 2013-03-14 2015-03-24 Intel Corporation Interconnect structures with polymer core
US8920934B2 (en) * 2013-03-29 2014-12-30 Intel Corporation Hybrid solder and filled paste in microelectronic packaging
KR102067155B1 (ko) * 2013-06-03 2020-01-16 삼성전자주식회사 연결단자를 갖는 반도체 장치 및 그의 제조방법

Also Published As

Publication number Publication date
JP2017126806A (ja) 2017-07-20
JP2015170854A (ja) 2015-09-28
US20150255415A1 (en) 2015-09-10
US20170207152A1 (en) 2017-07-20
US9613933B2 (en) 2017-04-04
US10049971B2 (en) 2018-08-14
JP6593762B2 (ja) 2019-10-23

Similar Documents

Publication Publication Date Title
JP6593762B2 (ja) 装置および方法
TWI459505B (zh) 電互連結構及方法
TWI582868B (zh) Semiconductor device manufacturing method
JP5874683B2 (ja) 実装基板の製造方法、および電子機器の製造方法
KR101569577B1 (ko) 패키지 온 패키지 구조물 및 이의 형성 방법
JP4137112B2 (ja) 電子部品の製造方法
TW201923985A (zh) 具有多層囊封物之半導體裝置及相關系統、裝置及方法
JP5272922B2 (ja) 半導体装置及びその製造方法
TW201705414A (zh) 用來控制積體電路封裝扭曲的可移除式基板
KR20010050870A (ko) 반도체 장치 제조 방법
CN108198794A (zh) 一种芯片封装体及其制备方法
US6722557B2 (en) Flux cleaning method and method of manufacturing semiconductor device
US6227434B1 (en) Reworking of a ball grid array module
US8183697B2 (en) Apparatus and methods of forming an interconnect between a workpiece and substrate
WO2010070779A1 (ja) 異方性導電樹脂、基板接続構造及び電子機器
CN108231717A (zh) 一种封装元件及其制备方法
US20150251278A1 (en) Solder ball and circuit board including the same
CN104981092A (zh) 表面镀层和包括该表面镀层的半导体封装件
JP2005150446A (ja) 電子部品の製造方法
CN101276764A (zh) 半导体装置的制造方法
JP2004288771A (ja) 電子部品
JP6426453B2 (ja) 回路基板の製造方法
CN112004337A (zh) 具有涂层的焊球、植球方法及封装方法
KR101261926B1 (ko) 볼 그리드 어레이 반도체패키지의 솔더링 방법
TW200839969A (en) Semiconductor package and the method for manufacturing the same

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20160112

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160119

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160407

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20160913

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20161208

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170328

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170427

R150 Certificate of patent or registration of utility model

Ref document number: 6139578

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250