JP5544326B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5544326B2 JP5544326B2 JP2011084186A JP2011084186A JP5544326B2 JP 5544326 B2 JP5544326 B2 JP 5544326B2 JP 2011084186 A JP2011084186 A JP 2011084186A JP 2011084186 A JP2011084186 A JP 2011084186A JP 5544326 B2 JP5544326 B2 JP 5544326B2
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- transistor
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Description
本実施の形態では、図1(A)に示す半導体メモリ回路の動作の例について、図1(B)乃至図1(E)を用いて説明する。なお、電位として、以下に具体的な数値を挙げるが、それは、本発明の技術思想の理解を助けることが目的である。言うまでもなく、それらの値はトランジスタやキャパシタのさまざまな特性によって、あるいは実施者の都合によって変更される。また、図1(A)に示される半導体メモリ回路は、以下の方法以外の方法によっても、データを書き込み、あるいは読み出すことができる。
本実施の形態では、図2(A)に示す半導体メモリ回路の動作の例について、図3および図4を用いて説明する。なお、電位として、以下に具体的な数値を挙げるが、それは、本発明の技術思想の理解を助けることが目的である。言うまでもなく、それらの値はトランジスタやキャパシタのさまざまな特性によって、あるいは実施者の都合によって変更される。また、図2(A)に示される半導体メモリ回路は、以下の方法以外の方法によっても、データを書き込み、あるいは読み出すことができる。
本実施の形態では、実施の形態2で説明した半導体メモリ装置の形状や作製方法の例について説明する。本実施の形態では、書き込みトランジスタは、ガリウムとインジウムを含有する酸化物半導体を用い、読み出しトランジスタとしては、単結晶シリコン半導体を用いる。そのため、書き込みトランジスタは読み出しトランジスタの上に積層して設けられる。
まず、公知の半導体製造技術を用いて、n型の単結晶シリコン基板101上に、図9(A)に示すように、素子分離領域102、p型にドーピングされたシリコンによる導電性領域106、ゲート絶縁膜103、ダミーゲート104、層間絶縁物107を形成する。ダミーゲート104の側面には、図に示すようにサイドウォールを設けてもよい。
層間絶縁物107の表面が十分に平坦である場合には、ドライエッチング法により、層間絶縁物107をエッチングし、ダミーゲート104の上面が現れた時点でドライエッチングをやめる。ドライエッチング法の代わりに化学的機械的研磨(CMP)法を用いてもよいし、最初にCMP法で層間絶縁物107の表面を平坦にした後、ドライエッチング法で、さらにエッチングを進めてもよい。あるいは逆に、ドライエッチング法である程度、層間絶縁物をエッチングした後、CMP法で平坦化処理してもよい。かくして、層間絶縁物107を加工して、平坦な表面を有する層間絶縁物107aを得るとともに、ダミーゲート104の表面を露出せしめる。
次に、層間絶縁物107aを選択的にエッチングして、シリサイド領域105に達する開口部108を形成する。
さらに、ダミーゲート104を選択的にエッチングして、開口部109を形成する。ダミーゲート104の材料として多結晶シリコンを使用している場合には、2乃至40%、好ましくは、20乃至25%のTMAH(水酸化テトラメチルアンモニウム)を用いればよい。
単層あるいは多層の導電性材料の膜を堆積する。導電性材料としては、後に形成する酸化物半導体とオーミック接触を形成する材料が好ましい。また、この導電膜は、読み出しトランジスタ(ここではPチャネル型)のゲート電極でもあるので、そのしきい値を決定する上でも、仕事関数等の物性値が適切なものが好ましい。ひとつの材料で、これら2つの要件を満たせない場合は多層の膜にして、それぞれの条件を満足するようにすればよい。例えば、導電性材料として窒化チタンと窒化タンタルの多層膜を用いるとよい。
厚さ3乃至20nmの酸化物半導体膜をスパッタ法により形成する。酸化物半導体膜の作製方法はスパッタ法以外でもよい。酸化物半導体はガリウムとインジウムを含むことが好ましい。半導体メモリ装置の信頼性を高めるためには、酸化物半導体膜中の水素濃度は、1×1018cm−3未満、好ましくは1×1016cm−3未満とするとよい。組成比ガリウム/インジウムは、0.5以上2未満、好ましくは、0.9以上1.2未満とするとよい。ガリウム、インジウム以外に亜鉛を含んでもよい。
導電性材料により複数の配線114を形成する。配線114は、書き込みワード線Q1、Q2や読み出しワード線P1となる。書き込みワード線Q1、Q2の一部は酸化物半導体を用いたトランジスタのゲート電極となる。配線114の材料としては、その仕事関数が酸化物半導体の電子親和力より0.5eV以上高い材料が好ましい。例えば、タングステン、金、白金、p型シリコン等である。
その後、単層もしくは多層の薄膜よりなる層間絶縁物116を形成する。そして、その表面を平坦化し、選択的にエッチングして、n型の導電性を示す領域115に達するコンタクトホールを形成し、接続電極117を埋め込む。その後、配線118を形成する。配線118はビット線Rである。同様な配線を、配線114、あるいは、バイアス線Sと平行に形成してもよい。かくして、図10(D)に示されるように、書き込みトランジスタ119、読み出しトランジスタ120、キャパシタ121を有する半導体メモリ装置の記憶セルおよびそれらを有する記憶ユニットが作製される。
本実施の形態では、図2(B)に示す半導体メモリ回路の動作の例について、図6および図7を用いて説明する。なお、電位として、以下に具体的な数値を挙げるが、それは、本発明の技術思想の理解を助けることが目的である。言うまでもなく、それらの値はトランジスタやキャパシタのさまざまな特性によって、あるいは実施者の都合によって変更される。また、図2(B)に示される半導体メモリ回路は、以下の方法以外の方法によっても、データを書き込み、あるいは読み出すことができる。
本実施の形態では、実施の形態4で説明した半導体メモリ装置の形状について説明する。図11に本実施の形態の半導体メモリ装置の記憶ユニットのレイアウト例を示す。本実施の形態では、単位記憶ユニットに6つの記憶セルを有する。本実施の形態で示す半導体メモリ装置は、配線のパターン等は異なるが、実施の形態3で示した方法により作製できる。
本実施の形態では、図12(A)に示す半導体メモリ回路の動作の例について、図12(B)乃至図12(E)を用いて説明する。なお、電位として、以下に具体的な数値を挙げるが、それは、本発明の技術思想の理解を助けることが目的である。言うまでもなく、それらの値はトランジスタやキャパシタのさまざまな特性によって、あるいは実施者の都合によって変更される。また、図12(A)に示される半導体メモリ回路は、以下の方法以外の方法によっても、データを書き込み、あるいは読み出すことができる。
本実施の形態では、図13(A)に示す半導体メモリ回路の動作の例について、図14および図15を用いて説明する。なお、電位として、以下に具体的な数値を挙げるが、それは、本発明の技術思想の理解を助けることが目的である。言うまでもなく、それらの値はトランジスタやキャパシタのさまざまな特性によって、あるいは実施者の都合によって変更される。また、図13(A)に示される半導体メモリ装置は、以下の方法以外の方法によっても、データを書き込み、あるいは読み出すことができる。
本実施の形態では、実施の形態7で説明した半導体メモリ装置の形状の例について説明する。本実施の形態では、書き込みトランジスタは、ガリウムとインジウムを含有する酸化物半導体を用い、読み出しトランジスタとしては、単結晶シリコン半導体を用いる。そのため、実施の形態3と同様に書き込みトランジスタは読み出しトランジスタの上に積層して設けられる。
本実施の形態では、図17(A)に示す半導体メモリ回路の動作の例について、図18および図19を用いて説明する。図17(A)の回路と図17(B)の回路の違いは、全く同じ動作をする選択トランジスタを2つ設けるのか、1つ設けるのか、ということだけであるので、図17(B)の回路においても、以下の方法で同様に書き込みや読み出しをおこなうことができる。
本実施の形態では、実施の形態9で動作を説明した半導体メモリ装置の形状について説明する。図21に本実施の形態の半導体メモリ装置の記憶ユニットのレイアウト例を示す。本実施の形態では、単位記憶ユニットに6つの記憶セルを有する。本実施の形態で示す半導体メモリ装置は、配線のパターン等は異なるが、実施の形態3で示した方法により作製できる。
本実施の形態では、実施の形態1乃至5に示した半導体メモリ装置を用いた電子機器について説明する。これらの半導体メモリ装置は、パーソナルコンピュータ、携帯通信機器、映像表示装置、電子書籍等の機器に用いることができる。
102 素子分離領域
103 ゲート絶縁膜
104 ダミーゲート
105 シリサイド領域
106 導電性領域
106a 導電性領域
107 層間絶縁物
107a 層間絶縁物
108 開口部
109 開口部
110 接続電極
110a 接続電極
111 ゲート電極
111a ゲート電極
111b 第1のゲート電極
111c 第2のゲート電極
111d 第3のゲート電極
111e 第4のゲート電極
112 酸化物半導体領域
113 ゲート絶縁膜
114 配線
114a 配線
115 n型の導電性を示す領域
116 層間絶縁物
117 接続電極
118 配線
119 書き込みトランジスタ
120 読み出しトランジスタ
121 キャパシタ
WTr 書き込みトランジスタ
WTr1 書き込みトランジスタ
WTr2 書き込みトランジスタ
WTr3 書き込みトランジスタ
WTr4 書き込みトランジスタ
RTr 読み出しトランジスタ
RTr1 読み出しトランジスタ
RTr2 読み出しトランジスタ
RTr3 読み出しトランジスタ
RTr4 読み出しトランジスタ
STr 選択トランジスタ
STr1 選択トランジスタ
STr2 選択トランジスタ
C キャパシタ
C1 キャパシタ
C2 キャパシタ
C3 キャパシタ
C4 キャパシタ
Tr0 トランジスタ
F1 ノード
F2 ノード
F3 ノード
F4 ノード
P 読み出しワード線
P1 読み出しワード線
P2 読み出しワード線
P3 読み出しワード線
Q 書き込みワード線
Q1 書き込みワード線
Q2 書き込みワード線
Q3 書き込みワード線
Q4 書き込みワード線
Q5 書き込みワード線
Q6 書き込みワード線
R ビット線
S バイアス線
T 選択線
Claims (1)
- 第1のトランジスタと、
第2のトランジスタと、
第3のトランジスタと、
第4のトランジスタと、
第1の容量と、
第2の容量と、を有し、
前記第1のトランジスタは、書き込み用トランジスタとして機能することができ、
前記第2のトランジスタは、読み出し用トランジスタとして機能することができ、
前記第3のトランジスタは、読み出し用トランジスタとして機能することができ、
前記第4のトランジスタは、書き込み用トランジスタとして機能することができ、
前記第1のトランジスタのソース又はドレインの一方は、前記第2のトランジスタのゲートと電気的に接続され、
前記第1のトランジスタのソース又はドレインの一方は、前記第1の容量の一方の電極と電気的に接続され、
前記第1の容量の他方の電極は、第1の配線と電気的に接続され、
前記第1のトランジスタのソース又はドレインの一方は、前記第4のトランジスタのソース又はドレインの一方と電気的に接続され、
前記第4のトランジスタのソース又はドレインの他方は、前記第3のトランジスタのゲートと電気的に接続され、
前記第4のトランジスタのソース又はドレインの他方は、前記第2の容量の一方の電極と電気的に接続され、
前記第2の容量の他方の電極は、第2の配線と電気的に接続され、
前記第2のトランジスタのソース又はドレインの一方は、前記第3のトランジスタのソース又はドレインの一方と電気的に接続され、
前記第1のトランジスタは、ガリウムとインジウムとを有する、第1の酸化物半導体を有し、
前記第4のトランジスタは、ガリウムとインジウムとを有する、第2の酸化物半導体を有し、
前記第2のトランジスタは、シリコンを有する半導体を有し、
前記第3のトランジスタは、シリコンを有する半導体を有し、
前記第1の容量は、前記第2のトランジスタのゲートと、前記第1の酸化物半導体と、前記第1の配線とが重なる領域に設けられ、
前記第2の容量は、前記第3のトランジスタのゲートと、前記第2の酸化物半導体と、前記第2の配線とが重なる領域に設けられていることを特徴とする半導体装置。
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KR101904445B1 (ko) * | 2010-04-16 | 2018-10-04 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
WO2011135999A1 (en) * | 2010-04-27 | 2011-11-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor memory device |
US8537600B2 (en) * | 2010-08-04 | 2013-09-17 | Semiconductor Energy Laboratory Co., Ltd. | Low off-state leakage current semiconductor memory device |
US8634228B2 (en) * | 2010-09-02 | 2014-01-21 | Semiconductor Energy Laboratory Co., Ltd. | Driving method of semiconductor device |
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2011
- 2011-03-09 WO PCT/JP2011/056131 patent/WO2011125432A1/en active Application Filing
- 2011-03-09 KR KR1020127029086A patent/KR101884031B1/ko active IP Right Grant
- 2011-03-30 TW TW100111018A patent/TWI508267B/zh not_active IP Right Cessation
- 2011-03-31 US US13/076,787 patent/US8472231B2/en active Active
- 2011-04-06 JP JP2011084186A patent/JP5544326B2/ja not_active Expired - Fee Related
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2013
- 2013-10-11 JP JP2013213640A patent/JP2014041689A/ja not_active Withdrawn
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011204347A (ja) * | 2010-03-04 | 2011-10-13 | Semiconductor Energy Lab Co Ltd | 半導体メモリ装置および半導体メモリ装置の駆動方法 |
JP2014160535A (ja) * | 2010-04-07 | 2014-09-04 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
Also Published As
Publication number | Publication date |
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JP5865421B2 (ja) | 2016-02-17 |
TWI508267B (zh) | 2015-11-11 |
WO2011125432A1 (en) | 2011-10-13 |
TW201210002A (en) | 2012-03-01 |
KR101884031B1 (ko) | 2018-07-31 |
JP2014160535A (ja) | 2014-09-04 |
KR20130042486A (ko) | 2013-04-26 |
JP2011238333A (ja) | 2011-11-24 |
JP2014041689A (ja) | 2014-03-06 |
US20110249484A1 (en) | 2011-10-13 |
US8472231B2 (en) | 2013-06-25 |
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