JP5210518B2 - 一体化逆並列接合障壁ショットキーダイオードを備えた炭化珪素mosfetおよびその製造方法 - Google Patents
一体化逆並列接合障壁ショットキーダイオードを備えた炭化珪素mosfetおよびその製造方法 Download PDFInfo
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- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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Description
Claims (40)
- 炭化珪素DMOSFETと、
前記DMOSFETの内蔵ボディダイオードのターンオン電圧より低いターンオン電圧を有する構成の一体型炭化珪素接合障壁ショットキー(JBS)ダイオードと
を備え、
前記炭化珪素JBSダイオードは、前記DMOSFETのソース領域に隣接する複数の離隔されたp型炭化珪素領域を含むp型JBSグリッドの周辺のp型領域と、前記ソース領域に隣接または非常に近くにかつ結合されたショットキーコンタクトをさらに含み、
前記DMOSFETのソースコンタクトは、前記JBSグリッドの周辺のp型領域の一部上にも存在し、
前記JBSグリッドの周辺のp型領域は、前記DMOSFETのソースコンタクトに対するオーミックコンタクトを有し、かつ前記DMOSFETのp型ウエル領域と接触することを特徴とする炭化珪素半導体装置。 - 前記一体型JBSダイオードは、1ボルトのターンオン電圧を有することを特徴とする請求項1に記載の炭化珪素半導体装置。
- 前記炭化珪素JBSダイオードは、
前記DMOSFETのドリフト領域と共通のドリフト領域と、
前記DMOSFETのドレインコンタクトと共通の第2のコンタクトと
を備えたことを特徴とする請求項1に記載の炭化珪素半導体装置。 - 前記p型接合障壁ショットキー(JBS)グリッドは、1x1018〜1x1020cm−3のドーピング濃度を有する複数の離隔されたp型炭化珪素領域を有することを特徴とする請求項3に記載の炭化珪素半導体装置。
- 前記ショットキーコンタクトは、前記ソース領域と直接コンタクト状態にあることを特徴とする請求項3に記載の炭化珪素半導体装置。
- 前記ショットキーコンタクトは、前記DMOSFETのソースコンタクトを介して、前記ソース領域に結合されることを特徴とする請求項3に記載の炭化珪素半導体装置。
- 前記一体型炭化珪素JBSダイオードの活性領域は、前記炭化珪素DMOSFETの活性領域より狭いことを特徴とする請求項1に記載の炭化珪素半導体装置。
- 前記一体型炭化珪素JBSダイオードの活性領域は、前記炭化珪素DMOSFETの活性領域の50%より狭いことを特徴とする請求項1に記載の炭化珪素半導体装置。
- 前記一体型炭化珪素JBSダイオードの活性領域は、前記炭化珪素DMOSFETの活性領域の25%より狭いことを特徴とする請求項1に記載の炭化珪素半導体装置。
- 前記一体型炭化珪素JBSダイオードの活性領域は、前記炭化珪素DMOSFETの活性領域の20%より狭いことを特徴とする請求項1に記載の炭化珪素半導体装置。
- 前記一体型炭化珪素JBSダイオードの活性領域は、2.6V以下の順バイアス電圧で、前記DMOSFETの全スイッチ電流を流すように選択されることを特徴とする請求項1に記載の炭化珪素半導体装置。
- 炭化珪素半導体装置であって、
第1のn型炭化珪素層と、
前記第1のn型炭化珪素層内にあり、かつ前記第1のn型炭化珪素層の第1の表面に伸びるp型炭化珪素ウエル領域と、
p型炭化珪素ウエル領域の一部に隣接する前記第1のn型炭化珪素層内の第2のn型炭化珪素層であって、前記第1のn型炭化珪素層の第1の表面に伸び、かつ前記第1のn型炭化珪素層のキャリア濃度より高いキャリア濃度を有する第2のn型炭化珪素層と、
前記第1のn型炭化珪素層、前記第2のn型炭化珪素層、および前記p型炭化珪素ウエル領域上のゲート絶縁層と、
前記第1のn型炭化珪素内にあって、接合障壁グリッドを提供する複数の離隔されたp型炭化珪素領域であって、前記複数の離隔されたp型炭化珪素領域の周辺の1つは、前記第2のn型炭化珪素領域と前記p型炭化珪素ウエル領域に隣接する複数の離隔されたp型炭化珪素領域と、
前記第1のn型炭化珪素層、および前記複数のp型炭化珪素領域上のショットキーコンタクトと、
前記ショットキーコンタクトに隣接し、かつ前記第2のn型炭化珪素層上のソースコンタクトと、
前記ゲート絶縁層上のゲートコンタクトと、
前記第1のn型炭化珪素層の第1の表面の反対側の第1のn型炭化珪素層上のドレインコンタクトと
を備え、
前記複数のp型炭化珪素領域の周辺の1つは、前記p型炭化珪素ウエル領域に接触し、
前記ソースコンタクトは、前記複数のp型炭化珪素領域の周辺の1つの一部上にも存在し、
前記炭化珪素半導体装置は、前記接合障壁グリッドおよび前記ショットキーコンタクトを備えるショットキーダイオードを有し、前記ショットキーダイオードは、炭化珪素の前記第1のn型層および前記p型ウエル領域の内蔵pn接合のターンオン電圧未満のターンオン電圧を有することを特徴とする炭化珪素半導体装置。 - 前記ドレインコンタクトと前記第1のn型炭化珪素層間に配置された、前記第1のn型炭化珪素層のキャリア濃度より高いキャリア濃度を有する第3のn型炭化珪素層をさらに備えたことを特徴とする請求項12に記載の炭化珪素半導体装置。
- 前記ソースコンタクトを前記ショットキーコンタクトに接続するように、前記ソースコンタクトおよびショットキーコンタクトの上に金属オーバーレイをさらに設けたことを特徴とする請求項12に記載の炭化珪素半導体装置。
- 前記複数の離隔されたp型炭化珪素領域は、前記p型炭化珪素ウエル領域のドーピング濃度より高いドーピング濃度を有することを特徴とする請求項12に記載の炭化珪素半導体装置。
- 前記第1のn型炭化珪素層は、5x1014〜2x1016cm−3のドーピング濃度を有することを特徴とする請求項12に記載の炭化珪素半導体装置。
- 前記第1のn型炭化珪素層は、5〜30μmの厚さを有することを特徴とする請求項12に記載の炭化珪素半導体装置。
- 前記p型炭化珪素ウエル領域は、1016〜1020cm−3のドーピング濃度を有することを特徴とする請求項12に記載の炭化珪素半導体装置。
- 前記p型炭化珪素ウエル領域は、第1のn型炭化珪素層中に0.5〜1.5μmの深さに伸びることを特徴とする請求項12に記載の炭化珪素半導体装置。
- 前記複数の離隔されたp型炭化珪素領域は、1018〜1020cm−3のドーピング濃度を有することを特徴とする請求項12に記載の炭化珪素半導体装置。
- 前記複数の離隔されたp型炭化珪素領域は、0.5〜10μmの距離間隔をおいて配置されることを特徴とする請求項12に記載の炭化珪素半導体装置。
- 前記複数の離隔されたp型炭化珪素領域は、均一に離隔されることを特徴とする請求項12に記載の炭化珪素半導体装置。
- 前記複数の離隔されたp型炭化珪素領域は、不均一に離隔されることを特徴とする請求項12に記載の炭化珪素半導体装置。
- 前記複数の離隔されたp型炭化珪素領域は、0.5〜10μmのそれぞれの幅を有することを特徴とする請求項12に記載の炭化珪素半導体装置。
- 前記第2のn型炭化珪素層は、1019〜1021cm−3のドーピング濃度を有することを特徴とする請求項12に記載の炭化珪素半導体装置。
- 前記第2のn型炭化珪素層は、前記第1のn型炭化珪素層中に0.1〜0.7μmの深さに伸びることを特徴とする請求項12に記載の炭化珪素半導体装置。
- 炭化珪素DMOSFETを形成するステップと、
前記DMOSFETの内蔵ボディダイオードのターンオン電圧より低いターンオン電圧を有する構成の一体型炭化珪素接合障壁ショットキー(JBS)ダイオードを形成するステップと
を有し、
前記炭化珪素JBSダイオードを形成するステップは、前記DMOSFETのソース領域に隣接する複数の離隔されたp型炭化珪素領域を含むp型JBSグリッドと、前記ソース領域に隣接または非常に近くにかつ結合されたショットキーコンタクトとを形成するステップをさらに有し、
前記p型JBSグリッドを形成するステップは、前記JBSグリッドの周辺のp型領域を形成するステップを含み、
前記DMOSFETのソースコンタクトは、前記JBSグリッドの周辺のp型領域の一部上にも存在し、
前記JBSグリッドの周辺のp型領域は、前記DMOSFETのソースコンタクトに対するオーミックコンタクトを有し、かつ前記DMOSFETのp型ウエル領域と接触することを特徴とする炭化珪素半導体装置の製造方法。 - 前記一体型JBSダイオードを形成するステップは、1ボルトのターンオン電圧を有する一体型JBSダイオードを形成するステップを備えることを特徴とする請求項27に記載の方法。
- 前記炭化珪素ショットキーダイオードを形成するステップは、
前記DMOSFETのドリフト領域と共通のドリフト領域を形成するステップと、
前記DMOSFETのドレインコンタクトと共通の第2のコンタクトを形成するステップと
を有することを特徴とする請求項27に記載の方法。 - 前記p型接合障壁ショットキー(JBS)グリッドは、1x1018〜1x1020cm−3のドーピング濃度を有する複数の離隔されたp型炭化珪素領域を有することを特徴とする請求項29に記載の方法。
- 前記ショットキーコンタクトを形成するステップは、前記ソース領域と直接コンタクト状態にあるショットキーコンタクトを形成するステップを含むことを特徴とする請求項29に記載の方法。
- 前記ショットキーコンタクトを形成するステップは、前記DMOSFETのソースコンタクトを介して前記ソース領域に結合されるショットキーコンタクトを形成するステップを含むことを特徴とする請求項29に記載の方法。
- 前記一体型炭化珪素JBSダイオードを形成するステップは、前記炭化珪素DMOSFETの活性領域より狭い活性領域を有する一体型炭化珪素JBSダイオードを形成するステップを含むことを特徴とする請求項27に記載の方法。
- 前記炭化珪素JBSダイオードを形成するステップは、前記炭化珪素DMOSFETの活性領域の50%より狭い活性領域を有する一体型炭化珪素JBSダイオードを形成するステップを含むことを特徴とする請求項27に記載の方法。
- 前記炭化珪素JBSダイオードを形成するステップは、前記炭化珪素DMOSFETの活性領域の25%より狭い活性領域を有する一体型炭化珪素JBSダイオードを形成するステップを含むことを特徴とする請求項27に記載の方法。
- 前記炭化珪素JBSダイオードを形成するステップは、前記炭化珪素DMOSFETの活性領域の20%より狭い活性領域を有する一体型炭化珪素JBSダイオードを形成するステップを含むことを特徴とする請求項27に記載の方法。
- 第1のn型炭化珪素層を形成するステップと、
前記第1のn型炭化珪素層内にあり、かつ前記第1のn型炭化珪素層の第1の表面に伸びるp型炭化珪素ウエル領域を形成するステップと、
p型炭化珪素ウエル領域の一部に隣接する前記第1のn型炭化珪素層内の第2のn型炭化珪素層であって、前記第1のn型炭化珪素層の第1の表面に伸び、かつ前記第1のn型炭化珪素層のキャリア濃度より高いキャリア濃度を有する第2のn型炭化珪素層を形成するステップと、
前記第1のn型炭化珪素層、前記第2のn型炭化珪素層、および前記p型炭化珪素ウエル領域上のゲート絶縁層を形成するステップと、
前記第1のn型炭化珪素内にあり、接合障壁グリッドを提供する複数の離隔されたp型型炭化珪素領域であって、前記複数の離隔されたp型炭化珪素領域の周辺の1つは、前記第2のn型炭化珪素領域と前記p型炭化珪素ウエル領域に隣接する複数の離隔されたp型炭化珪素領域を形成するステップと、
前記第1のn型炭化珪素層および前記複数のp型炭化珪素領域上にショットキーコンタクトを形成するステップと、
前記ショットキーコンタクトに隣接し、かつ前記第2のn型炭化珪素層上にソースコンタクトを形成するステップと、
前記ゲート絶縁層上にゲートコンタクトを形成するステップと、
前記第1のn型炭化珪素層の第1の表面の反対側の第1のn型炭化珪素層上にドレインコンタクトを形成するステップと
を有し、
前記複数の離隔されたp型炭化珪素領域を形成するステップは、前記複数のp型炭化珪素領域の周辺の1つは、前記p型炭化珪素ウエル領域に接触するように、複数の離隔されたp型炭化珪素領域を形成するステップを含み、前記ソースコンタクトを形成するステップは、前記複数のp型炭化珪素領域の周辺の1つの一部上に存在するソースコンタクトを形成するステップをさらに含み、
前記炭化珪素半導体装置は、前記接合障壁グリッドおよび前記ショットキーコンタクトを備えるショットキーダイオードを有し、前記ショットキーダイオードは、炭化珪素の前記第1のn型層および前記p型ウエル領域の内蔵pn接合のターンオン電圧未満のターンオン電圧を有することを特徴とする炭化珪素半導体装置の製造方法。 - 前記ドレインコンタクトと前記第1のn型炭化珪素層間に配置された第3のn型炭化珪素層であって、第1のn型炭化珪素層のキャリア濃度より高いキャリア濃度を有する第3のn型炭化珪素層を形成するステップをさらに有することを特徴とする請求項37に記載の炭化珪素半導体装置の製造方法。
- 前記ソースコンタクトを前記ショットキーコンタクトに接続するように、前記ソースコンタクトおよびショットキーコンタクトの上に金属オーバーレイをさらに設けたことを特徴とする請求項37に記載の方法。
- 前記複数の離隔されたp型炭化珪素領域は、前記p型炭化珪素ウエル領域のドーピング濃度より高いドーピング濃度を有することを特徴とする請求項39に記載の方法。
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2003
- 2003-04-24 US US10/422,554 patent/US6979863B2/en not_active Expired - Lifetime
-
2004
- 2004-02-17 TW TW093103780A patent/TWI352421B/zh not_active IP Right Cessation
- 2004-02-19 EP EP04712840A patent/EP1616356A2/en not_active Ceased
- 2004-02-19 WO PCT/US2004/004892 patent/WO2004097944A2/en active Search and Examination
- 2004-02-19 JP JP2006508767A patent/JP5210518B2/ja not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9887285B1 (en) | 2016-09-21 | 2018-02-06 | Kabushiki Kaisha Toshiba | Semiconductor device |
US10432190B2 (en) | 2016-09-21 | 2019-10-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method for controlling semiconductor device |
US10396072B2 (en) | 2017-09-19 | 2019-08-27 | Kabushiki Kaisha Toshiba | Semiconductor device |
US10297685B2 (en) | 2017-09-20 | 2019-05-21 | Kabushiki Kaisha Toshiba | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
TWI352421B (en) | 2011-11-11 |
US20040212011A1 (en) | 2004-10-28 |
US6979863B2 (en) | 2005-12-27 |
WO2004097944A2 (en) | 2004-11-11 |
JP2006524432A (ja) | 2006-10-26 |
EP1616356A2 (en) | 2006-01-18 |
WO2004097944A3 (en) | 2004-12-23 |
TW200428644A (en) | 2004-12-16 |
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