ITMI20042243A1 - Processo per la realizzazione di un dispositivo mos di potenza ad alta densita' di integrazione - Google Patents

Processo per la realizzazione di un dispositivo mos di potenza ad alta densita' di integrazione

Info

Publication number
ITMI20042243A1
ITMI20042243A1 IT002243A ITMI20042243A ITMI20042243A1 IT MI20042243 A1 ITMI20042243 A1 IT MI20042243A1 IT 002243 A IT002243 A IT 002243A IT MI20042243 A ITMI20042243 A IT MI20042243A IT MI20042243 A1 ITMI20042243 A1 IT MI20042243A1
Authority
IT
Italy
Prior art keywords
realization
high density
power device
density mos
intension
Prior art date
Application number
IT002243A
Other languages
English (en)
Inventor
Giuseppe Arena
Marco Camalleri
Giuseppe Ferla
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT002243A priority Critical patent/ITMI20042243A1/it
Publication of ITMI20042243A1 publication Critical patent/ITMI20042243A1/it
Priority to EP05025287A priority patent/EP1659637B1/en
Priority to DE602005025845T priority patent/DE602005025845D1/de
Priority to EP10011934A priority patent/EP2302684A3/en
Priority to US11/285,759 priority patent/US7569883B2/en
Priority to US11/285,741 priority patent/US7875936B2/en
Priority to US11/285,742 priority patent/US7601610B2/en
Priority to US12/551,999 priority patent/US8013384B2/en
Priority to US12/967,845 priority patent/US8420487B2/en
Priority to US12/967,861 priority patent/US8482085B2/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
IT002243A 2004-11-19 2004-11-19 Processo per la realizzazione di un dispositivo mos di potenza ad alta densita' di integrazione ITMI20042243A1 (it)

Priority Applications (10)

Application Number Priority Date Filing Date Title
IT002243A ITMI20042243A1 (it) 2004-11-19 2004-11-19 Processo per la realizzazione di un dispositivo mos di potenza ad alta densita' di integrazione
EP05025287A EP1659637B1 (en) 2004-11-19 2005-11-18 Method of manufacturing a power MOS device
DE602005025845T DE602005025845D1 (de) 2004-11-19 2005-11-18 Verfahren zur Herstellung einer MOS-Leistungsanordnung
EP10011934A EP2302684A3 (en) 2004-11-19 2005-11-18 Power MOS device
US11/285,759 US7569883B2 (en) 2004-11-19 2005-11-21 Switching-controlled power MOS electronic device
US11/285,741 US7875936B2 (en) 2004-11-19 2005-11-21 Power MOS electronic device and corresponding realizing method
US11/285,742 US7601610B2 (en) 2004-11-19 2005-11-21 Method for manufacturing a high integration density power MOS device
US12/551,999 US8013384B2 (en) 2004-11-19 2009-09-01 Method for manufacturing a high integration density power MOS device
US12/967,845 US8420487B2 (en) 2004-11-19 2010-12-14 Power MOS electronic device and corresponding realizing method
US12/967,861 US8482085B2 (en) 2004-11-19 2010-12-14 Power MOS electronic device and corresponding realizing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT002243A ITMI20042243A1 (it) 2004-11-19 2004-11-19 Processo per la realizzazione di un dispositivo mos di potenza ad alta densita' di integrazione

Publications (1)

Publication Number Publication Date
ITMI20042243A1 true ITMI20042243A1 (it) 2005-02-19

Family

ID=36088155

Family Applications (1)

Application Number Title Priority Date Filing Date
IT002243A ITMI20042243A1 (it) 2004-11-19 2004-11-19 Processo per la realizzazione di un dispositivo mos di potenza ad alta densita' di integrazione

Country Status (4)

Country Link
US (2) US7601610B2 (it)
EP (2) EP1659637B1 (it)
DE (1) DE602005025845D1 (it)
IT (1) ITMI20042243A1 (it)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9178054B2 (en) 2013-12-09 2015-11-03 Micrel, Inc. Planar vertical DMOS transistor with reduced gate charge
US9184278B2 (en) * 2013-12-09 2015-11-10 Micrel, Inc. Planar vertical DMOS transistor with a conductive spacer structure as gate
US9607635B1 (en) * 2016-04-22 2017-03-28 International Business Machines Corporation Current perpendicular-to-plane sensors having hard spacers
US9947348B1 (en) 2017-02-28 2018-04-17 International Business Machines Corporation Tunnel magnetoresistive sensor having leads supporting three-dimensional current flow
US10803889B2 (en) 2019-02-21 2020-10-13 International Business Machines Corporation Apparatus with data reader sensors more recessed than servo reader sensor
US11074930B1 (en) 2020-05-11 2021-07-27 International Business Machines Corporation Read transducer structure having an embedded wear layer between thin and thick shield portions
US11114117B1 (en) 2020-05-20 2021-09-07 International Business Machines Corporation Process for manufacturing magnetic head having a servo read transducer structure with dielectric gap liner and a data read transducer structure with an embedded wear layer between thin and thick shield portions

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US4055884A (en) 1976-12-13 1977-11-01 International Business Machines Corporation Fabrication of power field effect transistors and the resulting structures
US4318759A (en) * 1980-07-21 1982-03-09 Data General Corporation Retro-etch process for integrated circuits
US4748103A (en) * 1986-03-21 1988-05-31 Advanced Power Technology Mask-surrogate semiconductor process employing dopant protective region
EP0518418A1 (en) * 1991-06-10 1992-12-16 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device whereby field oxide regions are formed in a surface of a silicon body through oxidation
US5430314A (en) 1992-04-23 1995-07-04 Siliconix Incorporated Power device with buffered gate shield region
EP1408542A3 (en) 1994-07-14 2009-01-21 STMicroelectronics S.r.l. High-speed MOS-technology power device integrated structure, and related manufacturing process
US5795793A (en) * 1994-09-01 1998-08-18 International Rectifier Corporation Process for manufacture of MOS gated device with reduced mask count
US5510281A (en) * 1995-03-20 1996-04-23 General Electric Company Method of fabricating a self-aligned DMOS transistor device using SiC and spacers
JP3166148B2 (ja) 1995-07-11 2001-05-14 横河電機株式会社 半導体装置
EP0772242B1 (en) * 1995-10-30 2006-04-05 STMicroelectronics S.r.l. Single feature size MOS technology power device
DE69631524T2 (de) 1996-07-05 2004-10-07 St Microelectronics Srl Asymmetrische MOS-Technologie-Leistungsanordnung
US6025230A (en) * 1997-11-06 2000-02-15 Mageposer Semiconductor Corporation High speed MOSFET power device with enhanced ruggedness fabricated by simplified processes
US6187694B1 (en) * 1997-11-10 2001-02-13 Intel Corporation Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer
GB9726829D0 (en) 1997-12-19 1998-02-18 Philips Electronics Nv Power semiconductor devices
US6107649A (en) * 1998-06-10 2000-08-22 Rutgers, The State University Field-controlled high-power semiconductor devices
US6215152B1 (en) * 1998-08-05 2001-04-10 Cree, Inc. MOSFET having self-aligned gate and buried shield and method of making same
KR20000051294A (ko) * 1999-01-20 2000-08-16 김덕중 전기적 특성이 향상된 디모스 전계 효과 트랜지스터 및 그 제조 방법
JP4917709B2 (ja) 2000-03-06 2012-04-18 ローム株式会社 半導体装置
US6710405B2 (en) 2001-01-17 2004-03-23 Ixys Corporation Non-uniform power semiconductor device
US6756644B2 (en) * 2001-03-28 2004-06-29 International Rectifier Corporation Ultra low QGD power MOSFET
DE10131917A1 (de) * 2001-07-02 2003-01-23 Infineon Technologies Ag Verfahren zur Erzeugung einer stufenförmigen Struktur auf einem Substrat
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US7045845B2 (en) * 2002-08-16 2006-05-16 Semiconductor Components Industries, L.L.C. Self-aligned vertical gate semiconductor device
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Also Published As

Publication number Publication date
US8013384B2 (en) 2011-09-06
DE602005025845D1 (de) 2011-02-24
EP1659637B1 (en) 2011-01-12
EP1659637A2 (en) 2006-05-24
EP2302684A2 (en) 2011-03-30
US20090321826A1 (en) 2009-12-31
EP2302684A3 (en) 2012-03-14
EP1659637A3 (en) 2006-07-19
US20060138537A1 (en) 2006-06-29
US7601610B2 (en) 2009-10-13

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