DE69631524T2 - Asymmetrische MOS-Technologie-Leistungsanordnung - Google Patents

Asymmetrische MOS-Technologie-Leistungsanordnung Download PDF

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Publication number
DE69631524T2
DE69631524T2 DE69631524T DE69631524T DE69631524T2 DE 69631524 T2 DE69631524 T2 DE 69631524T2 DE 69631524 T DE69631524 T DE 69631524T DE 69631524 T DE69631524 T DE 69631524T DE 69631524 T2 DE69631524 T2 DE 69631524T2
Authority
DE
Germany
Prior art keywords
technology power
power arrangement
mos technology
asymmetric mos
asymmetric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69631524T
Other languages
English (en)
Other versions
DE69631524D1 (de
Inventor
Angelo Magri
Raffaele Zambrano
Ferruccio Frisina
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Publication of DE69631524D1 publication Critical patent/DE69631524D1/de
Application granted granted Critical
Publication of DE69631524T2 publication Critical patent/DE69631524T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69631524T 1996-07-05 1996-07-05 Asymmetrische MOS-Technologie-Leistungsanordnung Expired - Fee Related DE69631524T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP96830384A EP0817274B1 (de) 1996-07-05 1996-07-05 Asymmetrische MOS-Technologie-Leistungsanordnung

Publications (2)

Publication Number Publication Date
DE69631524D1 DE69631524D1 (de) 2004-03-18
DE69631524T2 true DE69631524T2 (de) 2004-10-07

Family

ID=8225959

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69631524T Expired - Fee Related DE69631524T2 (de) 1996-07-05 1996-07-05 Asymmetrische MOS-Technologie-Leistungsanordnung

Country Status (4)

Country Link
US (2) US6222232B1 (de)
EP (1) EP0817274B1 (de)
JP (1) JPH10107283A (de)
DE (1) DE69631524T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005294584A (ja) * 2004-03-31 2005-10-20 Eudyna Devices Inc 半導体装置および不純物導入用マスクならびに半導体装置の製造方法
DE102004021393B4 (de) * 2004-04-30 2006-06-14 Infineon Technologies Ag Feldeffekt-Leistungstransistor
US7875936B2 (en) * 2004-11-19 2011-01-25 Stmicroelectronics, S.R.L. Power MOS electronic device and corresponding realizing method
ITMI20042243A1 (it) 2004-11-19 2005-02-19 St Microelectronics Srl Processo per la realizzazione di un dispositivo mos di potenza ad alta densita' di integrazione
JP6047297B2 (ja) * 2012-04-09 2016-12-21 ルネサスエレクトロニクス株式会社 半導体装置
US9673103B2 (en) 2015-06-30 2017-06-06 Stmicroelectronics, Inc. MOSFET devices with asymmetric structural configurations introducing different electrical characteristics
JP7029364B2 (ja) * 2018-08-20 2022-03-03 株式会社東芝 半導体装置

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4069067A (en) * 1975-03-20 1978-01-17 Matsushita Electric Industrial Co., Ltd. Method of making a semiconductor device
US4412242A (en) 1980-11-17 1983-10-25 International Rectifier Corporation Planar structure for high voltage semiconductor devices with gaps in glassy layer over high field regions
US4417385A (en) 1982-08-09 1983-11-29 General Electric Company Processes for manufacturing insulated-gate semiconductor devices with integral shorts
US4816882A (en) 1986-03-10 1989-03-28 Siliconix Incorporated Power MOS transistor with equipotential ring
US4920393A (en) * 1987-01-08 1990-04-24 Texas Instruments Incorporated Insulated-gate field-effect semiconductor device with doped regions in channel to raise breakdown voltage
US4920388A (en) 1987-02-17 1990-04-24 Siliconix Incorporated Power transistor with integrated gate resistor
US4916509A (en) 1987-11-13 1990-04-10 Siliconix Incorporated Method for obtaining low interconnect resistance on a grooved surface and the resulting structure
EP0332822A1 (de) 1988-02-22 1989-09-20 Asea Brown Boveri Ag Feldeffektgesteuertes, bipolares Leistungshalbleiter-Bauelement sowie Verfahren zu seiner Herstellung
JPH0648729B2 (ja) 1988-02-24 1994-06-22 シーメンス、アクチエンゲゼルシシヤフト 電界効果制御可能のバイポーラ・トランジスタ
US5248891A (en) 1988-03-25 1993-09-28 Hiroshi Takato High integration semiconductor device
JP2675572B2 (ja) 1988-03-31 1997-11-12 株式会社東芝 半導体集積回路の製造方法
DE4001947A1 (de) 1989-02-17 1990-08-23 Volkswagen Ag Sicherheitseinrichtung fuer ein fahrzeug
US4998151A (en) 1989-04-13 1991-03-05 General Electric Company Power field effect devices having small cell size and low contact resistance
JPH07105496B2 (ja) * 1989-04-28 1995-11-13 三菱電機株式会社 絶縁ゲート型バイポーラトランジスタ
JPH02312280A (ja) * 1989-05-26 1990-12-27 Mitsubishi Electric Corp 絶縁ゲート型バイポーラトランジスタ
US4985740A (en) 1989-06-01 1991-01-15 General Electric Company Power field effect devices having low gate sheet resistance and low ohmic contact resistance
US5234851A (en) 1989-09-05 1993-08-10 General Electric Company Small cell, low contact assistance rugged power field effect devices and method of fabrication
US5119153A (en) 1989-09-05 1992-06-02 General Electric Company Small cell low contact resistance rugged power field effect devices and method of fabrication
US5047833A (en) 1990-10-17 1991-09-10 International Rectifier Corporation Solderable front metal contact for MOS devices
US5404040A (en) 1990-12-21 1995-04-04 Siliconix Incorporated Structure and fabrication of power MOSFETs, including termination structures
US5183769A (en) 1991-05-06 1993-02-02 Motorola, Inc. Vertical current flow semiconductor device utilizing wafer bonding
JPH05206469A (ja) * 1992-01-29 1993-08-13 Hitachi Ltd 絶縁ゲート型バイポーラトランジスタ
US5321281A (en) * 1992-03-18 1994-06-14 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device and method of fabricating same
US5319222A (en) * 1992-04-29 1994-06-07 North Carolina State University MOS gated thyristor having on-state current saturation capability
JP2984478B2 (ja) 1992-08-15 1999-11-29 株式会社東芝 伝導度変調型半導体装置及びその製造方法
US5486715A (en) 1993-10-15 1996-01-23 Ixys Corporation High frequency MOS device
DE69434268T2 (de) * 1994-07-14 2006-01-12 Stmicroelectronics S.R.L., Agrate Brianza Intergrierte Struktur einer Hochgeschwindigkeits-MOS-Technologe-Leistungsvorrichtung und zugehöriges Herstellungsverfahren
JPH08227999A (ja) * 1994-12-21 1996-09-03 Mitsubishi Electric Corp 絶縁ゲート型バイポーラトランジスタ及びその製造方法並びに半導体集積回路及びその製造方法

Also Published As

Publication number Publication date
DE69631524D1 (de) 2004-03-18
EP0817274A1 (de) 1998-01-07
EP0817274B1 (de) 2004-02-11
US20010001213A1 (en) 2001-05-17
JPH10107283A (ja) 1998-04-24
US6326271B2 (en) 2001-12-04
US6222232B1 (en) 2001-04-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee