JP5179014B2 - デュアル金属層を有するテープ配線基板及びそれを用いたチップオンフィルムパッケージ - Google Patents
デュアル金属層を有するテープ配線基板及びそれを用いたチップオンフィルムパッケージ Download PDFInfo
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- JP5179014B2 JP5179014B2 JP2006075044A JP2006075044A JP5179014B2 JP 5179014 B2 JP5179014 B2 JP 5179014B2 JP 2006075044 A JP2006075044 A JP 2006075044A JP 2006075044 A JP2006075044 A JP 2006075044A JP 5179014 B2 JP5179014 B2 JP 5179014B2
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- 239000002184 metal Substances 0.000 title claims description 46
- 229910052751 metal Inorganic materials 0.000 title claims description 46
- 230000009977 dual effect Effects 0.000 title claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 44
- 239000000758 substrate Substances 0.000 claims description 21
- 239000011347 resin Substances 0.000 claims description 9
- 229920005989 resin Polymers 0.000 claims description 9
- 238000000465 moulding Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 239000010408 film Substances 0.000 description 37
- 239000007788 liquid Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Description
本発明の一態様に係るデュアル金属層を有するテープ配線基板は、上部面及び下部面を有し、前記上部面に半導体チップが実装されるチップ実装領域が形成され、上下に貫通するビアが形成されたフィルムと、一端が前記フィルムの上部面に形成され、前記半導体チップの電極バンプがボンディングされ、前記一端に連結した他端は、前記チップ実装領域の外部に延びている入出力端子パターンを有する上部金属層と、前記チップ実装領域の下部の前記フィルムの下部面に形成され、接地層を有する下部金属層と、を備えることを特徴とする。
また、本発明の他の態様に係るパッケージは、活性面の周縁部に電極バンプが形成された半導体チップと、前記半導体チップが前記電極バンプを介して上部面にボンディングされるテープ配線基板と、前記半導体チップと前記テープ配線基板との間に充填された成形樹脂と、備え、前記テープ配線基板は、上部面及び下部面を有し、前記上部面に半導体チップが実装されるチップ実装領域が形成され、上下に貫通するビアが形成されたフィルムと、一端が前記フィルムの上部面に形成され、前記半導体チップの電極バンプがボンディングされ、前記一端に連結した他端は、前記チップ実装領域の外部に延びている入出力端子パターンを有する上部金属層と、前記チップ実装領域の下部の前記フィルムの下部面に形成され、接地層を有する下部金属層と、を備えることを特徴とする。
図3は、本発明の第1実施例に係るデュアル金属層124、131を有するテープ配線基板120を用いたCOFパッケージ200を示す上面平面図である。図4は、図3のIV−IV線における断面図である。図5は、本発明の第1実施例に係るCOFパッケージ200の底面を概略的に示す平面図である。
112 電極パッド
116 電極バンプ
117 入力バンプ
117a 接地バンプ
118 出力バンプ
119 ダミーバンプ
120 テープ配線基板
121 ベースフィルム
124 上部金属層
125 入力端子パターン
125a 接地端子パターン
126 出力端子パターン
128 ダミー端子パターン
127 ビア
131 下部金属層
131、231、331、431、531、631 接地層
134 ダミービア
140 成形樹脂
200 チップオンフィルムパッケージ
333、433、533、633 電源層
Claims (12)
- テープ配線基板において、
上部面及び下部面を有し、前記上部面に半導体チップが実装されるチップ実装領域が形成され、上下に貫通するビアが形成されたフィルムと、
一端が前記フィルムの上部面に形成され、前記半導体チップの電極バンプがボンディングされ、前記一端に連結した他端は、前記チップ実装領域の外部に延びている入出力端子パターンを有する上部金属層と、
前記チップ実装領域の下部の前記フィルムの下部面に形成され、接地層を有する下部金属層と、を備え、
前記下部金属層は、前記チップ実装領域の下部の前記フィルムの下部面に形成された電源層をさらに備え、前記接地層及び電源層を含む下部金属層は、前記半導体チップの接地バンプと電源バンプの配置位置や使用される電圧環境に応じて配置されると同時に、前記接地層及び電源層はそれぞれ2つ以上の電圧環境に応じて分離配置されることを特徴とするデュアル金属層を有するテープ配線基板。 - 前記電源層及び前記接地層は、板またはメッシュ形態で形成されることを特徴とする請求項1に記載のテープ配線基板。
- 前記上部金属層は、前記半導体チップのダミーバンプがボンディングされるダミー端子パターンをさらに備え、前記ダミー端子パターンは、ダミービアを介して前記接地層に連結されることを特徴とする請求項2に記載のテープ配線基板。
- 前記ビアは、前記入力端子パターンの一段下部に形成され、前記ダミービアは、前記ダミー端子パターンの一段下部に形成されることを特徴とする請求項3に記載のテープ配線基板。
- 前記接地層は、複数個で分離されていることを特徴とする請求項4に記載のテープ配線基板。
- 前記接地層は、前記チップ実装領域の下部に形成され、前記電源層は、前記接地層の端縁部を取り囲む形態で形成されることを特徴とする請求項2に記載のテープ配線基板。
- 活性面の周縁部に電極バンプが形成された半導体チップと、
前記半導体チップが前記電極バンプを介して上部面にボンディングされるテープ配線基板と、
前記半導体チップと前記テープ配線基板との間に充填された成形樹脂と、備え、
前記テープ配線基板は、
上部面及び下部面を有し、前記上部面に半導体チップが実装されるチップ実装領域が形成され、上下に貫通するビアが形成されたフィルムと、
一端が前記フィルムの上部面に形成され、前記電極バンプがボンディングされ、前記一端に連結した他端は、前記チップ実装領域の外部に延びている入出力端子パターンを有する上部金属層と、
前記チップ実装領域の下部の前記フィルムの下部面に形成され、接地層を有する下部金属層と、を備え、
前記下部金属層は、前記チップ実装領域の下部の前記フィルムの下部面に形成された電源層をさらに備え、前記接地層及び電源層を含む下部金属層は、前記半導体チップの接地バンプと電源バンプの配置位置や使用される電圧環境に応じて配置されると同時に、前記接地層及び電源層はそれぞれ2つ以上の電圧環境に応じて分離配置されることを特徴とするパッケージ。 - 前記電源層及び前記接地層は、板またはメッシュ形態で形成されることを特徴とする請求項7に記載のパッケージ。
- 前記上部金属層は、前記半導体チップのダミーバンプがボンディングされるダミー端子パターンをさらに備え、前記ダミー端子パターンは、ダミービアを介して前記接地層に連結されることを特徴とする請求項8に記載のパッケージ。
- 前記ビアは、前記入力端子パターンの一段下部に形成され、前記ダミービアは、前記ダミー端子パターンの一段下部に形成されることを特徴とする請求項7に記載のパッケージ。
- 前記接地層は、複数個で分離されていることを特徴とする請求項10に記載のパッケージ。
- 前記接地層は、前記チップ実装領域の下部に形成され、前記電源層は、前記接地層の端縁部を取り囲む形態で形成されることを特徴とする請求項8に記載のパッケージ。
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