CN1901179B - 带布线基板以及利用该基板的薄膜上芯片封装 - Google Patents

带布线基板以及利用该基板的薄膜上芯片封装 Download PDF

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CN1901179B
CN1901179B CN2006100678640A CN200610067864A CN1901179B CN 1901179 B CN1901179 B CN 1901179B CN 2006100678640 A CN2006100678640 A CN 2006100678640A CN 200610067864 A CN200610067864 A CN 200610067864A CN 1901179 B CN1901179 B CN 1901179B
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CN1901179A (zh
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李始勋
宋垠锡
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Samsung Electronics Co Ltd
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Abstract

本发明公开了一种带布线基板以及利用该基板的薄膜上芯片封装。所述封装可以包括带布线基板、安装在所述带布线基板上的半导体芯片，以及设置在所述半导体芯片和所述带布线基板之间的模塑料。所述带布线基板可以包括具有上下表面的薄膜。通路可以穿通所述薄膜。上金属层可以设置在所述薄膜的上表面上并包括输入端子图案和/或输出端子图案。输入端子图案可以包括接地端子图案和/或电源端子图案。下金属层可以设置在所述薄膜的下表面上并包括接地层和/或电源层。所述接地层和电源层可以至少覆盖芯片安装区域。

Description

带布线基板以及利用该基板的薄膜上芯片封装
技术领域
本发明的示范性实施例总体上涉及一种带布线基板(tape wiringsubstrate)以及利用该带布线基板的带封装，更具体而言，涉及一种具有双金属层的带布线基板以及实现该带布线基板的薄膜上芯片封装。
背景技术
平板显示器可以包括例如用于便携式电话的液晶显示器(“LCD”)、用于计算机的薄膜晶体管液晶显示器(“TFT LCD”)和家用的等离子体显示面板(“PDP”)。平板显示器可以包括本领域中公知的带封装部件。在某些应用中，带封装可以具有细距布线图案。
带封装可以包括带布线基板。带封装的两种主要类型可以是带载封装(“TCP”)和薄膜上芯片(“COF”)封装。TCP的带布线基板可以具有芯片安装窗口，其中可以经由(例如)内引脚键合方法来安装半导体芯片。COF的带布线基板可以不包括芯片安装窗口。此时，半导体芯片可以被倒装芯片式键合到带布线基板。与TCP相比，COF封装可以允许更薄的带布线基板和/或更细节距的布线图案。
在COF封装中，I/O端子图案可以取代焊料凸点而起到外部连接端子的作用。I/O端子图案可以直接附着到印刷电路板或显示面板。
图1是常规COF封装100的平面图。图2是沿图1的II-II线得到的横截面图。
参照图1和2，COF封装100可以包括带布线基板20。半导体芯片10可以被倒装芯片式键合到带布线基板20。模塑料(molding compound)40可以通过下填充工艺(underfill process)密封被倒装芯片式键合的部分。
半导体芯片10可以具有可支撑电极焊盘12的有源表面。可以沿该有源表面的边缘部分设置电极焊盘12。电极凸点16可以设置在电极焊盘12上。电极凸点16可以包括例如输入凸点17和输出凸点18。输入凸点17可以包括例如接地凸点17a和电源凸点17b。
带布线基板20可以包括基薄膜21以及设置在基薄膜21的上表面22上的上金属层24。基薄膜21可以具有面对半导体芯片10的芯片安装区域。芯片安装区域可以位于基薄膜21的中心部分。基薄膜21可以包括定位孔(sprocket holes)29。定位孔29可以沿着基薄膜21以预定间距排列。上金属层24的一端可以连接到电极凸点16。上金属层24的另一端可以从芯片安装区域向外延伸。上金属层24可以包括输入端子图案25和输出端子图案26。输入端子图案25可以包括用于地的输入端子图案25a(“接地端子图案”)和用于电源的输入端子图案25b(“电源端子图案”)。输入端子图案25可以延伸到相对于半导体芯片10的基薄膜21的一侧，输出端子图案26可以延伸到相对于半导体芯片10的基薄膜21的另一侧。输入和输出端子图案25和26可以平行于定位孔29的设置而延伸。
当半导体芯片10被倒装芯片式键合到带布线基板20时，接地凸点17a可以键合到接地端子图案25a，并且电源凸点17b可以键合到电源端子图案25b。
虽然常规COF封装通常被认为是可接受的，但其并非没有缺点。例如，为了有助于实现重量更轻、尺寸更小、速度更快、多功能和/或性能增强的半导体产品，可以使上金属层24具有细距布线图案，使半导体芯片10更加小型化，并且可以增大电极凸点16的数目。因此，接地端子图案25a和电源端子图案25b在节距上减小。例如，为了稳定的接地和/或电源，设置在基薄膜21的上表面22上的接地端子图案25a和电源端子图案25b可能具有不足的面积。
常规COF封装100不能充分减小有可能在半导体芯片10的工作期间产生的电磁波和/或噪声，这会导致差的电磁干扰和/或噪声特性。此外，常规COF封装100有可能向半导体芯片10不稳定地供电。
发明内容
根据一示范性非限制实施例，带布线基板可以包括薄膜，所述薄膜含有包括芯片安装区域的上表面、下表面和穿通所述薄膜的通路。上金属层可以设置在所述薄膜的上表面上并连接到半导体芯片的电极凸点。所述上金属层可以包括输入端子图案和输出端子图案。所述上金属层可以仅延伸到所述芯片安装区域的外围区域上。下金属层可以设置在所述薄膜的下表面上。所述下金属层包括接地层。
根据另一示范性非限制实施例，封装可以包括含有带电极凸点的有源表面的半导体芯片。可以设置带布线基板，其上安装了所述半导体芯片，使得所述电极凸点可以面对所述带布线基板。模塑料可以设置在所述半导体芯片和所述带布线基板之间。所述带布线基板可以包括薄膜，所述薄膜含有包括芯片安装区域的上表面、下表面和穿通所述薄膜的通路。上金属层可以设置在所述薄膜的上表面上并连接到所述电极凸点。所述上金属层可以包括输入端子图案和输出端子图案。所述上金属层可以仅延伸到所述芯片安装区域的外围区域上。下金属层可以设置在所述薄膜的下表面上。所述下金属层包括接地层。
附图说明
通过结合附图参照以下提供的详细说明，能够更容易地理解本发明的示范性非限制实施例，其中相似的附图标记表示相似的结构部件。
图1是常规COF封装的平面图；
图2是沿图1的II-II线得到的横截面图；
图3是根据本发明的一示范性非限制实施例的COF封装的平面图；
图4是沿图3的IV-IV线得到的横截面图；
图5是根据本发明的一示范性非限制实施例的COF封装的底视图；
图6是根据本发明的另一示范性非限制实施例的COF封装的底视图；
图7是根据本发明的又一示范性非限制实施例的COF封装的底视图；
图8是根据本发明的又一示范性非限制实施例的COF封装的底视图；
图9是根据本发明的又一示范性非限制实施例的COF封装的底视平面图；以及
图10是根据本发明的又一示范性非限制实施例的COF封装的底视图。
附图仅用于说明的目的而并未按比例绘制。在各个实施例中示出的元件的空间关系和相对尺寸可能被减小、扩大和/或重新排布从而相对于相应的说明而改善附图的清晰性。因此，附图不应被解释为准确地反映了根据本发明的示范性非限制实施例所制造的实际器件所包含的相应结构元件的相对尺寸和/或定位。
具体实施方式
现将参照附图更充分地描述本发明的示范性非限制实施例。然而，本发明可以以多种不同形式实施而不应理解为仅限于在此阐述的示范性实施例。而且，提供所公开的实施例是为了使本公开彻底而完全，并将本发明的范围充分告知本领域技术人员。在不偏离本发明的范围的前提下，本发明的原理和特征可以以各种实施例实施。
当一元件被直接安装(或设置)在参考元件上或者被安装(或设置)在覆盖参考元件的其他元件上时，该元件可以被认为是安装(或设置)在另一元件“上”。在本公开通篇，在描述附图中所示的各种元件或者元件的部分或区域时，为方便起见使用了例如“上”、“下”、“之上”和“之下”的空间术语。然而，这些术语并不要求结构保持在任何特定方位。
为了避免使本发明含糊不清，没有详细描述或说明公知的结构和工艺。
图3是根据本发明的一示范性非限制实施例的COF封装200的平面图。图4是沿图3的IV-IV线得到的横截面图。图5是根据本发明的一示范性非限制实施例的COF封装200的底视图。
参照图3至5，COF封装200可以包括带布线基板120和半导体芯片110。带布线基板120可以具有双金属层124和131。半导体芯片110可以被倒装芯片式键合到带布线基板120。模塑料140可密封被倒装芯片式键合的部分。可以经由例如下填充工艺来设置模塑料。
半导体芯片110可以具有带有电极焊盘112的有源表面。电极焊盘112可以沿着有源表面的外围设置。可以在电极焊盘112上设置电极凸点116。电极凸点116可以包括例如输入凸点117和输出凸点118。输入凸点117可以包括例如接地凸点117a和电源凸点(未示出)。输入凸点117可以在尺寸和/或节距上大于输出凸点118。这可以减小例如由于输入凸点117之间的静电所致的故障可能性。半导体芯片110可以包括伪凸点(dummy pattern)119。伪凸点119例如可以设置在有源表面的角部区域。伪凸点119可以改善例如组装稳定性和/或热辐射性。
带布线基板120可以包括基薄膜121。基薄膜121可以由例如聚酰亚胺制造。基薄膜121也可以由本领域中公知的多种其他材料制成。双金属层124和131可以由例如在基薄膜121上成箔的Cu制造。双金属层124和131也可以由本领域中公知的各种材料(Cu之外)并使用各种技术(铺箔之外)来制造。基薄膜121可以含有包括芯片安装区域的上表面122以及与上表面122相对的下表面123。芯片安装区域可以是上表面122的面对半导体芯片110的区域。也就是说，半导体芯片110可以叠置于上表面122的芯片安装区域之上。通路127可以穿通基薄膜121。双金属层124和131可以包括设置在基薄膜121的上表面122上的上金属层124以及设置在基薄膜121的下表面123上的下金属层131。
上金属层124可以设置在芯片安装区域上并且可以连接到电极凸点116。上金属层124可以从芯片安装区域向外延伸。上金属层124可以包括例如输入端子图案125和输出端子图案126。仅作为实例，输入端子图案125可以延伸到相对于半导体芯片110的基薄膜121的一侧，输出端子图案126可以延伸到相对于半导体芯片110的基薄膜121的另一侧。输入端子图案125可以包括连接到接地凸点117a的接地端子图案125a。
下金属层131可以设置在下表面123的对应于芯片安装区域的区域上。例如，芯片安装区域可以叠置在下金属层131之上。下金属层131可以包括接地层132。接地层132可以通过通路127连接到接地端子图案125a。仅作为实例，接地层132可以至少覆盖芯片安装区域。接地层132可以由例如板状物或网状物制造。接地层132可以提供足够的接地面积从而减小由半导体芯片110发射的电磁波的损耗和/或噪声，由此改善电稳定性。
将接地端子图案125a连接到接地层132的通路127可以减小对于将接地端子图案125a连接到接地层132的单独布线的需要和/或减小接地路线长度。
上金属层124可以设置在芯片安装区域的外围区域上。在一示范性实施例中，上金属层124可以不覆盖芯片安装区域的中心区域。仅在芯片安装区域的外围区域上(而不在芯片安装区域的中心部分上)设置上金属层124有助于下填充工艺期间模塑料140的流动和/或降低空洞产生的可能性。
接地层132可以用作辐射例如由半导体芯片110发出的热量的散热器。伪凸点119可以连接到接地层132以改善例如热辐射特性。伪凸点119可以通过伪通路134连接到伪端子图案128。
在本示范性实施例中，接地层132可以是整体的一件式构造。在可选实施例中，接地层也可以是多件式构造。例如，参照图6，COF封装300可以包括具有第一接地层232a和第二接地层232b的带布线基板200。第一接地凸点217a’可以通过第一通路227a连接到第一接地层232a。第二接地凸点217a”可以通过第二通路227a”连接到第二接地层232b。
仅作为实例，多件式接地层232可以在不同的电压施加到半导体芯片210时生效。例如，当半导体芯片210具有施加了5V电压的模拟电路和施加了1.5V电压的数字电路时，接地层可以被分成用于模拟电路的接地层和用于数字电路的接地层。
在以上示范性实施例中，基薄膜可以仅具有接地层。在可选实施例中，基薄膜可以具有接地层和电源层。
参照图7，COF封装400可以具有包括接地层332和电源层333的下金属层331。接地层332可以与电源层333分开。
电源层333可以设置在基薄膜321的下表面323上，对应于芯片安装区域。电源端子图案(未示出)可以键合到电源凸点317b。电源端子图案可以通过通路327b连接到电源层333。
将电源凸点317b连接到电源层333的通路327b可以减少对于将电源凸点317b连接到电源层333的单独布线的需要，和/或减小电源路线长度。
仅作为实例，电源层333可以在不同的电压施加到半导体芯片310上时生效。在该示范性实施例中，电源层333可以设置在接地层332之间。
包括接地层和电源层的下金属层可以根据半导体芯片的接地凸点和电源凸点的设置和电压而具有各种布局。
参照图8，COF封装500可以具有包括接地层432和电源层433的下金属层431。电源层433可以具有围绕接地层432的环形。在该示范性实施例中，电源层433可以具有方环形状。在可选实施例中，电源层433可以具有弓形环形状(例如，圆环形状)。此外，接地层432和电源层433之间的间隔可以是均匀的(如所示)或者变化的。
参照图9，COF封装600可以具有包括接地层532和电源层533的下金属层531。电源层533可以具有字母“C”的形状。电源层533可以包围接地层532。
参照图10，COF封装700可以具有包括接地层632和电源层633的下金属层631。电源层633可以具有梳形。电源层633可以包围接地层632。
虽然以上示范性实施例示出了电源层可以包围接地层，但可以理解的是，接地层可以包围电源层。此外，在以上示范性实施例中，下金属层可以具有相同形状的接地层和/或相同形状的电源层。在可选实施例中，给定的下金属层可以具有不同形状的接地层和/或不同形状的电源层。
尽管已经详细描述了本发明的示范性非限制实施例，但应理解的是，对于本领域技术人员而言显而易见的对于基本发明构思的多种变化和/或改进仍将落入由权利要求限定的本发明的示范性实施例的主旨和范围内。
本申请要求于2005年7月18日提交的韩国专利申请No.2005-64789的优先权，其全部内容在此引入作为参考。

Claims (16)

1.一种带布线基板，包括：
薄膜，所述薄膜含有包括芯片安装区域的上表面、下表面以及穿通所述薄膜的通路；
设置在所述薄膜的上表面上并连接到半导体芯片的电极凸点的上金属层，所述上金属层包括用于连接所述半导体芯片与至少一个外部电路的输入端子图案和输出端子图案，所述上金属层从所述芯片安装区域的外围区域延伸；以及
设置在所述薄膜的下表面上并连接到所述通路的下金属层，所述下金属层包括接地层，
其中所述上金属层还包括用于所述半导体芯片的伪凸点的伪端子图案，并且所述伪端子图案通过伪通路连接到所述接地层。
2.根据权利要求1所述的基板，其中所述接地层至少重叠所述芯片安装区域。
3.根据权利要求1所述的基板，其中所述下金属层设置在对应于所述芯片安装区域的下表面上，并且所述下金属层还包括电源层。
4.根据权利要求3所述的基板，其中所述电源层和所述接地层由板状物和网状物之一制造。
5.根据权利要求4所述的基板，其中所述通路设置在所述输入端子图案的一端之下并且所述伪通路设置在所述伪端子图案的一端之下。
6.根据权利要求5所述的基板，其中所述接地层被分成多个接地层。
7.根据权利要求6所述的基板，其中所述电源层被分成多个电源层。
8.根据权利要求4所述的基板，其中所述接地层设置在所述芯片安装区域之下并且所述电源层包围所述接地层。
9.一种封装，包括：
半导体芯片，所述半导体芯片含有具有电极凸点的有源表面；
带布线基板，在所述带布线基板上安装了所述半导体芯片，使得所述电极凸点面对所述带布线基板；以及
设置在所述半导体芯片和所述带布线基板之间的模塑料，
所述带布线基板包括：
薄膜，所述薄膜含有包括芯片安装区域的上表面、下表面以及穿通所述薄膜的通路；
设置在所述薄膜的上表面上并连接到所述电极凸点的上金属层，所述上金属层包括用于连接所述半导体芯片与至少一个外部电路的输入端子图案和输出端子图案，所述上金属层仅从所述芯片安装区域的外围区域延伸；以及
设置在所述薄膜的下表面上并连接到所述通路的下金属层，所述下金属层包括接地层，
其中所述上金属层还包括用于所述半导体芯片的伪凸点的伪端子图案，并且所述伪端子图案通过伪通路连接到所述接地层。
10.根据权利要求9所述的封装，其中所述接地层至少重叠所述芯片安装区域。
11.根据权利要求9所述的封装，其中所述下金属层设置在对应于所述芯片安装区域的下表面上，并且所述下金属层还包括电源层。
12.根据权利要求11所述的封装，其中所述电源层和所述接地层由板状物和网状物之一制造。
13.根据权利要求12所述的封装，其中所述通路设置在所述输入端子图案的一端之下并且所述伪通路设置在所述伪端子图案的一端之下。
14.根据权利要求13所述的封装，其中所述接地层被分成多个接地层。
15.根据权利要求14所述的封装，其中所述电源层被分成多个电源层。
16.根据权利要求12所述的封装，其中所述接地层设置在所述芯片安装区域之下并且所述电源层包围所述接地层。
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