JP4512460B2 - 埋設電導層を備えた高電圧トランジスタの製造方法 - Google Patents

埋設電導層を備えた高電圧トランジスタの製造方法 Download PDF

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JP4512460B2
JP4512460B2 JP2004271371A JP2004271371A JP4512460B2 JP 4512460 B2 JP4512460 B2 JP 4512460B2 JP 2004271371 A JP2004271371 A JP 2004271371A JP 2004271371 A JP2004271371 A JP 2004271371A JP 4512460 B2 JP4512460 B2 JP 4512460B2
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レイ ディズニー ドナルド
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パワー インテグレーションズ、インコーポレイテッド
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Description

本願は、本願の譲受人に譲渡されたＲｕｍｅｎｎｉｋ等の１９９９年２月５日に出願した米国特許出願第０９／２４５，０２９号に関連し、この出願は、本願明細書において参照として組み入れられる。
本発明は、半導体装置に関する。より詳細には、本発明は、シリコン基板に製造された高電圧電界効果トランジスタの構造に関する。
横方向高電圧電界効果トランジスタ（ＨＶＦＥＴ）は、高電圧接合電界効果トランジスタ（ＪＦＥＴ）と直列に配置された絶縁ゲート電界効果トランジスタ（ＩＧＦＥＴ）を用いて製造されている。このＩＧＦＥＴは、装置の「オン」状態電流を制御するために使用され、ＪＦＥＴは、「オフ」状態で高電圧をサポートするために使用される。このＨＶＦＥＴ構造は、高電圧でスイッチングされることができ、低いオン状態抵抗値を有し、絶縁ゲート制御を有している。更に、単一の集積回路チップ上で低電圧ロジックトランジスタの近くに有利に製造できる。
横方向ＨＶＦＥＴは、減少表面電界（ＲＥＳＵＲＦ）原理に従って一般に製造される。しかしながら、ＲＥＳＵＲＦ原理は、高いブレークダウン電圧を得るために、横方向ＪＦＥＴのチャンネルとして働く拡張ドレイン領域中の電荷を注意深く制御する必要がある。電子なだれブレークダウンが生じる臨界電界以下に最大電界を保持するために、ＪＦＥＴチャンネルでの電荷量は、典型的に約１×１０12ｃｍ-2の最大値に制限される。ＨＶＦＥＴが「オン」状態にあるときに、ＪＦＥＴチャンネルの抵抗値は、ＨＶＦＥＴのオン状態抵抗値の大きな部分を構成する。従って、ＪＦＥＴ中の最大電荷についての制限もまた装置の最小固有オン抵抗値を決定する。
拡張ドレイン領域の導電型と反対の導電型の頂部層と共に拡張ドレイン領域を有するＨＶＦＥＴは、米国特許第４，８１１，０７５号に開示されている。この米国特許第４，８１１，０７５号は、頂部層が装置のオン抵抗値の同程度の減少を伴って導電層の電荷をほぼ２倍にすることを教示する。この頂部層もまた拡張ドレインが高電圧をサポートしているときにＪＦＥＴ導電領域を空乏化するのを助ける。
この概念を一層拡大する上で、米国特許第５，４１１，９０１号は、相補形高電圧トランジスタでのＪＦＥＴの導電部分として反対導電型頂部層を用いることを教示する。しかしながら、１つの欠点は、この相補形装置の構造が高電圧機能を達成するために追加の処理を必要とすることである。更に、相補形装置のオン抵抗値は、頂部領域に対する電荷要求（例えば、約１×１０12ｃｍ-2）によって制限される。他の困難性は、頂部層が往々シリコン表面の酸化に先立って形成され、これは追加の処理を導入してしまうことである。
ＪＦＥＴの導電領域での全体電荷を一層増大し、かつ、オン抵抗値を減少するために、米国特許第５，３１３，０８２号は、２つのＪＦＥＴチャンネルが平行して配列されるようなＨＶＦＥＴ構造を教示する。３つの別々の打ち込みおよび拡散ステップがＮ−型導電頂部層、Ｐ−型中間層およびＮ−型導電底部層を有するＨＶＦＥＴを形成する必要がある三重拡散プロセスが開示されている。交互の導電型のこれら多数の層は、打ち込みを行い、次いで拡散を行い、半導体基板にドーピングすることによって作成される。米国特許第５，３１３，０８２号は、また、三層拡張ドリフト領域に追加の層を付加することによって形成される相補形高電圧トランジスタ（すなわち、Ｐ−チャンネル装置）をも記載している。
この従来技術のアプローチの１つの欠点は、各連続した層が対応領域の導電型を充分に補って変化するために先行する層よりも高い表面濃度を持たなければならないことである。表面からのドーパントの拡散は、層間で適切な電荷バランスを維持することを極めて困難にする。更に、埋設層およびドレイン拡散領域間の大きくドーピングしたＰ−Ｎ接合は、装置のブレークダウン電圧を低下する。濃度もまた各層内の自由キャリアの移動度を低下しようとし、それによってＨＶＥＦＴのオン抵抗値を悪化する。相補形装置を形成するために必要な追加の層は、製造プロセスを複雑にする。
相補形ＣＭＯＳ装置を製造するための一般的なプロセスとの互換性があるＰ−チャンネルＭＯＳ装置の設計は、米国特許第５，８９４，１５４号に記載されている。
以下、本発明の一実施例の高電圧電界効果トランジスタを説明する。このＨＶＦＥＴは、低い固有オン抵抗値を有し、かつ低電圧ロジック装置と共に同一のチップ上に相補形横方向ＨＶＦＥＴと容易に集積化され得る。以下の説明において、本発明の完全な理解を与えるために材料形式、ドーピングレベル、構造的特徴、処理ステップ等のような多くの特定の詳細が述べられる。半導体技術の当業者には、本発明がこれら詳細の多くを持たずに実施され得ることが理解される。他の例では、周知の要素、技術およびプロセスステップは、本発明が不明確にならないように詳細には記載されなかった。
図１は、本発明の一実施例に従ったＰ−チャンネルＨＶＦＥＴ装置構造の横断面側面図である。（図中の要素は、描写的であり、明瞭化のため実寸では描かれてはいないことも理解されるべきである。）Ｎ−チャンネルトランジスタが図示の拡散領域の全てに反対導電型を用いることによって実現され得る。図１の装置は、ゲート２２（例えば、ポリシリコンからなる）と二酸化ケイ素あるいは他の適切な誘電性絶縁材料からなるゲート絶縁層３０と軽くドーピングしたＰ−型基板領域１０中に設けられた下層のＮ−型ウエル領域１２とを有する絶縁ゲート電界効果トランジスタ（ＩＧＥＦＴ）を含んでいる。ゲート２２の真下のＮ―型ウエル領域１２の区域は、トランジスタのＩＧＥＦＴチャンネル領域３１である。この実施例において、ゲート領域は、金属酸化物半導体（ＭＯＳ）であり、ＩＧＥＦＴは、ＰＭＯＳトランジスタである。
チャンネル領域３１は、一端でＰ＋ソース拡散領域１９によって他端でＰ−型拡散領域１６によって定められ、これはＮ−ウエル１２の基板表面から下方に延びる。横方向高電圧Ｐ−チャンネルＦＥＴがＰＭＯＳ装置とＮ−ウエル領域１２へのＰ−型ドーパント（例えば、ホウ素）の高エネルギー打ち込みによって形成されたＰ−型ＪＦＥＴトランジスタとの直列接続によって形成される。この高エネルギー打ち込みは、Ｐ−型埋設層１４を形成し、これはＰ−型拡散領域１６に接続される。埋設層１４は、Ｐ−型ＪＦＥＴ装置の拡張ドレインの導電部分を構成する。Ｐ−型埋設領域１４の電荷は、この実施例でほぼ２×１０12ｃｍ-2であり、伝統的な装置より約５０％低いオン抵抗値となる。
Ｐ−型拡散領域１６のドーピングは、この領域がオフ状態において比較的に低電圧（＜１００Ｖ）で完全に空乏化され得るように選択されるということは当業者には認められる。これは、領域１６がオフ状態では高電圧（〜７００Ｖ）をサポートするためにトランジスタの能力を妨げないようにする。
ソース電極２９は、Ｐ＋ソース拡散領域１９への電気接続を与える。同様に、ドレイン電極２８は、Ｐ＋ドレイン拡散領域１８に接続する。ドレイン拡散領域１８およびソース拡散領域１９は、同一の打ち込みステップを用いて形成されてもよい。ドレイン拡散領域１８と埋設層１４との間の電気接続は、Ｐ−型拡散領域１７により確立される。領域１７は、同一の処理ステップを用いてＰ−型拡散領域１６と同時に形成されてもよいことを理解される。別形態として、Ｐ＋ドレイン拡散領域１８は、Ｐ−型埋設層１４まで基板表面から垂直方向下方に延びるように形成されてもよい。
それぞれのソースおよびドレイン電極２９および２８は、多数の広く使われている金属または金属合金で構成されてもよい。ソース電極２９は、ゲート２９の上方を延びるように示され、かつ、それから絶縁されており、その際、それは電界板として働くことを留意される。同様に、ドレイン電極２８は、ドレイン拡散領域１８の上に配置され、かつ、それに近傍するポリシリコン電界板部材２３の上方を延びる。電界板は、表面電界を減少し、基板の空乏の有効半径を増大し、それによってトランジスタのブレークダウン電圧を増大するように働く。
図１の実施例において、Ｎ＋拡散領域２０は、Ｐ＋ソース拡散領域１９に近接して配置される。拡散領域２０は、Ｎ−ウエル領域１２への良好な電気接続を与えるので、寄生バイポーラ効果に対する装置の敏感さを減少する。
図１のＰ−チャンネルＨＶＦＥＴがオン状態にあるときには、電流は、ソース拡散領域１９からＩＧＦＥＴチャンネル領域３１次いでＰ−型領域１６、１４および１７を介してＰ＋ドレイン拡散領域１８に流れる。上記のように、Ｐ−型埋没領域１４の電荷は、従来のＰ−チャンネル装置よりほぼ２倍大きい。このため、拡張ドレイン領域の抵抗値は、従来の装置の約１／２に減少される。
オフ状態においては、Ｐ−拡散領域１６、Ｐ−型埋設層領域１４およびＮ−ウエル領域１２は、自由キャリアから共通に空乏化される。
図１に示される装置構造の重要な長所は、それが相補形、高電圧Ｎ−チャンネルＦＥＴを作るために使用される同一のプロセスを用いて構成され得ることである。１つの例を挙げると、このようなプロセスは、本願明細書に組み入れられたＲｕｍｅｎｎｉｋ等の米国特許出願の図１１ａ〜１１ｉに示され、関連した説明が行われている。重要なことは、Ｐ−領域１６の追加以外同一のマスキング層が両装置に対して使用され得るため、追加の処理の複雑性が導入されないことである。
Ｎ−チャンネルＨＶＦＥＴを製造するための上述のプロセスに従って、同一のシリコン基板上に相補形装置を製造することは、Ｐ−チャンネルおよびＮ−チャンネル装置に関連したそれぞれのＮ−ウエル領域を分離することによって達成される。Ｐ−チャンネル装置のＰ−型埋設層領域１４を形成するために使用されるマスキング層は、Ｎ−チャンネル装置構造の埋設層領域を同時に形成するために使用される。Ｎ−チャンネル装置においては、このＰ−型埋設層は、単一の導電性Ｎ−ウエルをＪＦＥＴトランジスタの並列の導電性ドリフト領域に分割する。並列に加えられて、各導電性領域は、ＨＶＦＥＴ構造のオン抵抗を減少する。
一例として、図３は、同一のＰ−型基板１０上に互いに近接して製造された高電圧ＰＭＯＳおよびＮＭＯＳトランジスタを示す。ＰＭＯＳ装置のＮ−ウエル１２を形成するために使用される同一の処理ステップもＮＭＯＳ装置のＮ−ウエル５２を製造するために使用されてもよいことを特記する。同様に、ＰＭＯＳ装置の埋設層１４およびＮＭＯＳ装置の埋設層７４は、同一のステップを用いて形成されてもよい。同一の処理ステップで形成可能なＰＭＯＳおよびＮＭＯＳ装置の他の抵抗は、それぞれＰ＋領域１９および６９と、Ｎ＋領域２０および７０と、ゲート酸化物領域３０および８０とを含んでいる。
例えば、図１のＰ−型拡散領域１６は、Ｎ−チャンネルおよびＰ−チャンネル装置のＰ−型埋設層領域を形成する打ち込みステップの前あるいは後に形成されてもよい。一例として、拡散領域１６は、Ｎ−ウエル１２の形成に引き続く基板へのホウ素の打ち込みで形成されてもよい。プロセスが電界酸化物層を形成するためのステップを随意に選択して含むならば、Ｐ−型拡散領域１６は、従来の処理技術を用いて、電界酸化物成長の前あるいはその後にＮ−ウエル１２に形成されてもよい。
図２は、本発明の別態様の実施例を示し、これはＮ−ウエル領域１２に分散された複数の垂直方向に積み重ねられたＰ−型埋設層領域１４ａ〜１４ｃを具備する。典型的な処理シーケンスにおいて、全ての埋設層を定めるために単一の打ち込みマスクが使用される。次いで、高エネルギー打ち込みが埋設層領域１４ａ、１４ｂおよび１４ｃを形成するために使用される。図２の装置構造は、チャンネル３１の一端を定めるＰ−型拡散領域２６を含んでいる。拡散領域２６は、基板表面から下方に延び、埋設層領域１４ａ〜１４ｃのそれぞれと電気的接続を行う。同様に、Ｐ−型拡散領域２７は、Ｐ＋ドレイン拡散領域１８から垂直方向下方に延び、埋設層領域１４ａ〜１４ｃのそれぞれと接続する。個別のＰ−型領域２７を形成せずに、ドレイン拡散領域１８の下の埋設層領域１４のそれぞれへの接続がＰ＋ドレイン拡散領域１８を基板表面から垂直方向下方に埋設層領域１４ａ〜１４ｃとの接続を行うための充分な深さまで単純に延ばすことによって達成されてもよい。
このようにして、図２のＨＶＦＥＴにおいて空間的に隔てられたＰ−型埋設層領域１４は、並列導電路を与える。それぞれの埋設層領域１４の電荷を制御することによって、高電圧をサポートするＰ−チャンネル装置の能力が悪化されない。更にまた、上述の教示によれば、それぞれの追加導電層は、追加の２×１０12ｃｍ-2の電荷に寄与し、装置のオン抵抗値を一層低下させる。
本発明による高電圧電界効果トランジスタ（ＨＶＦＥＴ）装置構造の一実施例の横断面側面図。 本発明に従って作られたＨＶＦＥＴの他の実施例の横断面側面図である。 本発明に従って同一の基板上に作られた相補形ＨＶＦＥＴの横断面側面図である。
符号の説明
１０ Ｐ−型基板領域
１２ Ｎ−型ウエル領域
１４、１４ａ〜１４ｃ Ｐ−型埋設領域
１６ Ｐ−型拡散領域
１７ Ｐ−型拡散領域
１８ Ｐ＋ドレイン拡散領域
１９ Ｎ＋ソース拡散領域
２０ Ｎ＋拡散領域
２２ ゲート
２３ ポリシリコン電界板部材
２８ ドレイン電極
２９ ソース電極
３０ ゲート絶縁層
３１ ＩＧＥＦＴチャンネル領域
５２ Ｎ−ウエル
６９ Ｐ＋領域
７０ Ｎ＋領域
７４ 埋設層
８０ ゲート酸化物領域

Claims (4)

  1. 第１の導電型の基板に相補型高電圧電界効果トランジスタ（ＨＶＦＥＴ）を製造する方法であって、
    第１の導電型と反対の第２の導電型の第１および第２のウエル領域を基板に形成する段階と、
    第１および第２の横方向に延びる埋設層領域を第１および第２のウエル領域内にそれぞれ形成するために第１および第２のウエル領域に第１の導電型のドーパントを打ち込む段階と、
    第１のウエル領域の上方に第１の絶縁ゲートを形成し、基板の上方で第２のウエル領域に近接して第２の絶縁ゲートを形成する段階と、
    第１のウエル領域で隔置された第１の導電型の第１のドレイン領域および第１のソース領域を形成し、第１のドレイン領域および第１のソース領域は、第１のＨＶＦＥＴに関連する段階と、
    第１のドレイン領域から隔置され、かつ、第１のドレイン領域と第１のソース領域との間に位置して第１のウエル領域に第１の導電型の追加のドレイン領域を形成し、第１の絶縁ゲートの下方に追加のドレイン領域と第１のソース領域との間で第１のウエル領域に第１のチャンネル領域を定める段階と、
    第２のウエル領域に第２の導電型の第２のドレイン領域を形成し、かつ、第２のウエル領域から隔置された第２の導電型の第２のソース領域を形成し、第２のドレイン領域および第２のソース領域は、第２のＨＶＦＥＴと関連し、第２の絶縁ゲートの下方で第２のソース領域と第２のウエル領域との間で第２のチャンネル領域が定められる段階とを含み、
    第１のドレイン領域および追加のドレイン領域は、第１のウエル領域を通って垂直方向下方に延びて第１の横方向に延びた埋設層領域に接続され、第１のＨＶＦＥＴがオン状態のときに第１の横方向に延びた埋設層領域によって電流が横方向に流れるように導電路が与えられ、第２のＨＶＦＥＴがオン状態のときに第２の横方向に延びた埋設層領域によって対応するＪＦＥＴ導通路が第２のウエル領域に定められる前記方法。
  2. 請求項１記載の方法において、第１の導電型は、Ｐ−型であり、ドーパントは、ホウ素からなる前記方法。
  3. 請求項１記載の方法において、第１および第２の横方向に延びた埋設層領域は、それぞれ第１および第２のウエル領域内の異なる深さに配置された複数の平行な隔置された埋設層領域を含む前記方法。
  4. 請求項１記載の方法において、第１および第２の横方向に延びた埋設層領域は、打ち込みによって同時に形成される前記方法。
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