CN102684485B - 垂直互补场效应管 - Google Patents

垂直互补场效应管 Download PDF

Info

Publication number
CN102684485B
CN102684485B CN201110056548.4A CN201110056548A CN102684485B CN 102684485 B CN102684485 B CN 102684485B CN 201110056548 A CN201110056548 A CN 201110056548A CN 102684485 B CN102684485 B CN 102684485B
Authority
CN
China
Prior art keywords
intermediate layer
substrate layer
mos cell
electrodes
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201110056548.4A
Other languages
English (en)
Other versions
CN102684485A (zh
Inventor
黄勤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
VERSINE SEMICONDUCTOR Co Ltd
Original Assignee
VERSINE SEMICONDUCTOR Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by VERSINE SEMICONDUCTOR Co Ltd filed Critical VERSINE SEMICONDUCTOR Co Ltd
Priority to CN201110056548.4A priority Critical patent/CN102684485B/zh
Priority to TW100145689A priority patent/TWI447853B/zh
Priority to US13/413,175 priority patent/US8476710B2/en
Publication of CN102684485A publication Critical patent/CN102684485A/zh
Application granted granted Critical
Publication of CN102684485B publication Critical patent/CN102684485B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107Substrate region of field-effect devices
    • H01L29/1075Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00Conversion of dc power input into dc power output
    • H02M3/02Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1588Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

垂直互补场效应管,涉及半导体芯片生产技术。更具体的说,涉及功率集成电路芯片生产技术。本发明的衬底层局部延伸入中间层并形成位于两个MOS单元之间的栓部,衬底层的下侧设有导出端,当两个MOS单元的栅极施加开通电压后,形成MOS单元-栓部-衬底层-导出端的两个导流通道。本技术可以集成俩个以上MOS管,因而减小了芯片尺寸。

Description

垂直互补场效应管
技术领域
本发明涉及半导体技术,具体是一种主要用于形成直流-直流变换器(DC/DC Converter)中积木式组件的垂直互补场效应管。
背景技术
目前,积木式组件(Building Block)被广泛地应用于各种电路设计及生产中。积木式组件包括分离的电源开关、电感器、电容器等,为了提高功率密度和开关频率,设计高度集成的积木式组件显得很有必要。
图1所示为一种直流-直流变换器的原理图,SW1和SW2为两个MOS管开关,对应这种电路,应用CMOS技术,可以将SW1和SW2集成在一个积木式组件中。现有集成CMOS结构如图2所示,两个PN极性相反的MOS单元分别设在P衬底(p-substrate)和N井(n-well)上,SW1、SW2的源极和漏极都设在上表面,SW1的漏极、SW2的源极分别接Vin电位和GND电位,SW2的漏极、SW1的源极则相接并输出电位VX,通过控制SW1、SW2的开关来控制VX电位。
这种结构存在如下问题:1)这种横向结构因为侧电流的影响容易在P衬底和N井中产生自偏效应,限制了芯片的尺寸,进一步也限制了转换器的额定电流;2)和分离结构相比,击穿电压较小;3)芯片表面有三个电流端子(Vin、GND、VX),也限制了功率密度和芯片的尺寸。
发明内容
为了解决现有技术中存在的问题,本发明提供一种垂直互补场效应管及方法,通过改进芯片结构,来减小对芯片尺寸的限制,并提高击穿电压。
为此,本发明采用以下技术方案:
垂直互补场效应管,包括至少两个MOS单元,其特征在于:还包括衬底层和设于衬底层上的中间层,该中间层与一个MOS单元对应处嵌有井区,衬底层的PN极性与中间层相反,与井区相同,所述的每个MOS单元包括一对PN同性电极和一个栅极,两个MOS单元的电极PN极性相反,其中一对电极设于中间层上并能在栅极控制下在中间层形成导通沟道,另一对电极设于井上并能在栅极控制下在井中形成导通沟道,所述的衬底层局部延伸入中间层并形成位于两个MOS单元之间的栓部,衬底层的下侧设有导出端,当两个MOS单元的栅极施加开通电压后,形成MOS单元-栓部-衬底层-导出端的两个导流通道。
作为对上述技术方案的完善和补充,本发明进一步采取如下技术措施或是这些措施的任意组合:
所述的衬底为N+材料,中间层为P-材料,井区为N-材料,位于中间层上的MOS单元两个电极均为N+材料,而位于井区的MOS单元两个电极均为P+材料。
所述的衬底为P+材料,中间层为N-材料,井区为P-材料,位于中间层上的MOS单元两个电极均为P+材料,而位于井区的MOS单元两个电极均为N+材料。
本发明也可采用如下方案:
垂直互补场效应管,包括至少两个MOS单元,其特征在于:还包括衬底层和设于衬底层上的中间层,两个MOS单元设于中间层上且共用一个电极,另两个电极则作为两个导入端,这三个电极的PN极性都相同且与中间层相反,所述的衬底层局部延伸入中间层形成栓部并与共用电极连通,衬底层的下侧设有导出端,衬底层与电极的PN极性相同,当两个MOS单元的栅极施加开通电压后,形成导入端电极-共用电极-栓部-衬底层-导出端的两个导流通道。
作为对上述技术方案的完善和补充,本发明进一步采取如下技术措施或是这些措施的任意组合:
所述的衬底为N+材料,中间层为P-材料,位于中间层上的两个MOS单元的两个电极均为N+材料。
所述的衬底为P+材料,中间层为N-材料,位于中间层上的两个MOS单元的两个电极均为P+材料。
在所述MOS单元的漏电极和栅极间设置轻掺杂漏区,来有效提高芯片的击穿电压。
有益效果:本发明通过设置竖向的栓引导电流竖向流动,改原有的横向结构为竖向结构,避免横向侧电流引起自偏效应,且芯片表面只需要两个电流端子,有助于增大芯片尺寸和功率密度,提高转换器的额定电流。由于增加了中间层,在采用低掺杂漏(LDD)工艺的情况下,可以有效增大击穿电压,器件工作更加安全;本发明可以采用修改过的CMOS工艺来实现。除了实现本方面中描述的器件外, 还可以实现标准的模拟和数字集成电路功能。
附图说明
图1为直流-直流变换器的原理图;
图2为现有的直流-直流变换器芯片结构示意图;
图3为本发明的一种芯片结构示意图;
图4为本发明的另一种芯片结构示意图;
图5为本发明的另一种芯片结构示意图;
图6为本发明用作单个MOS开关时的结构示意图;
图7为本发明有LDD区域时的结构示意图。
具体实施方式
实施例一
如图3所示的垂直互补场效应管,N+衬底上为P-中间层,中间层一般为外延层,P-中间层里有N-井层,MOS单元SW1和SW2分别设在P-中间层和N-井层上,N+衬底局部上延伸入中间层形成一个N+栓(Plug),N+衬底下侧为导出端。SW1的漏极和SW2的源极接有两个电流端子,分别用于连接Vin电位和GND电位,导出端用于输出电位VX。工作室电流流向如图中箭头所示,主要沿竖向流动,避免了横向结构存在的自偏效应。
实施例二
如图4所示的垂直互补场效应管,结构与实施例1相似,区别在于各层PN极性相反。
实施例三
如图5所示的垂直互补场效应管,N+衬底上为P-中间层,中间层可为P-外延层或P-井,MOS单元SW1和SW2共用一个电极,三个电极都设在中间层上,N+衬底局部上延伸入中间层直至共用电极形成一个N+栓,N+衬底下侧为导出端。N+栓将SW1和SW2相互隔离,能更好避免侧电流的影响。工作室电流流向同样如图中箭头所示。
实施例四
实施例三的结构略作改进可将本发明结构用于单个MOS管场合(图6),即将芯片表面的三个电极连通,这种结构中,表面的电极作为源极,而底面的导出端作为漏极。通过控制MOS单元SW1和SW2的栅极可调节漏极电流。
理论上,本发明的栓可被设置在每一个N-MOS或者P-MOS单元中,也可每几个N-MOS或者P-MOS单元放置一个栓。为了提供击穿电压, MOS单元的漏电极和栅极间引入了轻掺杂漏区(LDD),可以有效提高芯片的击穿电压(BV),如图7所示。
经过试验,这种结构的垂直互补场效应管在BV为10V的情况下,其Ron(通态电阻)为1.8 mohm  2V(1.8 mohm  2V是指当栅电压从0变到2V时,通态电阻为1.8 mohm),Qgd(栅-漏电荷电容)为1nC (Vds=5V),FOM (品质因数)1.8 mohm-nC,Qg(栅电荷)为30 nC 2V。(30 nC 2V是指当栅电压从0变到2V时,栅电荷是30 nC。)
BV为35V情况下,Ron为3.7 mohm5V,Qgd为2nC,FOM 为7.4 mW-nC。
可见,其性能与标准CMOS相似。
应当指出,本实施例仅列示性说明本发明的原理及功效,而非用于限制本发明。任何熟悉此项技术的人员均可在不违背本发明的精神及范围下,对上述实施例进行修改。因此,本发明的权利保护范围,应如权利要求书所列。

Claims (7)

1.垂直互补场效应管,包括至少两个MOS单元,其特征在于:还包括衬底层和设于衬底层上的中间层,该中间层与一个MOS单元对应处嵌有阱区,衬底层的PN极性与中间层相反,与阱区相同,所述的每个MOS单元包括一对PN同性电极和一个栅极,两个MOS单元的电极PN极性相反,其中一对电极设于中间层上并能在栅极控制下在中间层形成导通沟道,另一对电极设于阱上并能在栅极控制下在阱中形成导通沟道,所述的衬底层局部延伸入中间层并形成位于两个MOS单元之间的栓部,衬底层的下侧设有导出端,当两个MOS单元的栅极施加开通电压后,形成MOS单元-栓部-衬底层-导出端的两个导流通道。
2.根据权利要求1所述的垂直互补场效应管,其特征在于:所述的衬底层为N+材料,中间层为P-材料,阱区为N-材料,位于中间层上的MOS单元两个电极均为N+材料,而位于阱区的MOS单元两个电极均为P+材料。
3.根据权利要求1所述的垂直互补场效应管,其特征在于:所述的衬底层为P+材料,中间层为N-材料,阱区为P-材料,位于中间层上的MOS单元两个电极均为P+材料,而位于阱区的MOS单元两个电极均为N+材料。
4.垂直互补场效应管,包括至少两个MOS单元,其特征在于:还包括衬底层和设于衬底层上的中间层,两个MOS单元设于中间层上且共用一个电极,另两个电极则作为两个导入端,这三个电极的PN极性都相同且与中间层相反,所述的衬底层局部延伸入中间层形成栓部并与共用电极连通,衬底层的下侧设有导出端,衬底层与电极的PN极性相同,当两个MOS单元的栅极施加开通电压后,形成导入端电极-共用电极-栓部-衬底层-导出端的两个导流通道。
5.根据权利要求4所述的垂直互补场效应管,其特征在于:所述的衬底层为N+材料,中间层为P-材料,位于中间层上的MOS单元两个电极均为N+材料。
6.根据权利要求4所述的垂直互补场效应管,其特征在于:所述的衬底层为P+材料,中间层为N-材料,位于中间层上的MOS单元两个电极均为P+材料。
7.根据权利要求4所述的垂直互补场效应管,其特征在于:在所述MOS单元的漏电极和栅极间设置轻掺杂漏区,来有效提高芯片的击穿电压。
CN201110056548.4A 2011-03-09 2011-03-09 垂直互补场效应管 Expired - Fee Related CN102684485B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201110056548.4A CN102684485B (zh) 2011-03-09 2011-03-09 垂直互补场效应管
TW100145689A TWI447853B (zh) 2011-03-09 2011-12-12 Vertical complementary field effect transistor
US13/413,175 US8476710B2 (en) 2011-03-09 2012-03-06 Vertical complementary FET

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110056548.4A CN102684485B (zh) 2011-03-09 2011-03-09 垂直互补场效应管

Publications (2)

Publication Number Publication Date
CN102684485A CN102684485A (zh) 2012-09-19
CN102684485B true CN102684485B (zh) 2015-01-21

Family

ID=46794757

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110056548.4A Expired - Fee Related CN102684485B (zh) 2011-03-09 2011-03-09 垂直互补场效应管

Country Status (3)

Country Link
US (1) US8476710B2 (zh)
CN (1) CN102684485B (zh)
TW (1) TWI447853B (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0267447A2 (en) * 1986-11-12 1988-05-18 SILICONIX Incorporated A vertical DMOS power transistor with an integral operating condition sensor
US6465291B1 (en) * 2001-01-24 2002-10-15 Power Integrations, Inc. High-voltage transistor with buried conduction layer
CN1375879A (zh) * 2001-02-16 2002-10-23 佳能株式会社 半导体器件及其制造方法和喷液设备
CN1802752A (zh) * 2003-11-25 2006-07-12 松下电器产业株式会社 半导体元件
CN101267000A (zh) * 2008-04-29 2008-09-17 西安理工大学 氧化物填充扩展沟槽栅超结mosfet及其制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS632370A (ja) * 1986-06-23 1988-01-07 Nissan Motor Co Ltd 半導体装置
US4896196A (en) * 1986-11-12 1990-01-23 Siliconix Incorporated Vertical DMOS power transistor with an integral operating condition sensor
JP2001119022A (ja) * 1999-10-20 2001-04-27 Fuji Electric Co Ltd 半導体装置及びその製造方法
US6642583B2 (en) * 2001-06-11 2003-11-04 Fuji Electric Co., Ltd. CMOS device with trench structure
US7061057B2 (en) * 2004-06-16 2006-06-13 Cree Microwave, Llc Laterally diffused MOS transistor having N+ source contact to N-doped substrate

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0267447A2 (en) * 1986-11-12 1988-05-18 SILICONIX Incorporated A vertical DMOS power transistor with an integral operating condition sensor
US6465291B1 (en) * 2001-01-24 2002-10-15 Power Integrations, Inc. High-voltage transistor with buried conduction layer
CN1375879A (zh) * 2001-02-16 2002-10-23 佳能株式会社 半导体器件及其制造方法和喷液设备
CN1802752A (zh) * 2003-11-25 2006-07-12 松下电器产业株式会社 半导体元件
CN101267000A (zh) * 2008-04-29 2008-09-17 西安理工大学 氧化物填充扩展沟槽栅超结mosfet及其制造方法

Also Published As

Publication number Publication date
TW201246455A (en) 2012-11-16
TWI447853B (zh) 2014-08-01
CN102684485A (zh) 2012-09-19
US20120228698A1 (en) 2012-09-13
US8476710B2 (en) 2013-07-02

Similar Documents

Publication Publication Date Title
US9530885B2 (en) Normally on high voltage switch
US9673319B2 (en) Power semiconductor transistor with improved gate charge
CN105895692B (zh) 具有补偿结构的半导体器件
US9306064B2 (en) Semiconductor device and integrated apparatus comprising the same
WO2013185604A1 (zh) 一种高压结型场效应晶体管
US20150061008A1 (en) Ldmosfet having a bridge region formed between two gate electrodes
US20110115019A1 (en) Cmos compatible low gate charge lateral mosfet
US11114559B2 (en) Semiconductor device having reduced gate charges and superior figure of merit
CN103296081A (zh) 一种横向双扩散金属氧化物半导体场效应晶体管
CN103928464A (zh) 复合器件及开关电源
CN100576541C (zh) 一种半导体器件及其提供的低压电源的应用
CN100464421C (zh) 集成增强型和耗尽型垂直双扩散金属氧化物场效应管
CN106887451B (zh) 超结器件及其制造方法
US20140167158A1 (en) Integrated device and method for fabricating the integrated device
JP5056147B2 (ja) 半導体装置
CN102684485B (zh) 垂直互补场效应管
CN103489865B (zh) 一种横向集成soi半导体功率器件
CN203787431U (zh) 复合器件及开关电源
US8294215B2 (en) Low voltage power supply
CN101964329B (zh) 150v-bcd体硅制造工艺和lcd背光驱动芯片
US20180286860A1 (en) Cmos compatible low gate charge high voltage pmos
CN112151533B (zh) 一种双向导电的功率半导体器件结构
CN108091696A (zh) 一种逆阻型vdmos器件
CN103311277A (zh) 半导体结构及其制备方法
CN105070757A (zh) 改善超级结器件的开关特性的结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20150121

Termination date: 20160309