TWI447853B - Vertical complementary field effect transistor - Google Patents

Vertical complementary field effect transistor Download PDF

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TWI447853B
TWI447853B TW100145689A TW100145689A TWI447853B TW I447853 B TWI447853 B TW I447853B TW 100145689 A TW100145689 A TW 100145689A TW 100145689 A TW100145689 A TW 100145689A TW I447853 B TWI447853 B TW I447853B
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mos
intermediate layer
electrodes
layer
substrate
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TW201246455A (en
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Qin Huang
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
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Description

垂直互補場效應管
本發明涉及半導體技術，主要用於形成直流-直流變換器(DC/DC Converter)中積木式組件的垂直互補場效應管。
目前產業中，積木式元件(Building Block)被廣泛地應用於各種電路設計及生產中。積木式元件包括分離的電源開關、電感器、電容器等，為了提高功率密度和開關頻率，設計高度集成的積木式組件顯得很有必要；如第一圖所示，主要係為一種直流-直流變換器的原理圖，SW1和SW2為兩個MOS管開關，對應這種電路，應用於CMOS技術，可以將SW1和SW2集成在一個積木式元件中，現有集成CMOS結構如第二圖所示，當兩個PN極性相反的MOS單元分別設在P襯底(p-substrate)和N井(n-well)上時，SW1、SW2的源極和漏極都設在上表面，SW1的漏極、SW2的源極分別接Vin電位和GND電位，SW2的漏極、SW1的源極則相接並輸出電位VX，通過控制SW1、SW2的開關來控制VX電位；這種結構會存在有如下問題：
1.這種橫向結構因為側電流的影響容易在P襯底和N井中產生自偏效應，限制了晶片的尺寸，進一步也限制了轉換器的額定電流；
2.和分離結構相比，擊穿電壓較小；
3.晶片表面有三個電流端子(Vin、GND、VX)，也限制了功率密度和晶片的尺寸。
為了解決現有技術中存在的問題，本發明提供一種垂直互補場效應管及方法，通過改進晶片結構，來減小對晶片尺寸的限制，並提高擊穿電壓；本發明可依據不同方式形成如下的技術方案：其中第一種垂直互補場效應管，主要包括至少兩個MOS單元，特徵在於還包括襯底層和設於襯底層上的中間層，該中間層與一個MOS單元對應處嵌有井區，襯底層的PN極性與中間層相反，與井區相同，而前述的每個MOS單元包括有一對PN同性電極和一個柵極，兩個MOS單元的電極PN極性相反，其中一對電極設於中間層上並能在柵極控制下在中間層形成導通溝道，而另一對電極設於井上並能在柵極控制下在井中形成導通溝道，前述的襯底層局部延伸入中間層並形成位於兩個MOS單元之間的栓部，襯底層的下側設有匯出端，當兩個MOS單元的柵極施加開通電壓後，形成MOS單元-栓部-襯底層-匯出端的兩個導流通道；而作為對上述技術方案的完善和補充，本發明進一步採取如下技術措施或是這些措施的任意組合：當所述的襯底為N+材料時，中間層則為P-材料，井區則為N-材料，位於中間層上的MOS單元兩個電極則均為N+材料，而位於井區的MOS單元兩個電極則均為P+材料。
當所述的襯底為P+材料時，中間層則為N-材料，井區則為P-材料，位於中間層上的MOS單元兩個電極則均為P+材料，而位於井區的MOS單元兩個電極則均為N+材料。
本發明之垂直互補場效應管的另一較佳實施方案，亦可為包括至少兩個MOS單元，其特徵在於：包括襯底層和設於襯底層上的中間層，兩個MOS單元設於中間層上且共用一個電極，另兩個電極則作為兩個導入端，這三個電極的PN極性都相同且與中間層相反，所述的襯底層局部延伸入中間層形成栓部並與共用電極連通，襯底層的下側設有匯出端，襯底層與電極的PN極性相同，當兩個MOS單元的柵極施加開通電壓後，形成導入端電極-共用電極-栓部-襯底層-匯出端的兩個導流通道；而作為對上述技術方案的完善和補充，本發明進一步採取如下技術措施或是這些措施的任意組合：當所述的襯底為N+材料時，中間層則為P-材料，位於中間層上的兩個MOS單元的兩個電極則均為N+材料；當所述的襯底為P+材料時，中間層則為N-材料，位於中間層上的兩個MOS單元的兩個電極則均為P+材料。
同時在所述MOS單元的漏電極和柵極間設置有輕摻雜漏區，用來有效提高晶片的擊穿電壓。
藉由上述的技術方案，本發明通過設置豎向的栓引導電流豎向流動，改原有的橫向結構為豎向結構，避免橫向側電流引起自偏效應，且晶片表面只需要兩個電流端子，有助於增大晶片尺寸和功率密度，提高轉換器的額定電流，更由於增加了中間層，在採用低摻雜漏(LDD)技術的情況下，可以有效增大擊穿電壓，構件運用時更加安全；本發明還可以採用修改過的CMOS工藝來展現，除了實現本方面中描述的結構外，還可以實現標準的模擬和數位積體電路等功能。
請參閱第三圖所示之垂直互補場效應管，N+襯底上為P-中間層，中間層一般為外延層，P-中間層裡有N-井層，MOS單元SW1和SW2分別設在P-中間層和N-井層上，N+襯底局部上延伸入中間層形成一個N+栓(Plug)，N+襯底下側為匯出端。SW1的漏極和SW2的源極接有兩個電流端子，分別用於連接Vin電位和GND電位，匯出端用於輸出電位VX。工作室電流流向如圖中箭頭所示，主要沿豎向流動，避免了橫向結構存在的自偏效應；再請參閱第四圖所示之垂直互補場效應管，結構與第三圖相似，區別則在於各層PN極性係為相反者；再請參閱第五圖所示之垂直互補場效應管，N+襯底上為P-中間層，中間層可為P-外延層或P-井，MOS單元SW1和SW2共用一個電極，三個電極都設在中間層上，N+襯底局部上延伸入中間層直至共用電極形成一個N+栓，N+襯底下側為匯出端。N+栓將SW1和SW2相互隔離，能更好避免側電流的影響，其工作室電流流向同樣如圖中箭頭所示；另外，可將第五圖的結構略作改進後則可將本發明結構用於單個MOS管場合，如第六圖所示，，即為將晶片表面的三個電極連通，在這種結構中，表面的電極作為源極，而底面的匯出端作為漏極，通過控制MOS單元SW1和SW2的柵極可調節漏極電流；在理論上，本發明的栓可被設置在每一個N-MOS或者P-MOS單元中，也可每幾個N-MOS或者P-MOS單元放置一個栓，而為了提供擊穿電壓，MOS單元的漏電極和柵極間引入了輕摻雜漏區(LDD)，則可以有效提高晶片的擊穿電壓(BV)，如第七圖所示；經過試驗結果顯示，這種結構的垂直互補場效應管在BV為10V的情況下，其Ron(通態電阻)為1.8 mohm @ 2V，Qgd(柵-漏電荷電容)為1nC(Vds=5V)，FOM(品質因數)1.8 mohm-nC，Qg(柵電荷)為30 nC @2V；BV為35V情況下，Ron為3.7 mohm@5V，Qgd為2nC，FOM為7.4 mW-nC；因此，其性能與漂準CMOS相似；本發明上述僅列示性說明本發明的基本原理及功效，而非用於限制本發明。任何熟悉此項技術的人員均可在不違背本發明的精神及範圍下，對上述實施例進行修改，因此，本發明的權利保護範圍，應如權利要求書所列。
第一圖：係為習用技術之直流-直流變換器的原理圖；
第二圖：係為習用技術之直流-直流變換器晶片結構示意圖；
第三圖：係為本發明晶片結構示意圖；
第四圖：係為本發明另一實施例之晶片結構示意圖；
第五圖：係為本發明另一實施例之晶片結構示意圖；
第六圖：係為本發明用作單個MOS開關時的結構示意圖；
第七圖：係為本發明有LDD區域時的結構示意圖；

Claims (7)

  1. 一種垂直互補場效應管，包括至少兩個MOS單元，其特徵在於：包括有一襯底層和一設於襯底層上的中間層，在該中間層與一個MOS單元對應處係嵌有井區，該襯底層的PN極性與中間層相反，與井區相同，前述的每個MOS單元包括一對PN同性電極和一個柵極，兩個MOS單元的電極PN極性相反，其中一對電極設於中間層上並能在柵極控制下在中間層形成導通溝道，另一對電極設於井區上並能在柵極控制下在井區中形成導通溝道，所述的襯底層局部延伸入中間層並形成位於兩個MOS單元之間的栓部，襯底層的下側設有匯出端，當兩個MOS單元的柵極施加開通電壓後，形成MOS單元-栓部-襯底層-匯出端的兩個導流通道。
  2. 根據申請專利範圍第1項所述之垂直互補場效應管，其中，當襯底為N+材料時，中間層則為P-材料，井區則為N-材料，位於中間層上的MOS單元兩個電極則均為N+材料，而位於井區的MOS單元兩個電極則均為P+材料。
  3. 根據申請專利範圍第1項所述之垂直互補場效應管，其中，當襯底為P+材料時，中間層則為N-材料，井區則為P-材料，位於中間層上的MOS單元兩個電極則均為P+材料，而位於井區的MOS單元兩個電極則均為N+材料。
  4. 一種垂直互補場效應管，包括至少兩個MOS單元，其特徵在於：包括襯底層和設於襯底層上的中間層，兩個MOS單元設於中間層上且共用一個電極，另兩個電極則作為兩個導入端，這三個電極的PN極性都相同且與中間層相反，其中，該襯底層局部延伸入中間層形成栓部並與共用電極連通，襯底層的下側則設有匯出端，襯底層與電極的PN極性相同，當兩個MOS單元的柵極施加開通電壓後，形成導入端電極-共用電極-栓部-襯底層-匯出端的兩個導流通道。
  5. 根據申請專利範圍第4項所述之垂直互補場效應管，其中，該襯底為N+材料時，中間層則為P-材料，位於中間層上的MOS單元兩個電極則均為N+材料。
  6. 根據申請專利範圍第4項所述之垂直互補場效應管，其中，該襯底為P+材料時，中間層則為N-材料，位於中間層上的MOS單元兩個電極則均為P+材料。
  7. 根據申請專利範圍第4項所述之垂直互補場效應管，其中，該MOS單元的漏電極和柵極間設置有輕摻雜漏區，用來有效提高晶片的擊穿電壓。
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