TWI721140B - 半導體裝置以及半導體裝置的製造方法 - Google Patents

半導體裝置以及半導體裝置的製造方法 Download PDF

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TWI721140B
TWI721140B TW106110211A TW106110211A TWI721140B TW I721140 B TWI721140 B TW I721140B TW 106110211 A TW106110211 A TW 106110211A TW 106110211 A TW106110211 A TW 106110211A TW I721140 B TWI721140 B TW I721140B
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oxide film
concentration
well region
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森田健士
津村和宏
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日商艾普凌科有限公司
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Abstract

本發明提供一種能夠容易地調整半導體裝置的靜電保護元件的耐壓的構造。在將N通道型MOS電晶體作為靜電保護元件的半導體裝置中，N通道型MOS電晶體設為包含如下區域的構造：縱方向的電場緩和區域，具有自N型高濃度汲極區域向下減少的三種不同的雜質濃度；橫方向的電場緩和區域，具有自N型高濃度汲極區域向通道區域減少的三種不同的雜質濃度；以及雜質濃度最低的電場緩和區域，與縱方向的電場緩和區域及橫方向的電場緩和區域相接。

Description

半導體裝置以及半導體裝置的製造方法
本發明是有關於一種使用N通道型金屬氧化物半導體（metal oxide semiconductor、MOS）電晶體作為靜電保護元件的半導體裝置。
在使用MOS型電晶體作為靜電保護元件的半導體裝置中，經常使用將N通道型MOS電晶體的汲極連接於外部端子，使閘極電位及源極電位接地，在斷開狀態下使用的所謂截止電晶體（off transistor）。
當對進行高電壓動作的元件進行保護時，使用在所述N通道型MOS電晶體的汲極的周圍在通道區域與汲極區域之間包含場氧化膜（field oxidation film）的高耐壓構造。並且，為了提高耐壓及減小導通電阻，使用在N型高濃度汲極區域周邊包含雜質濃度不同的N型低濃度擴散區域的高耐壓構造（例如，參照專利文獻1）。 [現有技術文獻] [專利文獻]
[專利文獻1]日本專利特開2007-266473號公報
[發明所欲解決的問題] 在用作靜電保護元件的N通道型MOS電晶體中，要求具備如下電氣特性的構造：理想的是具有半導體裝置的額定電壓以上的第一崩潰電壓（first breakdown voltage）及第二崩潰電壓（second breakdown voltage），並且形成為分別低於內部元件的第一崩潰電壓及第二崩潰電壓的第一崩潰電壓及第二崩潰電壓。通常若提高耐壓，則導通電阻升高，因此當為了降低導通電阻而提高低濃度擴散區域的濃度時，有時第一崩潰電壓會下降而低於半導體裝置的額定電壓或工作電壓（operation voltage），從而無法滿足所需的特性。另一方面，當忽視導通電阻而設為低濃度以提高耐壓時，有時第二崩潰電壓會上升而無法保護內部元件。
再者，第一崩潰電壓及第二崩潰電壓是在MOS電晶體的汲極源極電流-汲極源極電壓（drain source current-drain source voltage，IDS-VDS）特性中加以界定。圖5中表示示意性的IDS-VDS特性。第一崩潰電壓是在將閘極電壓保持為0 V，而提高汲極-源極間的電壓VDS的情況下，汲極電流IDS開始上升的電壓。第二崩潰電壓是在進一步提高汲極-源極間的電壓VDS的情況下汲極-源極間的電阻急遽減小，開始流入大電流的電壓。
本發明是鑒於所述問題而完成的，其提供一種可不進行濃度變更而藉由擴散間的距離來容易地調整半導體裝置的靜電保護元件的耐壓的構造。 [解決問題的手段]
為了解決所述問題，在本發明中使用以下的方法。
首先，設為如下的半導體裝置，其包含N通道型MOS電晶體，所述N通道型MOS電晶體包括：場氧化膜及閘極氧化膜，設置於半導體基板上；閘極電極，設置於所述閘極氧化膜上，一端在所述場氧化膜上延伸而配置；N型高濃度源極區域，設置於所述閘極電極的另一端；通道區域，夾於所述N型高濃度源極區域與所述場氧化膜的一個端部之間，設置於所述閘極氧化膜下；N型高濃度汲極區域，設置於所述場氧化膜的成為所述一個端部的相反側的另一個端部；以及電場緩和區域，設置於所述場氧化膜的下方，即設置於所述N型高濃度汲極區域的周圍；所述半導體裝置的特徵在於：設置於所述場氧化膜下的N型中濃度擴散區域包含自所述N型高濃度汲極區域至所述通道區域具有多個雜質濃度的區域。
並且，設為如下的半導體裝置的製造方法，所述半導體裝置包含N通道型MOS電晶體，所述N通道型MOS電晶體包括：場氧化膜及閘極氧化膜，設置於半導體基板上；閘極電極，設置於所述閘極氧化膜上，一端在所述場氧化膜上延伸而配置；N型高濃度源極區域，設置於所述閘極電極的另一端；通道區域，夾於所述N型高濃度源極區域與所述場氧化膜的一個端部之間，設置於所述閘極氧化膜下；N型高濃度汲極區域，設置於所述場氧化膜的成為所述一個端部的相反側的另一個端部；以及電場緩和區域，設置於所述場氧化膜的下方，即設置於所述N型高濃度汲極區域的周圍；所述半導體裝置的製造方法的特徵在於包括： 在半導體基板的表面上形成P型阱區域及第一N型阱區域步驟；將第二N型阱區域形成淺於所述第一N型阱區域步驟；將N型雜質離子植入至場氧化膜的形成區域下，經氧化擴散而同時形成場氧化膜及N型中濃度擴散區域步驟；在無所述場氧化膜的區域內形成通道區域步驟；在所述通道區域的表面上形成閘極氧化膜；在所述閘極氧化膜上形成閘極電極步驟；將所述閘極電極及所述場氧化膜作為遮罩離子植入高濃度的N型雜質而形成N型高濃度源極區域及N型高濃度汲極區域步驟；層間絕緣膜形成步驟；接觸通路（contact via）形成步驟；配線步驟；以及保護膜形成步驟。 [發明的效果]
藉由使用所述方法，將靜電保護元件的電壓特性調整為所需值變得容易。
根據本發明，對第一崩潰電壓及第二崩潰電壓造成影響的構造是通道區域與N型低濃度擴散區域（第二N型阱區域）之間的距離、N型低濃度擴散區域（第二N型阱區域）與第一N型阱區域之間的距離，對第二崩潰電壓造成影響的構造是N型低濃度擴散區域（第二N型阱區域）與N型高濃度擴散區域（N型高濃度汲極區域）之間的距離，藉由對所述構造之中的任一個距離在保持其他兩個距離的狀態下進行改變，便可調整成所需的第一崩潰電壓及第二崩潰電壓。
以下，利用圖式，對本發明中的成為半導體裝置的實施形態的靜電保護元件進行說明。
圖1表示成為作為本發明的實施例的半導體裝置的利用N通道型MOS電晶體的靜電保護元件的示意剖面圖。
N通道型MOS電晶體是用於高耐壓的橫向擴散金屬氧化物半導體（laterally diffused metal oxide semiconductor，LDMOS）構造，在導電型為P型或N型的半導體基板100上設置有P型阱區域101及N型阱區域102。在形成於P型阱區域101的基板表面的一部分上的閘極氧化膜106上設置有閘極電極108，閘極電極108的一部分在藉由矽局部氧化（Local Oxidation of Silicon，LOCOS）法而形成於基板上的場氧化膜104上延伸。在閘極電極108的一個端部設置有N型高濃度源極區域109，在夾於所述N型高濃度源極區域109與場氧化膜104之間的閘極氧化膜106下形成有通道區域107。在場氧化膜104的一端載置有閘極電極108的一部分，在位於另一端的下方的N型阱區域102的基板表面上自基板表面起以0.4 μm的深度設置有N型高濃度汲極區域110。在場氧化膜104下形成有N型中濃度擴散區域105。
N型中濃度擴散區域105的雜質濃度為4～10 e16/cm3 ，設置於自場氧化膜104的底部起0.5 μm的深度。並且，在N型阱區域102內設置有擴散深度大於N型中濃度擴散區域105的N型低濃度擴散區域103。所述N型低濃度擴散區域103自N型阱區域102抵達至P型阱區域101的一部分為止，其端部是以與閘極電極108不重疊的方式而擴散形成。
此處，區域a至區域f成為位於N型高濃度汲極區域110的周圍的N型中濃度擴散區域105、N型低濃度擴散區域103、N型阱區域102及P型阱區域101單獨地或藉由重合而形成的電場緩和區域，將所述區域a至區域f界定如下。再者，關於基板，由於是共同的，故而不加以提及。
設為區域a僅包含N型阱區域102，區域b為N型阱區域102與N型低濃度擴散區域103重疊的區域，區域c為N型阱區域102、N型低濃度擴散區域103與N型中濃度擴散區域105重疊的區域，區域d為N型中濃度擴散區域105、N型低濃度擴散區域103與P型阱區域101重疊的區域，區域e為N型中濃度擴散區域105與P型阱區域101重疊的區域，區域f為N型低濃度擴散區域103與P型阱區域101重疊的區域。
其結果為形成如下的電場緩和區域：在橫方向，自通道區域107向N型高濃度汲極區域110按照區域e→區域d→區域c的順序雜質濃度逐漸升高，在縱方向，自N型阱區域102向N型高濃度汲極區域110按照區域a→區域b→區域c的順序雜質濃度逐漸升高。此外，區域f是包含雜質濃度最低的N型擴散區域的電場緩和區域。N通道型MOS電晶體的第一崩潰電壓或第二崩潰電壓藉由該些六個雜質濃度不同的電場緩和區域即N型擴散區域的配置而發生變化。
圖2是表示使N型低濃度擴散區域103與N型阱區域102之間的距離以及N型低濃度擴散區域103與N型高濃度擴散區域即N型高濃度汲極區域110與N型高濃度源極區域109之間的距離保持固定，而使通道區域107與N型低濃度擴散區域103之間的距離X1發生變化時的靜電保護元件的特性變化的圖。第一崩潰電壓及第二崩潰電壓的兩個特性發生變化。即，顯示出若距離X1增大，則第一崩潰電壓及第二崩潰電壓升高的傾向。
圖3是表示使N型低濃度擴散區域103與N型高濃度擴散區域即N型高濃度汲極區域110與N型高濃度源極區域109之間的距離以及通道區域107與N型低濃度擴散區域103之間的距離保持固定，而使N型低濃度擴散區域103與N型阱區域102之間的距離X2發生變化時的靜電保護元件的特性變化的圖。第一崩潰電壓及第二崩潰電壓的兩個特性發生變化。即，顯示出若距離X2增大，則第一崩潰電壓升高，第二崩潰電壓降低的傾向。
圖4是表示使通道區域107與N型低濃度擴散區域103之間的距離以及N型低濃度擴散區域103與N型阱區域102之間的距離保持固定，而使N型低濃度擴散區域103與N型高濃度汲極區域110之間的距離X3發生變化時的靜電保護元件的特性變化的圖。第一崩潰電壓保持固定，僅使第二崩潰電壓發生變化。即，若距離X3增大，則第二崩潰電壓升高，而第一崩潰電壓為大致固定。
當欲獲得所需的第一崩潰電壓及第二崩潰電壓的N通道型MOS電晶體的靜電保護元件時，例如，藉由如圖2所示僅變更通道區域與N型低濃度擴散區域之間的距離X1，或如圖3所示僅變更N型低濃度擴散區域與N型阱區域之間的距離X2來改變第一崩潰電壓及第二崩潰電壓，而調整成所需的第一崩潰電壓，其次，藉由如圖4所示僅變更N型低濃度擴散區域與N型高濃度擴散區域之間的距離X3而在保持著第一崩潰電壓的狀態下調整成所需的第二崩潰電壓，藉此可獲得具有所需的第一崩潰電壓及第二崩潰電壓的N通道型MOS電晶體的靜電保護元件。
如以上所述，在使用用作靜電保護元件的N通道型MOS電晶體的半導體裝置中，需要具備分別低於內部元件的第一崩潰電壓及第二崩潰電壓的第一崩潰電壓及第二崩潰電壓的靜電保護元件，若使用所述方法，可容易地獲得具有所需的崩潰電壓的N通道型MOS電晶體的靜電保護元件。
其次，利用圖1對本發明的半導體裝置的靜電保護元件的製造方法進行簡單說明。
首先，半導體基板100也在表面上以5 μm左右的深度形成P型阱區域101及N型阱區域102。其次，以達到淺於N型阱區域102的1 μm～2 μm左右的深度形成第二N型阱區域即N型低濃度擴散區域103。所述N型低濃度擴散區域103不僅形成於N型阱區域102上，而且形成至P型阱區域101的一部分上，構成成為圖1的區域b、區域c、區域d、區域f的電場緩和區域。
在場氧化膜104形成區域下離子植入作為N型雜質的磷（P）之後經氧化擴散而同時形成場氧化膜104及N型中濃度擴散區域105。所形成的N型中濃度擴散區域105以單體計為5 e16/cm3 左右的濃度，但在圖1的區域e內由於P型阱區域101而使N型雜質濃度減少，在區域d內由於N型低濃度擴散區域103而使N型雜質濃度高於單體濃度，區域c內的N型雜質濃度則進一步升高。
其次，在無場氧化膜104的區域內離子植入用於通道區域107的雜質部，然後，在通道區域107上的半導體基板表面上形成閘極氧化膜106，進而在其上形成閘極電極108。然後，將閘極電極108及場氧化膜104作為遮罩離子植入高濃度的N型雜質而形成N型高濃度源極區域109及N型高濃度汲極區域110。雖未圖示，但進而可經由層間絕緣膜形成步驟、接觸通路形成步驟、配線步驟、保護膜形成步驟等而形成本發明的半導體裝置。
此處，藉由如圖2所示僅變更通道區域與N型低濃度擴散區域之間的距離X1，或如圖3所示僅變更N型低濃度擴散區域與N型阱區域之間的距離X2，來改變第一崩潰電壓及第二崩潰電壓，而調整成所需的第一崩潰電壓，其次，藉由如圖4所示僅變更N型低濃度擴散區域與N型高濃度擴散區域之間的距離X3而在保持著第一崩潰電壓的狀態下調整成所需的第二崩潰電壓，藉此可製造出包含具有所需的第一崩潰電壓及第二崩潰電壓的N通道型MOS電晶體的靜電保護元件的半導體裝置。
100‧‧‧半導體基板 101‧‧‧P型阱區域 102‧‧‧N型阱區域 103‧‧‧N型低濃度擴散區域（第二N型阱區域） 104‧‧‧場氧化膜 105‧‧‧N型中濃度擴散區域 106‧‧‧閘極氧化膜 107‧‧‧通道區域 108‧‧‧閘極電極 109‧‧‧N型高濃度源極區域 110‧‧‧N型高濃度汲極區域 X1‧‧‧通道區域～N型低濃度擴散區域之間距離 X2‧‧‧N型低濃度擴散區域～N型阱區域之間距離 X3‧‧‧N型低濃度擴散區域～N型高濃度汲極區域之間距離 a、b、c、d、e、f‧‧‧N型擴散區域（電場緩和區域） IDS‧‧‧汲極源極電流 VDS‧‧‧汲極源極電壓
圖1是作為本發明的實施例的半導體裝置的靜電保護元件的示意剖面圖。 圖2是作為本發明的實施例的半導體裝置的靜電保護元件的特性圖。 圖3是作為本發明的實施例的半導體裝置的靜電保護元件的特性圖。 圖4是作為本發明的實施例的半導體裝置的靜電保護元件的特性圖。 圖5是N通道型MOS電晶體的IDS-VDS特性圖。
100‧‧‧半導體基板
101‧‧‧P型阱區域
102‧‧‧N型阱區域
103‧‧‧N型低濃度擴散區域(第二N型阱區域)
104‧‧‧場氧化膜
105‧‧‧N型中濃度擴散區域
106‧‧‧閘極氧化膜
107‧‧‧通道區域
108‧‧‧閘極電極
109‧‧‧N型高濃度源極區域
110‧‧‧N型高濃度汲極區域
X1‧‧‧通道區域~N型低濃度擴散區域之間距離
X2‧‧‧N型低濃度擴散區域~N型阱區域之間距離
X3‧‧‧N型低濃度擴散區域~N型高濃度汲極區域之間距離
a、b、c、d、e、f‧‧‧N型擴散區域(電場緩和區域)

Claims (6)

  1. 一種半導體裝置，包含N通道型MOS電晶體，所述N通道型MOS電晶體包括：場氧化膜及閘極氧化膜，設置於半導體基板上；閘極電極，設置於所述閘極氧化膜上，一端在所述場氧化膜上延伸而配置；N型高濃度源極區域，設置於所述閘極電極的另一端；通道區域，夾於所述N型高濃度源極區域與所述場氧化膜的一個端部之間，設置於所述閘極氧化膜下；N型高濃度汲極區域，設置於所述場氧化膜的成為所述一個端部的相反側的另一個端部；以及多個電場緩和區域，設置於所述場氧化膜的下方，即設置於所述N型高濃度汲極區域的周圍；所述半導體裝置的特徵在於：所述多個電場緩和區域包括：縱方向的電場緩和區域，具有自所述N型高濃度汲極區域向下減少的三種不同的雜質濃度；橫方向的電場緩和區域，具有自所述N型高濃度汲極區域向所述通道區域減少的三種不同的雜質濃度；以及雜質濃度最低的電場緩和區域，與所述縱方向的電場緩和區域及所述橫方向的電場緩和區域相接，所述多個電場緩和區域是N型中濃度擴散區域與P型阱區域及第一N型阱區域與第二N型阱區域重疊的區域。
  2. 如申請專利範圍第1項所述的半導體裝置，其中所述第一N型阱區域的半導體基板內深大於所述第二N型阱區域，所述第二N 型阱區域的半導體基板內深大於所述N型中濃度擴散區域。
  3. 如申請專利範圍第1項或第2項所述的半導體裝置，其中所述第二N型阱區域與在所述場氧化膜上延伸的所述閘極電極不重疊。
  4. 一種半導體裝置的製造方法，所述半導體裝置包含N通道型MOS電晶體，所述N通道型MOS電晶體包括：場氧化膜及閘極氧化膜，設置於半導體基板上；閘極電極，設置於所述閘極氧化膜上，一端在所述場氧化膜上延伸而配置；N型高濃度源極區域，設置於所述閘極電極的另一端；通道區域，夾於所述N型高濃度源極區域與所述場氧化膜的一個端部之間，設置於所述閘極氧化膜下；N型高濃度汲極區域，設置於所述場氧化膜的成為所述一個端部的相反側的另一個端部上；以及多個電場緩和區域，設置於所述場氧化膜的下方，即設置於所述N型高濃度汲極區域的周圍；所述半導體裝置的製造方法的特徵在於包括：在半導體基板的表面上形成P型阱區域及第一N型阱區域步驟；將第二N型阱區域形成淺於所述第一N型阱區域步驟；將N型雜質離子植入至場氧化膜的形成區域下，經氧化擴散而同時形成所述場氧化膜及N型中濃度擴散區域步驟；在無所述場氧化膜的區域內形成通道區域步驟； 在所述通道區域的表面上形成閘極氧化膜步驟；在所述閘極氧化膜上形成閘極電極步驟；將所述閘極電極及所述場氧化膜作為遮罩離子植入高濃度的N型雜質而形成N型高濃度源極區域及N型高濃度汲極區域步驟；層間絕緣膜形成步驟；接觸通路形成步驟；配線步驟；以及保護膜形成步驟。
  5. 如申請專利範圍第4項所述的半導體裝置的製造方法，更包括：調整所述通道區域與所述第二N型阱區域之間的距離步驟；以及調整所述第二N型阱區域與所述N型高濃度汲極區域之間的距離步驟。
  6. 如申請專利範圍第4項所述的半導體裝置的製造方法，更包括：調整所述第二N型阱區域與所述第一N型阱區域之間的距離步驟；以及調整所述第二N型阱區域與所述N型高濃度汲極區域之間的距離步驟。
TW106110211A 2016-03-30 2017-03-28 半導體裝置以及半導體裝置的製造方法 TWI721140B (zh)

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