JP2017183544A - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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JP2017183544A
JP2017183544A JP2016069165A JP2016069165A JP2017183544A JP 2017183544 A JP2017183544 A JP 2017183544A JP 2016069165 A JP2016069165 A JP 2016069165A JP 2016069165 A JP2016069165 A JP 2016069165A JP 2017183544 A JP2017183544 A JP 2017183544A
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region
type
oxide film
semiconductor device
type well
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JP6688653B2 (ja
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健士 森田
Takeshi Morita
健士 森田
津村　和宏
Kazuhiro Tsumura
和宏 津村
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Ablic Inc
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Ablic Inc
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Priority to US15/469,803 priority patent/US10096591B2/en
Priority to TW106110211A priority patent/TWI721140B/zh
Priority to CN201710195980.9A priority patent/CN107275401B/zh
Priority to KR1020170039818A priority patent/KR102255545B1/ko
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Priority to US16/123,349 priority patent/US10777544B2/en
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Abstract

【課題】半導体装置の静電気保護素子の耐圧を容易に調整できる構造を提供する。
【解決手段】Ｎチャネル型ＭＯＳトランジスタを静電気保護素子とする半導体装置において、Ｎチャネル型ＭＯＳトランジスタはＮ型高濃度ドレイン領域から下方に向かって減少する３種類の異なる不純物濃度を有する縦方向の電界緩和領域と、Ｎ型高濃度ドレイン領域から前記チャネル領域に向かって減少する３種類の異なる不純物濃度を有する横方向の電界緩和領域と、縦方向の電界緩和領域と横方向の電界緩和領域とに接する最も不純物濃度の低い電界緩和領域とを有する構造とした。
【選択図】図１

Description

本発明は、Ｎチャネル型ＭＯＳトランジスタを静電気保護素子として用いる半導体装置に関する。
ＭＯＳ型トランジスタを静電気保護素子として用いる半導体装置においては、Ｎチャネル型ＭＯＳトランジスタのドレインを外部端子につなぎ、ゲート電位およびソース電位を接地し、オフ状態で使用するいわゆるオフトランジスタがよく利用されている。
高耐圧動作を行う素子を保護する場合、このＮチャネル型ＭＯＳトランジスタのドレイン構造はチャネル領域とドレイン領域の間にフィールド酸化膜を備えた高耐圧構造が利用される。また、耐圧の向上及びオン抵抗を小さくするため、Ｎ型高濃度ドレイン領域周辺に不純物濃度の異なるＮ型低濃度拡散領域を備えた高耐圧構造が利用される（例えば、特許文献１参照）。
特開２００７−２６６４７３号公報
しかしながら、静電気保護素子として用いられるＮチャネル型ＭＯＳトランジスタにおいては、理想的には半導体装置の定格電圧以上のファーストブレークダウン電圧及びセカンドブレークダウン電圧を有するとともに、内部素子のファーストブレークダウン電圧及びセカンドブレークダウン電圧よりも低いファーストブレークダウン電圧及びセカンドブレークダウン電圧となっている電気特性を備えた構造が要求される。一般に耐圧を上げるとオン抵抗は高くなるので、オン抵抗を低くするために低濃度拡散領域を高濃度にした場合、ファーストブレークダウン電圧が下がって半導体装置の定格電圧や動作電圧を下回り、所望の特性を満たせないことがある。一方でオン抵抗を無視して耐圧を上げるために低濃度側にした場合にはセカンドブレークダウンが上がり内部素子を保護できないことがある。なお、ファーストブレークダウン電圧およびセカンドブレークダウン電圧はＭＯＳトランジスタのＩＤＳ−ＶＤＳ特性において定義される。図５に模式的なＩＤＳ−ＶＤＳ特性を示している。ファーストブレークダウン電圧はゲート電圧を０Ｖとしたまま、ドレイン−ソース間の電圧ＶＤＳを上げていったときに、ドレイン電流ＩＤＳが立ち上がり始める電圧である。セカンドブレークダウン電圧は、さらにドレイン−ソース間の電圧ＶＤＳを上げていった場合にドレイン−ソース間の抵抗が急激に小さくなり、大電流が流れ始める電圧である。
本発明は、上記課題に鑑みてなされたものであり、濃度変更を行わず拡散間の距離によって半導体装置の静電気保護素子の耐圧を容易に調整できる構造を提供する。
上記課題解決のために本発明では以下の手段を用いた。
まず、半導体基板上に設けられたフィールド酸化膜、およびゲート酸化膜と、前記ゲート酸化膜を介して設けられ、一部が前記フィールド酸化膜上に延在するゲート電極と、前記ゲート電極の一端に設けられたＮ型高濃度ソース領域と、前記Ｎ型高濃度ソース領域と前記フィールド酸化膜の一方の端部に挟まれ、前記ゲート酸化膜下に設けられたチャネル領域と、前記フィールド酸化膜の一方の端部の反対側の端部に設けられたＮ型高濃度ドレイン領域と、前記Ｎ型高濃度ドレイン領域の周囲に設けた電界緩和領域と、からなるＮチャネル型ＭＯＳトランジスタを有する半導体装置であって、前記フィールド酸化膜の下に設けられたＮ型中濃度拡散領域が前記高濃度ドレイン領域から前記チャネル領域にかけて複数の不純物濃度を有する領域からなることを特徴とする半導体装置とした。
また、半導体基板上に設けられたフィールド酸化膜、およびゲート酸化膜と、前記ゲート酸化膜を介して設けられ、一部が前記フィールド酸化膜上に延在するゲート電極と、前記ゲート電極の一端に設けられたＮ型高濃度ソース領域と、前記Ｎ型高濃度ソース領域と前記フィールド酸化膜の一方の端部に挟まれ、前記ゲート酸化膜下に設けられたチャネル領域と、前記フィールド酸化膜の一方の端部の反対側の端部に設けられたＮ型高濃度ドレイン領域と、前記Ｎ型高濃度ドレイン領域の周囲に設けた電界緩和領域と、からなるＮチャネル型ＭＯＳトランジスタを有する半導体装置の製造方法であって、
前記半導体基板も表面にＰ型ウェル領域および第１のＮ型ウェル領域を形成する工程と、第２のＮ型ウェル領域を前記第１のウェル領域よりも浅く形成する工程と、前記フィールド酸化膜形成領域下にＮ型不純物をイオン注入し、酸化拡散してフィールド酸化膜とＮ型中濃度拡散領域を同時に形成する工程と、前記フィールド酸化膜の無い領域にチャネル領域を形成する工程と、前記チャネル領域上にゲート酸化膜を介してゲート電極を形成する工程と、ゲート電極およびフィールド酸化膜をマスクとして高濃度のＮ型不純物をイオン注入してＮ型高濃度ソース領域およびＮ型高濃度ドレイン領域を形成する工程と、層間絶縁膜形成工程と、コンタクトビア形成工程と、配線工程と、保護膜形成工程と、からなることを特徴とする半導体装置の製造方法とした。
上記手段を用いることにより、静電気保護素子の電圧特性を所望の値に調整することが容易になる。
本発明によれば、ファーストブレークダウン及びセカンドブレークダウンに影響する構造は、チャネル領域とＮ型低濃度拡散領域間の距離、Ｎ型低濃度拡散領域とＮ型ウェル領域間の距離であり、セカンドブレークダウンに影響する構造はＮ型低濃度拡散領域とＮ型高濃度拡散領域間の距離の距離であり、この構造のうちどれかひとつの距離を他二つの距離を保った状態で変えることで所望のファーストブレークダウン電圧及びセカンドブレークダウン電圧に調整することが可能となる。
本発明の実施例である半導体装置の静電気保護素子の模式断面図である。 本発明の実施例である半導体装置の静電気保護素子の特性図である。 本発明の実施例である半導体装置の静電気保護素子の特性図である。 本発明の実施例である半導体装置の静電気保護素子の特性図である。 Ｎチャネル型ＭＯＳトランジスタのＩＤＳ−ＶＤＳ特性図である。
以下では図を用いて、本発明における半導体装置の静電気保護素子について説明する。
図１は本発明の実施例であるＮチャネル型ＭＯＳトランジスタを利用した静電気保護素子の模式断面図を表したものである。
Ｎチャネル型ＭＯＳトランジスタは高耐圧に利用されるＬＤＭＯＳ構造であり、導電型がＰ型またはＮ型の半導体基板１００にＰ型ウェル領域１０１とＮ型ウェル領域１０２が設けられている。Ｐ型ウェル領域１０１の基板表面に形成されたゲート酸化膜１０６を介してゲート電極１０８が設けられ、ゲート電極１０８の一部は基板上にＬＯＣＯＳ（Ｌｏｃａｌ Ｏｘｉｄａｔｉｏｎ ｏｆ Ｓｉｌｉｃｏｎ）法によって形成されたフィールド酸化膜１０４上に延在している。ゲート電極の一方の端部にはＮ型高濃度ソース領域１０９が設けられ、このＮ型高濃度ソース領域１０９とフィールド酸化膜１０４に挟まれたゲート酸化膜１０６下にはチャネル領域１０７が形成される。一端にゲート電極の一部が載っているフィールド酸化膜１０４の他端のＮ型ウェル領域の基板表面にはＮ型高濃度ドレイン領域１１０が基板表面から０．４μｍの深さで設けられ、フィールド酸化膜１０４の下にはＮ型中濃度拡散領域１０５が形成される。ここで、Ｎ型中濃度拡散領域１０５の不純物濃度は４〜１０ｅ１６／ｃｍ３で、フィールド酸化膜底部から０．５μｍの深さに設けられる。また、Ｎ型ウェル領域１０２にはＮ型中濃度拡散領域１０５よりも拡散深さの深いＮ型低濃度拡散領域１０３が設けられている。このＮ型低濃度拡散領域１０３はＮ型ウェル領域からＰ型ウェル領域１０１の一部まで及ぶが、その端部はゲート電極１０８と重畳しないように拡散形成されている。
その結果、横方向では、チャネル領域１０７からＮ型高濃度ドレイン領域１１０に向かってｅ→ｄ→ｃの順に次第に不純物濃度が高くなり、縦方向では、Ｎ型ウェル領域１０２からＮ型高濃度ドレイン領域に向かってａ→ｂ→ｃの順に次第に不純物濃度が高くなる電界緩和領域が形成されることになる。さらに、領域ｆには最も不純物濃度の低いＮ型拡散領域が電界緩和領域として設けられている。ファーストブレークダウン電圧やセカンドブレークダウン電圧はこれら６つの不純物濃度が異なる電界緩和領域であるＮ型拡散領域の配置によって変化することになる。
図２は、Ｎ型低濃度拡散領域１０３とＮ型ウェル領域１０２の間の距離及びＮ型低濃度拡散領域１０３とＮ型高濃度拡散領域であるＮ型高濃度ドレイン領域１１０およびＮ型高濃度ソース領域１０９との間の距離を固定したまま、チャネル領域１０７とＮ型低濃度拡散領域１０３の間の距離Ｘ１を変化させた場合の保護素子の特性変化を示した図である。ファーストブレークダウン電圧及びセカンドブレークダウン電圧の二つの特性が変化する。すなわち、距離Ｘ１が大きくなると、ファーストブレークダウン電圧およびセカンドブレークダウン電圧が高くなる傾向を示す。
図３はＮ型低濃度拡散領域１０３とＮ型高濃度拡散領であるＮ型高濃度ドレイン領域１１０およびＮ型高濃度ソース領域１０９との間の距離及びチャネル領域１０７とＮ型低濃度拡散領域１０３の間の距離を固定したまま、Ｎ型低濃度拡散領域１０３とＮ型ウェル領域１０２の間の距離Ｘ２を変化させた場合の保護素子の特性変化を示した図である。ファーストブレークダウン電圧及びセカンドブレークダウン電圧の二つの特性が変化する。すなわち、距離Ｘ２が大きくなると、ファーストブレークダウン電圧が高く、セカンドブレークダウン電圧が低くなる傾向を示す。
図４はチャネル領域１０７とＮ型低濃度拡散領域１０３の間の距離およびＮ型低濃度拡散領域１０３とＮ型ウェル領域１０２の間の距離を固定したまま、Ｎ型低濃度拡散領域１０３とＮ型高濃度ドレイン領域１１０の間の距離Ｘ３を変化させた場合の保護素子の特性変化を示した図である。ファーストブレークダウン電圧は固定されたままセカンドブレークダウン電圧のみが変化する。すなわち、距離Ｘ３が大きくなると、セカンドブレークダウン電圧が高くなるが、ファーストブレークダウンはほぼ一定である。
所望のファーストブレークダウン電圧及びセカンドブレークダウン電圧のＮチャネル型ＭＯＳトランジスタの静電気保護素子を得る場合、たとえば、図２に示すようにチャネル領域とＮ型低濃度拡散領域間の距離Ｘ１のみを変更する、または、図３に示すようにＮ型低濃度拡散領域とＮ型ウェル領域間の距離Ｘ２のみを変更することでファーストブレークダウン電圧及びセカンドブレークダウン電圧を変え、所望のファーストブレークダウン電圧に調整し、次に、図４に示すようにＮ型低濃度拡散領域とＮ型高濃度拡散領域間の距離Ｘ３のみを変更することでファーストブレークダウン電圧を保ったまま所望のセカンドブレークダウン電圧に調整することで所望のファーストブレークダウン電圧とセカンドブレークダウン電圧を有するＮチャネル型ＭＯＳトランジスタの静電気保護素子を得ることができる。
以上のように、静電気保護素子として用いられるＮチャネル型ＭＯＳトランジスタを用いる半導体装置においては、内部素子のファーストブレークダウン電圧以下のファーストブレークダウン電圧及びセカンドブレークダウン電圧を備えた静電気保護素子構造が要求されるが、上記手法を用いれば、容易に所望のブレークダウン電圧を有するＮチャネル型ＭＯＳトランジスタの静電気保護素子を得ることが可能となる。
次に、本発明の半導体装置の静電気保護素子の製造方法について図１を用いて簡単に説明する。
まず、半導体基板１００も表面にＰ型ウェル領域１０１およびＮ型ウェル領域１０２を５μｍ程度の深さに形成する。次いで、第２のＮ型ウェル領域であるＮ型低濃度拡散領域１０３をＮ型ウェル領域よりも浅い１〜２μｍ程度の深さになるように形成する。このＮ型低濃度拡散領域１０３はＮ型ウェル領域１０２だけでなくＰ型ウェル領域１０１の一部にもかけて形成され、図の領域ｂ、ｃ、ｄ、ｆに示すＮ型拡散領域全域にＮ型低濃度拡散領域１０３を形成することになる。
フィールド酸化膜１０４形成領域下にＮ型不純物であるリン（Ｐ）をイオン注入した後に酸化拡散してフィールド酸化膜１０４とＮ型中濃度拡散領域１０５を同時に形成する。形成されたＮ型中濃度拡散領域１０５は単体で５ｅ１６／ｃｍ３程度の濃度であるが、図の領域ｅではＰウェル領域のためにＮ型不純物濃度は減じられ、領域ｄではＮ型低濃度拡散領域のためにＮ型不純物濃度は単体濃度よりも高くなり、領域ｃでのＮ型不純物濃度はさらに高くなる。
次いで、フィールド酸化膜の無い領域にチャネル領域のための不純部イオン注入し、その後、チャネル領域上の半導体基板表面にゲート酸化膜１０６を形成し、さらにその上にゲート電極１０８を形成する。そして、ゲート電極１０８およびフィールド酸化膜１０４をマスクとして高濃度のＮ型不純物をイオン注入してＮ型高濃度ソース領域１０９およびＮ型高濃度ドレイン領域１１０を形成する。図示していないが、さらに、層間絶縁膜形成工程、コンタクトビア形成工程、配線工程、保護膜形成工程などを経ることで本発明の半導体装置を形成することができる。
ここで、図２に示すようにチャネル領域とＮ型低濃度拡散領域間の距離Ｘ１のみを変更する、または、図３に示すようにＮ型低濃度拡散領域とＮ型ウェル領域間の距離Ｘ２のみを変更することでファーストブレークダウン電圧及びセカンドブレークダウン電圧を変え、所望のファーストブレークダウン電圧に調整し、次に、図４に示すようにＮ型低濃度拡散領域とＮ型高濃度拡散領域間の距離Ｘ３のみを変更することでファーストブレークダウン電圧を保ったまま所望のセカンドブレークダウン電圧に調整することで所望のファーストブレークダウン電圧とセカンドブレークダウン電圧を有するＮチャネル型ＭＯＳトランジスタの静電気保護素子を有する半導体装置を製造することができる。
１００ 半導体基板
１０１ Ｐ型ウェル領域
１０２ Ｎ型ウェル領域
１０３ Ｎ型低濃度拡散領域（第２のＮ型ウェル領域）
１０４ フィールド酸化膜
１０５ Ｎ型中濃度拡散領域
１０６ ゲート酸化膜
１０７ チャネル領域
１０８ ゲート電極
１０９ Ｎ型高濃度ソース領域
１１０ Ｎ型高濃度ドレイン領域
Ｘ１ チャネル領域〜Ｎ型低濃度拡散領域間距離
Ｘ２ Ｎ型低濃度拡散領域〜Ｎ型ウェル領域間距離
Ｘ３ Ｎ型低濃度拡散領域〜Ｎ型高濃度ドレイン領域間距離
ａ、ｂ、ｃ、ｄ、ｅ、ｆ Ｎ型拡散領域（電界緩和領域）

Claims (7)

  1. 半導体基板上に設けられたフィールド酸化膜およびゲート酸化膜と、
    前記ゲート酸化膜を介して設けられ、一部が前記フィールド酸化膜上に延在するゲート電極と、
    前記ゲート電極の一端に設けられたＮ型高濃度ソース領域と、
    前記Ｎ型高濃度ソース領域と前記フィールド酸化膜の一方の端部に挟まれ、前記ゲート酸化膜下に設けられたチャネル領域と、
    前記フィールド酸化膜の一方の端部の反対側となる他方の端部に設けられたＮ型高濃度ドレイン領域と、
    前記フィールド酸化膜の下方であって、前記Ｎ型高濃度ドレイン領域の周囲に設けられた複数の電界緩和領域と、
    からなるＮチャネル型ＭＯＳトランジスタを有する半導体装置であって、
    前記複数の電界緩和領域は、前記Ｎ型高濃度ドレイン領域から下方に向かって減少する３種類の異なる不純物濃度を有する縦方向の電界緩和領域と、前記Ｎ型高濃度ドレイン領域から前記チャネル領域に向かって減少する３種類の異なる不純物濃度を有する横方向の電界緩和領域と、前記縦方向の電界緩和領域と前記横方向の電界緩和領域とに接する最も不純物濃度の低い電界緩和領域を有していることを特徴とする半導体装置。
  2. 前記複数の電界緩和領域は、Ｎ型中濃度拡散領域とＰ型ウェル領域および第１のＮ型ウェル領域と第２のＮ型ウェル領域が重畳した領域であることを特徴とする請求項１記載の半導体装置。
  3. 前記第１のＮ型ウェル領域の半導体基板内深さは前記第２のＮ型ウェル領域よりも深く、前記第２のＮ型ウェル領域の半導体基板内深さは前記Ｎ型中濃度拡散領域よりも深いことを特徴とする請求項２記載の半導体装置。
  4. 前記第２のＮ型ウェル領域が前記フィールド酸化膜上に延在した前記ゲート電極と重畳しないことを特徴とする請求項２または請求項３記載の半導体装置。
  5. 半導体基板上に設けられたフィールド酸化膜およびゲート酸化膜と、
    前記ゲート酸化膜を介して設けられ、一部が前記フィールド酸化膜上に延在するゲート電極と、
    前記ゲート電極の一端に設けられたＮ型高濃度ソース領域と、
    前記Ｎ型高濃度ソース領域と前記フィールド酸化膜の一方の端部に挟まれ、前記ゲート酸化膜下に設けられたチャネル領域と、
    前記フィールド酸化膜の一方の端部の反対側となる他方の端部に設けられたＮ型高濃度ドレイン領域と、
    前記フィールド酸化膜の下方であって、前記Ｎ型高濃度ドレイン領域の周囲に設けられた複数の電界緩和領域と、
    からなるＮチャネル型ＭＯＳトランジスタを有する半導体装置の製造方法であって、
    前記半導体基板の表面にＰ型ウェル領域および第１のＮ型ウェル領域を形成する工程と、
    第２のＮ型ウェル領域を前記第１のＮ型ウェル領域よりも浅く形成する工程と、
    前記フィールド酸化膜の形成領域下にＮ型不純物をイオン注入し、酸化拡散して前記フィールド酸化膜とＮ型中濃度拡散領域を同時に形成する工程と、
    前記フィールド酸化膜の無い領域に前記チャネル領域を形成する工程と、
    前記チャネル領域上に前記ゲート酸化膜を介して前記ゲート電極を形成する工程と、
    前記ゲート電極および前記フィールド酸化膜をマスクとして高濃度のＮ型不純物をイオン注入して前記Ｎ型高濃度ソース領域および前記Ｎ型高濃度ドレイン領域を形成する工程と、
    層間絶縁膜形成工程と、
    コンタクトビア形成工程と、
    配線工程と、
    保護膜形成工程と、
    からなることを特徴とする半導体装置の製造方法。
  6. 前記チャネル領域と前記第２のＮ型ウェル領域の間の距離を調整する工程と、前記第２のＮ型ウェル領域と前記Ｎ型高濃度ドレイン領域の間の距離を調整する工程と、をさらに有することを特徴とする請求項５記載の半導体装置の製造方法。
  7. 前記第２のＮ型ウェル領域と前記第１のＮ型ウェル領域の間の距離を調整する工程と、前記第２のＮ型ウェル領域と前記Ｎ型高濃度ドレイン領域の間の距離を調整する工程と、をさらに有することを特徴とする請求項５記載の半導体装置の製造方法。
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