CN107275401A - 半导体装置和半导体装置的制造方法 - Google Patents

半导体装置和半导体装置的制造方法 Download PDF

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CN107275401A
CN107275401A CN201710195980.9A CN201710195980A CN107275401A CN 107275401 A CN107275401 A CN 107275401A CN 201710195980 A CN201710195980 A CN 201710195980A CN 107275401 A CN107275401 A CN 107275401A
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semiconductor device
oxide film
high concentration
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CN107275401B (zh
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森田健士
津村和宏
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Seiko Instruments Inc
Ablic Inc
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Seiko Instruments Inc
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Abstract

本发明提供半导体装置和半导体装置的制造方法，所述半导体装置能够容易地调整半导体装置的静电保护元件的耐压。在将N沟道型MOS晶体管作为静电保护元件的半导体装置中，N沟道型MOS晶体管构成为具有：纵向的电场缓和区域，其具有从N型高浓度漏区域朝向下方减小的3种不同的杂质浓度；横向的电场缓和区域，其具有从N型高浓度漏区域朝向沟道区域减小的3种不同的杂质浓度；以及杂质浓度最低的电场缓和区域，其与纵向的电场缓和区域和横向的电场缓和区域相接。

Description

半导体装置和半导体装置的制造方法
技术领域
本发明涉及将N沟道型MOS晶体管用作静电保护元件的半导体装置。
背景技术
在将MOS型晶体管用作静电保护元件的半导体装置中，使N沟道型MOS晶体管的漏极与外部端子相连且使栅极电位和源极电位接地而以截止状态来使用的所谓的截止晶体管被广泛利用。
在对执行高电压动作的元件进行保护的情况下，利用如下的高耐压结构：在该N沟道型MOS晶体管的漏极的周围，在沟道区域与漏区域之间具备场氧化膜。另外，为了提高耐压和减小导通电阻，利用了在N型高浓度漏区域周边具备杂质浓度不同的N型低浓度扩散区域的高耐压结构(例如，参照专利文献1)。
专利文献1：日本特开2007-266473号公报
在被用作静电保护元件的N沟道型MOS晶体管中，理想的是，要求具备如下电气特性的结构：具有半导体装置的额定电压以上的第一击穿电压和第二击穿电压，并且分别成为比内部元件的第一击穿电压和第二击穿电压低的第一击穿电压和第二击穿电压。一般来说，如果提高耐压，则导通电阻升高，因此，在为了降低导通电阻而提高了低浓度扩散区域的浓度的情况下，存在下述可能：第一击穿电压降低而低于半导体装置的额定电压或工作电压，从而无法满足所希望的特性。另一方面，在忽视了导通电阻、为了提高耐压而设置为低浓度的情况下，存在下述可能：第二击穿电压升高而无法保护内部元件。
另外，第一击穿电压和第二击穿电压在MOS晶体管的IDS-VDS特性中被定义。在图5中示出了示意性的IDS-VDS特性。第一击穿电压是在保持栅极电压为0V并提高了漏-源之间的电压VDS时漏电流IDS开始上升的电压。第二击穿电压是在进一步提高漏-源之间的电压VDS的情况下漏-源之间的电阻急剧变小而开始流动大电流的电压。
发明内容
本发明是鉴于上述课题而完成的，提供一种能够在不进行浓度变更的情况下通过扩散间的距离容易地调整半导体装置的静电保护元件的耐压的结构。
为了解决上述课题，在本发明中采用了以下的手段。
一种半导体装置，其具有N沟道型MOS晶体管，该N沟道型MOS晶体管包含下述部分：场氧化膜和栅氧化膜，它们被设置于半导体衬底上；栅极，其被设置于所述栅氧化膜的上方，该栅极的一端被配置成延伸至所述场氧化膜上；N型高浓度源区域，其被设置于所述栅极的另一端；沟道区域，其被所述N型高浓度源区域和所述场氧化膜的一个端部夹着，且设置于所述栅氧化膜的下方；N型高浓度漏区域，其被设置于所述场氧化膜的处于所述一个端部的相反侧的另一个端部；以及电场缓和区域，它们处于所述场氧化膜的下方，且被设置于所述N型高浓度漏区域的周围，其特征在于，设在所述场氧化膜的下方的N型中浓度扩散区域由从所述N型高浓度漏区域至所述沟道区域具有多个杂质浓度的区域构成。
另外，一种半导体装置的制造方法，所述半导体装置具有N沟道型MOS晶体管，该N沟道型MOS晶体管包含下述部分：场氧化膜和栅氧化膜，它们被设置于半导体衬底上；栅极，其被设置于所述栅氧化膜的上方，该栅极的一端被配置成延伸至所述场氧化膜上；N型高浓度源区域，其被设置于所述栅极的另一端；沟道区域，其被所述N型高浓度源区域和所述场氧化膜的一个端部夹着，且设置于所述栅氧化膜的下方；N型高浓度漏区域，其被设置于所述场氧化膜的处于所述一个端部的相反侧的另一个端部；以及电场缓和区域，它们处于所述场氧化膜的下方，且被设置于所述N型高浓度漏区域的周围，其特征在于，所述半导体装置的制造方法包含下述工序：在半导体衬底的表面形成P型阱区域和第1N型阱区域的工序；以比所述第1N型阱区域浅的方式形成第2N型阱区域的工序；在场氧化膜的形成区域的下方离子注入N型杂质，并使该N型杂质氧化扩散而同时形成所述场氧化膜和N型中浓度扩散区域的工序；在不存在所述场氧化膜的区域形成沟道区域的工序；在所述沟道区域的表面形成栅氧化膜的工序；在所述栅氧化膜的上方形成栅极的工序；将所述栅极和所述场氧化膜作为掩膜，离子注入高浓度的N型杂质而形成N型高浓度源区域和N型高浓度漏区域的工序；层间绝缘膜形成工序；接触孔形成工序；配线工序；以及保护膜形成工序。
通过采用上述手段，容易地将静电保护元件的电压特性调整为所希望的值。
根据本发明，影响第一击穿电压和第二击穿电压的结构是沟道区域与N型低浓度扩散区域(第2N型阱区域)之间的距离、以及N型低浓度扩散区域(第2N型阱区域)与第1N型阱区域之间的距离，影响第二击穿电压的结构是N型低浓度扩散区域(第2N型阱区域)与N型高浓度扩散区域(N型高浓度漏区域)之间的距离，在保持该结构中的其它两个距离的状态下改变该结构中的某一个的距离，由此能够调整出所希望的第一击穿电压和第二击穿电压。
附图说明
图1是作为本发明的实施例的半导体装置的静电保护元件的示意性的剖视图。
图2是作为本发明的实施例的半导体装置的静电保护元件的特性图。
图3是作为本发明的实施例的半导体装置的静电保护元件的特性图。
图4是作为本发明的实施例的半导体装置的静电保护元件的特性图。
图5是N沟道型MOS晶体管的IDS-VDS特性图。
标号说明
100：半导体衬底；
101：P型阱区域；
102：N型阱区域；
103：N型低浓度扩散区域(第2N型阱区域)；
104：场氧化膜；
105：N型中浓度扩散区域；
106：栅氧化膜；
107：沟道区域；
108：栅极；
109：N型高浓度源区域；
110：N型高浓度漏区域；
X1：沟道区域与N型低浓度扩散区域之间的距离；
X2：N型低浓度扩散区域与N型阱区域之间的距离；
X3：N型低浓度扩散区域与N型高浓度漏区域之间的距离；
a、b、c、d、e、f：N型扩散区域(电场缓和区域)；
具体实施方式
以下，利用附图，对作为本发明的半导体装置的实施方式的静电保护元件进行说明。
图1示出了利用作为本发明的实施例的半导体装置的N沟道型MOS晶体管的、静电保护元件的示意性的剖视图。
N沟道型MOS晶体管是被用于高耐压的LDMOS结构，在导电类型为P型或N型的半导体衬底100中设有P型阱区域101和N型阱区域102。栅氧化膜106形成于P型阱区域101的衬底表面的一部分，在栅氧化膜106的上方设有栅极108，栅极108的一部分延伸到场氧化膜104上，该场氧化膜104通过LOCOS(Local Oxidation of Silicon：硅的局部氧化)法形成于衬底上。在栅极108的一个端部设有N型高浓度源区域109，在被该N型高浓度源区域109与场氧化膜104夹着的栅氧化膜106的下方形成有沟道区域107。栅极108的一部分被载置于场氧化膜104的一端，在位于场氧化膜104的另一端的下方的N型阱区域102的衬底表面，以距衬底表面0.4μm的深度设置有N型高浓度漏区域110。在场氧化膜104的下方形成有N型中浓度扩散区域105。
N型中浓度扩散区域105的杂质浓度为4～10e16/cm3，且设置为距场氧化膜104的底部0.5μm的深度。另外，在N型阱区域102中设置有扩散深度比N型中浓度扩散区域105深的N型低浓度扩散区域103。该N型低浓度扩散区域103从N型阱区域102扩展至P型阱区域101的一部分，但其端部以不与栅极108重叠的方式扩散形成。
在此，对于由位于N型高浓度漏区域110的周围的N型中浓度扩散区域105、N型低浓度扩散区域103、N型阱区域102以及P型阱区域101单独地形成的、或者通过重合而形成的成为电场缓和区域的区域a至f，如下这样进行定义。并且，衬底是共用的，因此不进行说明。
设仅由N型阱区域102构成的区域为a，设N型阱区域102和N型低浓度扩散区域103相重叠的区域为b，设N型阱区域102、N型低浓度扩散区域103以及N型中浓度扩散区域105相重叠的区域为c，设N型中浓度扩散区域105、N型低浓度扩散区域103以及P型阱区域101相重叠的区域为d，设N型中浓度扩散区域105和P型阱区域101相重叠的区域为e，设N型低浓度扩散区域103和P型阱区域101相重叠的区域为f。
其结果是，形成了如下的电场缓和区域：在横向上，从沟道区域107朝向N型高浓度漏区域110，杂质浓度按照区域e→d→c的顺序逐渐变高，在纵向上，从N型阱区域102朝向N型高浓度漏区域110，杂质浓度按照区域a→b→c的顺序逐渐变高。而且，区域f是由杂质浓度最低的N型扩散区域构成的电场缓和区域。N沟道型MOS晶体管的第一击穿电压或第二击穿电压根据这6个杂质浓度不同的电场缓和区域即N型扩散区域的配置而变化。
图2是示出下述情况下的静电保护元件的特性变化的图：使N型低浓度扩散区域103与N型阱区域102之间的距离、以及N型低浓度扩散区域103与作为N型高浓度扩散区域的N型高浓度漏区域110及N型高浓度源区域109之间的距离固定，保持该状态，使沟道区域107与N型低浓度扩散区域103之间的距离X1变化。第一击穿电压和第二击穿电压这两者的特性发生变化。即，表现出如下趋势：如果距离X1变大，则第一击穿电压和第二击穿电压升高。
图3是示出下述情况下的静电保护元件的特性变化的图：使N型低浓度扩散区域103与作为N型高浓度扩散区域的N型高浓度漏区域110及N型高浓度源区域109之间的距离、以及沟道区域107与N型低浓度扩散区域103之间的距离固定，保持该状态，使N型低浓度扩散区域103与N型阱区域102之间的距离X2变化。第一击穿电压和第二击穿电压这两者的特性发生变化。即，表现出如下趋势：如果距离X2变大，则第一击穿电压升高、且第二击穿电压降低。
图4是示出下述情况下的静电保护元件的特性变化的图：使沟道区域107与N型低浓度扩散区域103之间的距离、以及N型低浓度扩散区域103与N型阱区域102之间的距离固定，保持该状态，使N型低浓度扩散区域103与N型高浓度漏区域110之间的距离X3变化。第一击穿电压保持固定，只有第二击穿电压发生变化。即，如果距离X3变大，则第二击穿电压升高，但第一击穿电压大致固定。
在要得到所希望的第一击穿电压和第二击穿电压的N沟道型MOS晶体管的静电保护元件的情况下，例如如图2所示那样仅变更沟道区域与N型低浓度扩散区域之间的距离X1、或者如图3所示那样仅变更N型低浓度扩散区域与N型阱区域之间的距离X2，由此改变第一击穿电压和第二击穿电压，调整出所希望的第一击穿电压，接下来，如图4所示那样仅变更N型低浓度扩散区域与N型高浓度扩散区域之间的距离X3，由此在保持第一击穿电压的状态下调整出所希望的第二击穿电压，由此，能够获得具有所希望的第一击穿电压和第二击穿电压的N沟道型MOS晶体管的静电保护元件。
如上所述，在使用了被用作静电保护元件的N沟道型MOS晶体管的半导体装置中，要求具备分别比内部元件的第一击穿电压和第二击穿电压低的第一击穿电压和第二击穿电压的静电保护元件，但是，如果采用上述方法，则能够容易地获得具有所希望的击穿电压的N沟道型MOS晶体管的静电保护元件。
接下来，利用图1对本发明的半导体装置的静电保护元件的制造方法简单地进行说明。
首先，在半导体衬底100的表面形成5μm左右的深度的P型阱区域101和N型阱区域102。接下来，使作为第2N型阱区域的N型低浓度扩散区域103形成为比N型阱区域102浅的1～2μm左右的深度。该N型低浓度扩散区域103不仅形成至N型阱区域102，而且还形成至P型阱区域101的一部分，从而构成成为图中的区域b、c、d、f的电场缓和区域。
在场氧化膜104形成区域的下方，离子注入作为N型杂质的磷(P)后，使其氧化扩散，同时形成场氧化膜104和N型中浓度扩散区域105。所形成的N型中浓度扩散区域105的单体浓度是5e16/cm3左右的浓度，但是，在图的区域e中，由于P型阱区域101，使得N型杂质浓度降低，在区域d中，由于N型低浓度扩散区域103，使得N型杂质浓度比单体浓度高，区域c中的N型杂质浓度变得更高。
接下来，在不存在场氧化膜104的区域中离子注入用于沟道区域107的杂质部，然后，在沟道区域107上方的半导体衬底表面形成栅氧化膜106，进而在栅氧化膜106上方形成栅极108。然后，将栅极108和场氧化膜104作为掩膜，离子注入高浓度的N型杂质，形成N型高浓度源区域109和N型高浓度漏区域110。虽然未图示，但通过进一步经过层间绝缘膜形成工序、接触孔形成工序、配线工序、保护膜形成工序等，能够形成本发明的半导体装置。
在此，如图2所示那样仅变更沟道区域与N型低浓度扩散区域之间的距离X1、或者如图3所示那样仅变更N型低浓度扩散区域与N型阱区域之间的距离X2，由此改变第一击穿电压和第二击穿电压，调整出所希望的第一击穿电压，接下来，如图4所示那样仅变更N型低浓度扩散区域与N型高浓度扩散区域之间的距离X3，由此在保持第一击穿电压的状态下调整出所希望的第二击穿电压，由此，能够制造出如下的半导体装置：该半导体装置具有存在所希望的第一击穿电压和第二击穿电压的N沟道型MOS晶体管的静电保护元件。

Claims (7)

1.一种半导体装置，其具有N沟道型MOS晶体管，该N沟道型MOS晶体管包含下述部分：
场氧化膜和栅氧化膜，它们被设置于半导体衬底上；
栅极，其被设置于所述栅氧化膜的上方，该栅极的一端被配置成延伸至所述场氧化膜上；
N型高浓度源区域，其被设置于所述栅极的另一端；
沟道区域，其被所述N型高浓度源区域和所述场氧化膜的一个端部夹着，且设置于所述栅氧化膜的下方；
N型高浓度漏区域，其被设置于所述场氧化膜的处于所述一个端部的相反侧的另一个端部；以及
多个电场缓和区域，它们处于所述场氧化膜的下方，且被设置于所述N型高浓度漏区域的周围，
其特征在于，
所述多个电场缓和区域具有：
纵向的电场缓和区域，其具有从所述N型高浓度漏区域朝向下方减小的3种不同的杂质浓度；
横向的电场缓和区域，其具有从所述N型高浓度漏区域朝向所述沟道区域减小的3种不同的杂质浓度；以及
杂质浓度最低的电场缓和区域，其与所述纵向的电场缓和区域和所述横向的电场缓和区域相接。
2.根据权利要求1所述的半导体装置，其特征在于，
所述多个电场缓和区域是N型中浓度扩散区域与P型阱区域相重叠的区域、和第1N型阱区域与第2N型阱区域相重叠的区域。
3.根据权利要求2所述的半导体装置，其特征在于，
所述第1N型阱区域在半导体衬底内的深度比所述第2N型阱区域在半导体衬底内的深度深，所述第2N型阱区域在半导体衬底内的深度比所述N型中浓度扩散区域在半导体衬底内的深度深。
4.根据权利要求2或权利要求3所述的半导体装置，其特征在于，
所述第2N型阱区域不与延伸到所述场氧化膜上的所述栅极重叠。
5.一种半导体装置的制造方法，所述半导体装置具有N沟道型MOS晶体管，该N沟道型MOS晶体管包含下述部分：
场氧化膜和栅氧化膜，它们被设置于半导体衬底上；
栅极，其被设置于所述栅氧化膜的上方，该栅极的一端被配置成延伸至所述场氧化膜上；
N型高浓度源区域，其被设置于所述栅极的另一端；
沟道区域，其被所述N型高浓度源区域和所述场氧化膜的一个端部夹着，且设置于所述栅氧化膜的下方；
N型高浓度漏区域，其被设置于所述场氧化膜的处于所述一个端部的相反侧的另一个端部；以及
多个电场缓和区域，它们处于所述场氧化膜的下方，且被设置于所述N型高浓度漏区域的周围，
其特征在于，
所述半导体装置的制造方法包含下述工序：
在半导体衬底的表面形成P型阱区域和第1N型阱区域的工序；
以比所述第1N型阱区域浅的方式形成第2N型阱区域的工序；
在场氧化膜的形成区域的下方离子注入N型杂质，并使该N型杂质氧化扩散而同时形成所述场氧化膜和N型中浓度扩散区域的工序；
在不存在所述场氧化膜的区域形成沟道区域的工序；
在所述沟道区域的表面形成栅氧化膜的工序；
在所述栅氧化膜的上方形成栅极的工序；
将所述栅极和所述场氧化膜作为掩膜，离子注入高浓度的N型杂质而形成N型高浓度源区域和N型高浓度漏区域的工序；
层间绝缘膜形成工序；
接触孔形成工序；
配线工序；以及
保护膜形成工序。
6.根据权利要求5所述的半导体装置的制造方法，其特征在于，
所述半导体装置的制造方法还具有：
调整所述沟道区域与所述第2N型阱区域之间的距离的工序；和
调整所述第2N型阱区域与所述N型高浓度漏区域之间的距离的工序。
7.根据权利要求5所述的半导体装置的制造方法，其特征在于，
所述半导体装置的制造方法还具有：
调整所述第2N型阱区域与所述第1N型阱区域之间的距离的工序；和
调整所述第2N型阱区域与所述N型高浓度漏区域之间的距离的工序。
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