CN112490288A - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN112490288A
CN112490288A CN201911356238.7A CN201911356238A CN112490288A CN 112490288 A CN112490288 A CN 112490288A CN 201911356238 A CN201911356238 A CN 201911356238A CN 112490288 A CN112490288 A CN 112490288A
Authority
CN
China
Prior art keywords
insulating film
semiconductor layer
layer
semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201911356238.7A
Other languages
English (en)
Inventor
岩津泰德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Devices and Storage Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Devices and Storage Corp filed Critical Toshiba Corp
Publication of CN112490288A publication Critical patent/CN112490288A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/086—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

实施方式提供能够使得截止状态时的高耐压和导通状态时的低电阻两立的半导体装置。实施方式的半导体装置具备：第1半导体层；第1导电型的第2半导体层，设置于第1半导体层的一部分上；第2导电型的第3半导体层，设置于第2半导体层的一部分上，与第1半导体层分离；第2导电型的第4半导体层，设置于第1半导体层的其他的一部分上；第1绝缘膜，设置于第3半导体层与第4半导体层之间的部分上及第4半导体层中的第2半导体层侧的部分上；第2绝缘膜，设置于第4半导体层上，与第1绝缘膜接触，比第1绝缘膜厚；第3绝缘膜，设置于第2绝缘膜上；以及电极，设置于第1绝缘膜上、第2绝缘膜上及第3绝缘膜上。

Description

半导体装置
【关联申请】
本申请享受以日本专利申请2019－166211号(申请日：2019年9月12日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
实施方式涉及半导体装置。
背景技术
作为电力控制用的半导体装置，使用LDMOS(Laterally Double-DiffusedMOSFET：横型双扩散MOSFET)。在LDMOS中，要求截止状态时的高耐压和导通状态时的低电阻的两立。
发明内容
实施方式提供能够使得截止状态时的高耐压和导通状态时的低电阻两立的半导体装置。
实施方式的半导体装置具备：第1半导体层；第1导电型的第2半导体层，设置于上述第1半导体层的一部分上；第2导电型的第3半导体层，设置于上述第2半导体层的一部分上，与上述第1半导体层分离；上述第2导电型的第4半导体层，设置于上述第1半导体层的其他的一部分上；第1绝缘膜，设置于上述第3半导体层与上述第4半导体层之间的部分上及上述第4半导体层中的上述第2半导体层侧的部分上；第2绝缘膜，设置于上述第4半导体层上，与上述第1绝缘膜接触，比上述第1绝缘膜厚；第3绝缘膜，设置于上述第2绝缘膜上；以及电极，设置于上述第1绝缘膜上、上述第2绝缘膜上及上述第3绝缘膜上。
附图说明
图1是表示实施方式的半导体装置的剖视图。
图2中(a)～(c)是表示实施方式的半导体装置的第1场绝缘膜及第2场绝缘膜的形成方法的剖视图。
图3中(a)及(b)是表示实施方式的半导体装置的第1场绝缘膜及第2场绝缘膜的形成方法的剖视图。
图4中(a)及(b)是表示半导体装置内的工艺仿真结果的图。
图5是横轴取X方向上的位置、纵轴取电场强度，而表示电场强度分布的器件仿真结果的曲线图。
图6是横轴取截止状态时的源极漏极间耐压、纵轴取导通状态时的源极漏极间电阻，而表示耐压与电阻的平衡的曲线图。
具体实施方式
图1是表示本发明的实施方式的半导体装置的剖视图。
如图1所示，本实施方式的半导体装置1是LDMOS(Laterally Double-DiffusedMOSFET：横型双扩散MOSFET)。在半导体装置1中，设置有半导体部分10、设置于半导体部分10上的绝缘体部分20及隔着绝缘体部分20而与半导体部分10分离的栅极电极30。
在半导体部分10，设置有导电型为例如p－形的阱层11(第1半导体层)。在阱层11的一部分上，设置有导电型为例如p型的基体层12(第2半导体层)。另外，导电型为“p－形”表示与“p型”相比成为受主的杂质的浓度较低。另外，阱层11的导电型也可以是n－型。即，阱层11的导电型和基体层12的导电型可以相同，也可以不同。
在基体层12的一部分上，设置有导电型为例如n+型的源极层13，以与源极层13接触的方式设置有导电型为n型的源极扩展层14。另外，导电型为“n+型”表示与“n型”相比成为施主的杂质的浓度较高。通过源极层13及源极扩展层14，构成第3半导体层。源极层13及源极扩展层14与阱层11分离，在源极层13与阱层11之间及源极扩展层14与阱层11之间，配置有基体层12。
另一方面，在阱层11的其他的一部分上设置有导电型为例如n型的漂移层15。在漂移层15的一部分上设置有导电型为例如n+型的漏极层16。通过漂移层15及漏极层16构成第4半导体层。漏极层16与阱层11分离，在漏极层16与阱层11之间配置有漂移层15。漂移层15与基体层12分离，在漂移层15与基体层12之间配置有阱层11的一部分。
通过阱层11及基体层12、源极层13及源极扩展层14以及漂移层15及漏极层16，构成半导体部分10。半导体部分10包括例如硅(Si)，通过对例如单晶硅导入杂质而形成。
在绝缘体部分20设置有栅极绝缘膜21(第1绝缘膜)、第1场绝缘膜22(第2绝缘膜)、第2场绝缘膜23(第3绝缘膜)、蚀刻阻挡膜24(第4绝缘膜)及侧壁25。
栅极绝缘膜21配置于半导体部分10中的源极扩展层14与漂移层15之间的部分上及漂移层15中的基体层12侧的部分上。
第1场绝缘膜22设置于漂移层15的一部分上。第1场绝缘膜22与栅极绝缘膜21接触。第1场绝缘膜22比栅极绝缘膜21厚。第1场绝缘膜22可以是LOCOS(Local Oxidation ofSilicon)，也可以是STI(Shallow Trench Isolation：元件分离绝缘膜)。
图1表示第1场绝缘膜22为LOCOS的情况。在此情况下，第1场绝缘膜22的端部的形状是鸟嘴状，越朝向前端越薄。例如，第1场绝缘膜22具有随着靠近栅极绝缘膜21侧的端部22a而变薄的形状。第1场绝缘膜22的下部与漂移层15的上表面中与第1场绝缘膜22不接触的区域相比位于靠下方，配置于源极层13与漏极层16之间。
第2场绝缘膜23配置于第1场绝缘膜22上。在从栅极绝缘膜21朝向第1场绝缘膜22的X方向上，第2场绝缘膜23的长度比第1场绝缘膜22的长度短。另外，第2场绝缘膜23与第1场绝缘膜22中的栅极绝缘膜21侧的端部22a分离。
在X方向上，第2场绝缘膜23的中央位置23cx与第1场绝缘膜22的中央位置22cx相比靠近漏极层16侧。即，若将在X方向上、第2场绝缘膜23的中央位置23cx与第1场绝缘膜22中的栅极绝缘膜21的相反侧的端部22b之间的距离设为距离L1，并将第1场绝缘膜22的中央位置22cx与第1场绝缘膜的端部22b之间的距离设为距离L2，则距离L1与距离L2相等或比其更短。即，L1≤L2。
蚀刻阻挡膜24设置于第1场绝缘膜22与第2场绝缘膜23之间。蚀刻阻挡膜24的材料与第1场绝缘膜22的材料及第2场绝缘膜23的材料不同。例如，栅极绝缘膜21、第1场绝缘膜22及第2场绝缘膜23由硅氧化物(SiO)构成，蚀刻阻挡膜24由硅氮化物(SiN)构成。
栅极电极30设置于栅极绝缘膜21上、第1场绝缘膜22上及第2场绝缘膜23上。栅极电极30由导电性材料构成，例如，由包含杂质的多晶硅构成。
侧壁25设置于栅极电极30的侧面上。源极扩展层14设置于源极层13的侧方而且是侧壁25中的源极侧的部分的正下方区域。
接下来，对本实施方式的半导体装置的制造方法中的、第1场绝缘膜22及第2场绝缘膜23的形成方法进行说明。
图2的(a)～(c)以及图3的(a)及(b)是表示本实施方式的半导体装置的第1场绝缘膜及第2场绝缘膜的形成方法的剖视图。
首先，如图2的(a)所示那样，在半导体部分10的上表面，通过例如热氧化法形成第1场绝缘膜22。在此情况下，第1场绝缘膜22是LOCOS，其端部的形状成为鸟嘴状。在半导体部分10包含硅的情况下，第1场绝缘膜22包含硅氧化物。另外，第1场绝缘膜22可以作为STI而形成。在此情况下，在半导体部分10的上表面形成沟槽，并在沟槽内沉积硅氧化物，由此形成第1场绝缘膜22。
接下来，如图2的(b)所示那样，整面地形成由与第1场绝缘膜22不同的材料例如硅氮化物构成的蚀刻阻挡膜24。蚀刻阻挡膜24通过例如CVD(Chemical Vapor Deposition：化学气相生长)法形成。蚀刻阻挡膜24形成于半导体部分10上及第1场绝缘膜22上。
接下来，如图2的(c)所示那样，整面地形成第2场绝缘膜23。第2场绝缘膜23例如通过用CVD法沉积硅氧化物而形成。
接下来，如图3的(a)所示那样，通过例如光刻法，在第2场绝缘膜23上的一部分形成抗蚀剂图案51。接下来，将抗蚀剂图案51作为掩模，将蚀刻阻挡膜24作为阻挡层，实施例如RIE(Reactive Ion Etching：反应性离子蚀刻)等的蚀刻。由此，第2场绝缘膜23选择性地被去除，而被印刻图案。接下来，将抗蚀剂图案51去除。
接下来，如图3的(b)所示那样，对蚀刻阻挡膜24进行蚀刻。由此，将蚀刻阻挡膜24中的未被第2场绝缘膜23覆盖的部分去除。
之后，通过通常的方法，在半导体部分10内通过离子注入法等形成各半导体层。另外，形成栅极绝缘膜21、栅极电极30及侧壁25等。由此，制造出半导体装置1。
接下来，对本实施方式的效果进行说明。
在本实施方式的半导体装置1中，不仅将栅极电极30配置在栅极绝缘膜21上，还配置在第1场绝缘膜22上。由此，能够抑制半导体部分10内的电场的集中。
另外，在本实施方式中，在第1场绝缘膜22上设置第2场绝缘膜23，并将栅极电极30的漏极侧的端部配置于第2场绝缘膜23上。由此，电场特别容易集中的栅极电极30的漏极侧的端部与半导体部分10之间的距离变长，能够更有效地抑制电场的集中。其结果，设置于半导体装置1的LDMOS的源极漏极间耐压提高。
进而，在本实施方式中，通过在第1场绝缘膜22与第2场绝缘膜23之间设置蚀刻阻挡膜24，由此仅蚀刻第2场绝缘膜23，就能够加工成任意的形状。由此，能够使栅极电极30为任意的形状。
图4的(a)是表示对比较例的半导体装置101假定的工艺仿真结果的图。图4的(b)是表示对本实施方式的半导体装置1假定的工艺仿真结果的图。
图5是横轴取X方向上的位置、纵轴取电场强度、而表示电场强度分布的器件仿真结果的曲线图。
在图5所示的器件仿真中，假定了对比较例的半导体装置101和本实施方式的半导体装置1施加了相同的源极漏极间电压的情况。
如图4的(a)所示那样，在比较例的半导体装置101中，未设置有第2场绝缘膜23及蚀刻阻挡膜24。与此相对，如图4的(b)所示那样，在本实施方式的半导体装置1中，在第1场绝缘膜22上设置有第2场绝缘膜23，在第2场绝缘膜23上配置有栅极电极30的漏极侧的端部。
如图5所示，在比较例的半导体装置101中，在半导体部分10的表面上电场最强的部分是栅极电极30的漏极侧的端部的正下方部分。因此，在该部分容易发生击穿。与此相对，本实施方式的半导体装置1与半导体装置101相比较，栅极电极30的漏极侧的端部与半导体部分10之间的距离增长，因此上述部分的电场变弱。因此，半导体装置1的源极漏极间耐压比半导体装置101高。
图6是横轴取截止状态时的源极漏极间耐压、纵轴取导通状态时的源极漏极间电阻(正向电阻)、而表示耐压与电阻的平衡的曲线图。
如图6所示，设置有第2场绝缘膜23的本实施方式的实施例1～3，与未设置有第2场绝缘膜23的比较例1～3相比较，维持同等的正向电阻，并且耐压提高。
这样，根据本实施方式，能够实现能够使得截止状态时的高耐压和导通状态时的低电阻两立的半导体装置。
以上，说明了本发明的实施方式，但该实施方式是作为例子提示的，意图不是限定发明的范围。该新的实施方式，能够以其他各种各样的方式实施，在不脱离发明的主旨的范围内，能够进行各种省略、置换、变更。该实施方式及其变形，包含在发明的范围及主旨中，并且包含在权利要求书记载的发明及其等同物的范围中。

Claims (8)

1.一种半导体装置，具备：
第1半导体层；
第1导电型的第2半导体层，设置于上述第1半导体层的一部分上；
第2导电型的第3半导体层，设置于上述第2半导体层的一部分上，与上述第1半导体层分离；
上述第2导电型的第4半导体层，设置于上述第1半导体层的其他的一部分上；
第1绝缘膜，设置于上述第3半导体层与上述第4半导体层之间的部分上及上述第4半导体层中的上述第2半导体层侧的部分上；
第2绝缘膜，设置于上述第4半导体层上，与上述第1绝缘膜接触，比上述第1绝缘膜厚；
第3绝缘膜，设置于上述第2绝缘膜上；以及
电极，设置于上述第1绝缘膜上、上述第2绝缘膜上及上述第3绝缘膜上。
2.如权利要求1所述的半导体装置，
在从上述第1绝缘膜朝向上述第2绝缘膜的第1方向上，上述第3绝缘膜的长度比上述第2绝缘膜的长度短。
3.如权利要求2所述的半导体装置，
上述第3绝缘膜与上述第2绝缘膜中的上述第1绝缘膜侧的端部分离。
4.如权利要求2所述的半导体装置，
在上述第1方向上，上述第3绝缘膜的中央与上述第2绝缘膜中的上述第1绝缘膜的相反侧的端部之间的第1距离，与上述第2绝缘膜的中央与上述第2绝缘膜中的上述第1绝缘膜的相反侧的端部之间的第2距离相等或比其更短。
5.如权利要求1～4中任一项所述的半导体装置，
还具备第4绝缘膜，该第4绝缘膜设置于上述第2绝缘膜与上述第3绝缘膜之间，由与上述第2绝缘膜的材料及上述第3绝缘膜的材料不同的材料构成。
6.如权利要求5所述的半导体装置，
上述第1绝缘膜、上述第2绝缘膜及上述第3绝缘膜由硅氧化物构成，上述第4绝缘膜由硅氮化物构成。
7.如权利要求1～4中任一项所述的半导体装置，
上述第2绝缘膜中的上述第1绝缘膜侧的端部越靠近上述第1绝缘膜则越薄。
8.如权利要求1～4中任一项所述的半导体装置，
上述第3半导体层具有源极层，
上述第4半导体层具有：
漂移层；以及
漏极层，杂质浓度比上述漂移层的杂质浓度高，
上述第2绝缘膜的下部配置于上述源极层与上述漏极层之间。
CN201911356238.7A 2019-09-12 2019-12-25 半导体装置 Pending CN112490288A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019166211A JP7216629B2 (ja) 2019-09-12 2019-09-12 半導体装置
JP2019-166211 2019-09-12

Publications (1)

Publication Number Publication Date
CN112490288A true CN112490288A (zh) 2021-03-12

Family

ID=74864319

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911356238.7A Pending CN112490288A (zh) 2019-09-12 2019-12-25 半导体装置

Country Status (3)

Country Link
US (1) US11322608B2 (zh)
JP (1) JP7216629B2 (zh)
CN (1) CN112490288A (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070057293A1 (en) * 2005-09-13 2007-03-15 Ching-Hung Kao Ultra high voltage mos transistor device
JP2008098624A (ja) * 2006-09-15 2008-04-24 Sanyo Electric Co Ltd 半導体装置及びその製造方法
CN101431103A (zh) * 2007-11-07 2009-05-13 冲电气工业株式会社 半导体元件及其制造方法
CN101471380A (zh) * 2007-12-28 2009-07-01 东部高科股份有限公司 横向双扩散金属氧化物半导体晶体管及其制造方法
CN101587911A (zh) * 2008-05-23 2009-11-25 恩益禧电子股份有限公司 半导体器件及其制造方法
CN107275401A (zh) * 2016-03-30 2017-10-20 精工半导体有限公司 半导体装置和半导体装置的制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59161871A (ja) 1983-02-16 1984-09-12 ノ−ザン・テレコム・リミテツド 高電圧金属オキサイド半導体トランジスタ
JP2002270830A (ja) 2001-03-12 2002-09-20 Fuji Electric Co Ltd 半導体装置
EP1321985B1 (en) * 2001-12-20 2007-10-24 STMicroelectronics S.r.l. Method of integrating metal oxide semiconductor field effect transistors
JP4042530B2 (ja) 2002-10-30 2008-02-06 富士電機デバイステクノロジー株式会社 半導体装置
JP3897801B2 (ja) * 2005-08-31 2007-03-28 シャープ株式会社 横型二重拡散型電界効果トランジスタおよびそれを備えた集積回路
JP5211652B2 (ja) * 2007-11-16 2013-06-12 トヨタ自動車株式会社 横型ｍｏｓトランジスタの製造方法
JP5354951B2 (ja) 2008-05-13 2013-11-27 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法
DE102011087845B4 (de) * 2011-12-06 2015-07-02 Infineon Technologies Ag Laterales transistorbauelement und verfahren zu dessen herstellung
TWI476926B (zh) * 2012-12-25 2015-03-11 Richtek Technology Corp 橫向雙擴散金屬氧化物半導體元件製造方法
US9184282B2 (en) * 2013-08-09 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Ultra-high voltage laterally-diffused MOS devices and methods of forming the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070057293A1 (en) * 2005-09-13 2007-03-15 Ching-Hung Kao Ultra high voltage mos transistor device
US20090072326A1 (en) * 2005-09-13 2009-03-19 Ching-Hung Kao Ultra high voltage mos transistor device
JP2008098624A (ja) * 2006-09-15 2008-04-24 Sanyo Electric Co Ltd 半導体装置及びその製造方法
CN101431103A (zh) * 2007-11-07 2009-05-13 冲电气工业株式会社 半导体元件及其制造方法
CN101471380A (zh) * 2007-12-28 2009-07-01 东部高科股份有限公司 横向双扩散金属氧化物半导体晶体管及其制造方法
CN101587911A (zh) * 2008-05-23 2009-11-25 恩益禧电子股份有限公司 半导体器件及其制造方法
CN107275401A (zh) * 2016-03-30 2017-10-20 精工半导体有限公司 半导体装置和半导体装置的制造方法

Also Published As

Publication number Publication date
US11322608B2 (en) 2022-05-03
JP7216629B2 (ja) 2023-02-01
US20210083106A1 (en) 2021-03-18
JP2021044432A (ja) 2021-03-18

Similar Documents

Publication Publication Date Title
US20190172930A1 (en) Hybrid active-field gap extended drain mos transistor
US7345341B2 (en) High voltage semiconductor devices and methods for fabricating the same
US9209277B2 (en) Manufacturing methods for laterally diffused metal oxide semiconductor devices
US9842924B2 (en) Semiconductor device having an electrode that is in a peripheral trench region and at a same potential as a source electrode
US6677210B1 (en) High voltage transistors with graded extension
CN111048420B (zh) 横向双扩散晶体管的制造方法
US20220157989A1 (en) Mosfet device with shielding region and manufacturing method thereof
US9748377B2 (en) Semiconductor device and method of manufacturing the same
US20170236930A1 (en) Vertical double-diffused metal-oxide semiconductor field-effect transistor and manufacturing method therefor
CN110828567A (zh) 半导体装置
CN110957370B (zh) 横向双扩散晶体管的制造方法
US9362398B2 (en) Low resistance LDMOS with reduced gate charge
US20180204926A1 (en) Transistor using selective undercut at gate conductor and gate insulator corner
CN109585558B (zh) 具有多个栅极结构的ldmos finfet结构
US11430885B2 (en) Semiconductor device
CN110911477B (zh) 半导体装置
CN112490288A (zh) 半导体装置
JP7148440B2 (ja) 半導体装置
US11217690B2 (en) Trench field electrode termination structure for transistor devices
US10522620B2 (en) Semiconductor device having a varying length conductive portion between semiconductor regions
US20230261105A1 (en) Semiconductor device
US20230290876A1 (en) Semiconductor device
US20220102550A1 (en) Metal oxide semiconductor device and method for manufacturing the same
CN111146286B (zh) 半导体装置
JP2022137629A (ja) 半導体装置、及び半導体装置の製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination