JP3897801B2 - 横型二重拡散型電界効果トランジスタおよびそれを備えた集積回路 - Google Patents
横型二重拡散型電界効果トランジスタおよびそれを備えた集積回路 Download PDFInfo
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- JP3897801B2 JP3897801B2 JP2005251475A JP2005251475A JP3897801B2 JP 3897801 B2 JP3897801 B2 JP 3897801B2 JP 2005251475 A JP2005251475 A JP 2005251475A JP 2005251475 A JP2005251475 A JP 2005251475A JP 3897801 B2 JP3897801 B2 JP 3897801B2
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- 230000005669 field effect Effects 0.000 title claims description 49
- 238000009792 diffusion process Methods 0.000 claims description 201
- 230000015556 catabolic process Effects 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- 230000005684 electric field Effects 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0886—Shape
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第1導電型の半導体層の表面に、実質的に矩形のパターンを用いて形成された第2導電型のボディ拡散層と、
上記ボディ拡散層内で、このボディ拡散層の表面の一部を占める領域に形成された第1導電型のソース拡散層と、
上記第1導電型の半導体層の表面のうち上記ボディ拡散層を離間して取り囲む領域に形成された第1導電型のドレイン拡散層と、
少なくとも上記ソース拡散層とドレイン拡散層との間の上記半導体層の表面を、ゲート絶縁膜を介して覆うゲート電極とを備え、
上記ゲート絶縁膜は、上記ソース拡散層から上記ボディ拡散層のパターンを越えた領域まで覆う第1ゲート絶縁膜と、この第1ゲート絶縁膜よりも膜厚が厚く、上記第1ゲート絶縁膜が覆う領域よりも上記ドレイン拡散層に近い領域を覆う第2ゲート絶縁膜とを含み、
上記第1ゲート絶縁膜と第2ゲート絶縁膜との間の境界線は、上記ボディ拡散層のパターンの辺に平行なストレート部と、上記ボディ拡散層のパターンの頂点を離間して取り囲むコーナー部とからなり、
上記ボディ拡散層のパターンの頂点と上記境界線のコーナー部との間の距離は、上記ボディ拡散層のパターンの辺と上記境界線のストレート部との間の距離以下であることを特徴とする。
同一の半導体基板上に、請求項1に記載の横型二重拡散型電界効果トランジスタと、ゲート絶縁膜の膜厚がそれぞれ実質的に一定で、互いに異なるドレイン耐圧を有する第1および第2の種類の電界効果トランジスタとを少なくとも備え、
上記横型二重拡散型電界効果トランジスタの上記第1ゲート絶縁膜の膜厚は、或るドレイン耐圧を有する第1の種類の電界効果トランジスタのゲート絶縁膜の膜厚と実質的に同じであり、
上記横型二重拡散型電界効果トランジスタの上記第2ゲート絶縁膜の膜厚は、上記ドレイン耐圧よりも高いドレイン耐圧を有する第2の種類の電界効果トランジスタのゲート絶縁膜の膜厚と実質的に同じであることを特徴とする。
2 Nウェル拡散層
3 Pボディ拡散層
4a 第2ゲート酸化膜
4b 第1ゲート酸化膜
5 ゲート電極
6 N+ソース拡散層
7 N+ドレイン拡散層
9 N型エピタキシャル層
13 境界線
13c,13r,13t コーナー部
13n ストレート部
Claims (7)
- 第1導電型の半導体層の表面に、実質的に矩形のパターンを用いて形成された第2導電型のボディ拡散層と、
上記ボディ拡散層内で、このボディ拡散層の表面の一部を占める領域に形成された第1導電型のソース拡散層と、
上記第1導電型の半導体層の表面のうち上記ボディ拡散層を離間して取り囲む領域に形成された第1導電型のドレイン拡散層と、
少なくとも上記ソース拡散層とドレイン拡散層との間の上記半導体層の表面を、ゲート絶縁膜を介して覆うゲート電極とを備え、
上記ゲート絶縁膜は、上記ソース拡散層から上記ボディ拡散層のパターンを越えた領域まで覆う第1ゲート絶縁膜と、この第1ゲート絶縁膜よりも膜厚が厚く、上記第1ゲート絶縁膜が覆う領域よりも上記ドレイン拡散層に近い領域を覆う第2ゲート絶縁膜とを含み、
上記第1ゲート絶縁膜と第2ゲート絶縁膜との間の境界線は、上記ボディ拡散層のパターンの辺に平行なストレート部と、上記ボディ拡散層のパターンの頂点を離間して取り囲むコーナー部とからなり、
上記ボディ拡散層のパターンの頂点と上記境界線のコーナー部との間の距離は、上記ボディ拡散層のパターンの辺と上記境界線のストレート部との間の距離以下であることを特徴とする横型二重拡散型電界効果トランジスタ。 - 請求項1に記載の横型二重拡散型電界効果トランジスタにおいて、
上記第1導電型の半導体層は、第2導電型の半導体基板上にエピタキシャル成長により形成されたエピタキシャル層であることを特徴とする横型二重拡散型電界効果トランジスタ。 - 請求項1に記載の横型二重拡散型電界効果トランジスタにおいて、
上記ボディ拡散層とドレイン拡散層との間で上記ドレイン拡散層に沿った領域に、上記第2ゲート絶縁膜に連なって形成されたロコスを備えることを特徴とする横型二重拡散型電界効果トランジスタ。 - 請求項1に記載の横型二重拡散型電界効果トランジスタにおいて、
上記境界線の各コーナー部は、そのコーナー部に連なる二つのストレート部に対して斜めに交差する線分であることを特徴とする横型二重拡散型電界効果トランジスタ。 - 請求項1に記載の横型二重拡散型電界効果トランジスタにおいて、
上記境界線の各コーナー部は、上記ボディ拡散層のパターンの対応する頂点を中心とした円弧であることを特徴とする横型二重拡散型電界効果トランジスタ。 - 請求項3に記載の横型二重拡散型電界効果トランジスタにおいて、
上記境界線と上記ロコスとの間の距離が、上記ボディ拡散層を取り囲む方向に沿って一定であることを特徴とする横型二重拡散型電界効果トランジスタ。 - 同一の半導体基板上に、請求項1に記載の横型二重拡散型電界効果トランジスタと、ゲート絶縁膜の膜厚がそれぞれ実質的に一定で、互いに異なるドレイン耐圧を有する第1および第2の種類の電界効果トランジスタとを少なくとも備え、
上記横型二重拡散型電界効果トランジスタの上記第1ゲート絶縁膜の膜厚は、或るドレイン耐圧を有する第1の種類の電界効果トランジスタのゲート絶縁膜の膜厚と実質的に同じであり、
上記横型二重拡散型電界効果トランジスタの上記第2ゲート絶縁膜の膜厚は、上記ドレイン耐圧よりも高いドレイン耐圧を有する第2の種類の電界効果トランジスタのゲート絶縁膜の膜厚と実質的に同じであることを特徴とする集積回路。
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JP2005251475A JP3897801B2 (ja) | 2005-08-31 | 2005-08-31 | 横型二重拡散型電界効果トランジスタおよびそれを備えた集積回路 |
KR1020060078185A KR100781213B1 (ko) | 2005-08-31 | 2006-08-18 | 횡형 2중 확산형 전계 효과 트랜지스터 및 그를 구비한집적회로 |
TW095130839A TWI309080B (en) | 2005-08-31 | 2006-08-22 | Lateral double-diffused field effect transistor and integrated circuit having same |
US11/509,717 US7485924B2 (en) | 2005-08-31 | 2006-08-25 | Lateral double-diffused field effect transistor and integrated circuit having same |
CNB2006101290191A CN100472809C (zh) | 2005-08-31 | 2006-08-29 | 横向双扩散场效应晶体管及含有它的集成电路 |
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JP2005251475A JP3897801B2 (ja) | 2005-08-31 | 2005-08-31 | 横型二重拡散型電界効果トランジスタおよびそれを備えた集積回路 |
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JP3897801B2 true JP3897801B2 (ja) | 2007-03-28 |
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US (1) | US7485924B2 (ja) |
JP (1) | JP3897801B2 (ja) |
KR (1) | KR100781213B1 (ja) |
CN (1) | CN100472809C (ja) |
TW (1) | TWI309080B (ja) |
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CN101266930B (zh) * | 2008-04-11 | 2010-06-23 | 北京大学 | 一种横向双扩散场效应晶体管的制备方法 |
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JPS55140262A (en) | 1979-04-19 | 1980-11-01 | Nippon Gakki Seizo Kk | Semiconductor device |
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US5585294A (en) * | 1994-10-14 | 1996-12-17 | Texas Instruments Incorporated | Method of fabricating lateral double diffused MOS (LDMOS) transistors |
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CN100472809C (zh) | 2009-03-25 |
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US7485924B2 (en) | 2009-02-03 |
US20070063271A1 (en) | 2007-03-22 |
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