GB2451122A - Low threshold voltage transistor with non-uniform thickness gate dielectric - Google Patents

Low threshold voltage transistor with non-uniform thickness gate dielectric Download PDF

Info

Publication number
GB2451122A
GB2451122A GB0714119A GB0714119A GB2451122A GB 2451122 A GB2451122 A GB 2451122A GB 0714119 A GB0714119 A GB 0714119A GB 0714119 A GB0714119 A GB 0714119A GB 2451122 A GB2451122 A GB 2451122A
Authority
GB
United Kingdom
Prior art keywords
gate
gate dielectric
dielectric layer
well region
thinner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0714119A
Other versions
GB0714119D0 (en
Inventor
Paul Ronald Stribley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
X Fab UK Ltd
Original Assignee
X Fab UK Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by X Fab UK Ltd filed Critical X Fab UK Ltd
Priority to GB0714119A priority Critical patent/GB2451122A/en
Publication of GB0714119D0 publication Critical patent/GB0714119D0/en
Priority to PCT/GB2008/050606 priority patent/WO2009013537A1/en
Publication of GB2451122A publication Critical patent/GB2451122A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A transistor comprises a body 6, a source, a gate 10, a drain 13, a gate dielectric layer 11, 12 for isolating the gate 10 from the body 6, and a well region 5 at least partially extending under the gate 10 to create a channel region. The gate dielectric layer comprises a thinner 12 and a thicker portion 11. The thicker portion 11 of the gate dielectric has a thickness intermediate between the thinner portion 12 and a field oxide dielectric 8. Further, the well region 5 does not reach the area covered by the thicker portion 11 of the gate dielectric layer. Therefore, the channel region is only formed in a region under the thinner dielectric portion 12. The transistor structure is useful for integrating high and low voltage CMOS processes.

Description

IMPROVEMENTS IN TRANSISTORS
The present invention relates to transistors. The invention fmds particular application in CMOS transistors.
High voltage (HV) CMOS processes can be integrated with lower voltage components.
For the purpose of this specification the term "high voltage" is preferably intended to mean voltages of 6V or more, and it will be appreciated that the term "high voltage" may cover a range of up to several hundreds of Volts or more.
When high voltage CMOS processes are integrated with lower voltage components problems can arise at the interface between high and low voltage capability. The lower voltages, when applied to the gate region, should be able to switch higher voltages at the drain. This may be accomplished using a CMOS process, where the channel region of a high voltage device is formed using a thin gate oxide under the polysilicon gate but the drain part of the transistor is made using a thicker oxide (e.g. field oxide).
The present Inventor has appreciated that some problems may be associated with the above technique: If the thin oxide is continuous/of uniform thickness then the termination of the well zone will mean that the surface part of the drift region is doped with the threshold adjust implant (boron in the case of HV-NMOS). The presence of the p-type surface region disconnects the channel from the HV drift region and this causes the device to malfunction.
The present invention aims to address this problem. In order to achieve a functional layout of the transistor with thin gate oxide channel the present Inventor has devised a transistor with a gate dielectric region formed adjacent to the channel which is of intermediate thickness. This region is adjacent to a thicker oxide which is used to create a high voltage drain zone.
Accordingly, in one aspect the present invention provides a transistor comprising: a body; a source; a gate; a drain; a gate dielectric layer for isolating the gate from the body; and a well region at least partially extending under the gate to create a channel region; wherein the gate dielectric layer comprises a thinner and a thicker portion, and wherein the well region does not reach the area covered by the thicker portion of the gate dielectric layer.
Although in the previous paragraph reference is made to "a thicker portion", this is intended to refer to the layer of intermediate thickness. This layer of intermediate thickness is thicker than the "thinner portion".
Preferably, the dielectric layer comprises an oxide layer.
In preferred embodiments the creation of a thin oxide to medium oxide transition zone helps a high voltage NMOS device to have the correct electrical behaviour. This device may then have a low threshold voltage, high drive current with low gate bias and also high voltage drain capability.
Some preferred embodiments of the invention will now be described by way of example only and with reference to the accompanying drawings, in which: Figure 1 shows a sectional view of a transistor according to an embodiment of the present invention.
Figure 2 shows a plan view of the layout of the transistor of Figure 1.
The features shown in Figs. 1 and 2 are as follows: 1. Metallisation connection 2. Interlayer dielectric 3. Contact metal 4. Heavily doped p+ diffusion.
5. Lightly doped p-diffusion; p-well, body 6. Lightly doped n-diffusion; deep n-well 7. Lightly doped p-diffusion; deep p-well
8. Field oxide dielectric
9. Metal suicide 10. Heavily doped polysilicon gate 11. Medium (thicker) gate dielectric 12. Thin gate dielectric 13. Heavily doped n+ diffusion 14. P-substrate B Base Connection S Source connection 0 Gate connection D Drain connection Referring to Figures 1 and 2, the lightly doped p-well 5 extends under the source and also partially under the gate 10. The lightly doped p-well 5 is located within lightly doped deep n- well 6. As can be seen in particular in Figure 1, the gate 10 is isolated from p-well 5 and n-well 6 by means of a dielectric layer 11, 12. This has a thinner portion 12 and a thicker portion 11. Although thicker portion 11 is thicker than the thinner portion 12, its thickness is still much less than the thickness of the field oxide dielectric 8, which defines the drain region. The thickness of the thicker portion 11 may for example be between l2nm and lOOnm and is preferably between 2Onm and 8Onm.
Good results have been achieved with a thickness of 4Onm. The thickness of the thinner portion 12 may for example be between 2nm and SOnm, preferably between 4nm and 2Onm. Good results have been achieved with a thickness of about 7nm.
The double-arrow in Figure 1 indicates the channel region. It is formed where the gate 10 overlaps with the p-well 5. The deep n-well 6 defines a drift region. As can be seen in Figure 1, the transition from the thinner portion 12 to the thicker portion 11 is above the drift region and not above the channel region. Expressed differently, the p-well 5 does not reach the area covered by the thicker portion 11.
With a thin to medium oxide step, the channel can interface to the drift region which is immediately under the medium oxide 11. This region does not have any surface p-type zone. Thus the channel can be effectively connected to the drain drift region. With the arrangement shown in the drawings the transistor channel region terminates before the drift region begins.
The p-well region 5 should be positioned carefully with respect to the thin-medium oxide interface, since the p-well 5, if it extended under the medium oxide 11, would normally cause the threshold voltage of the device to rise to unacceptable levels. This would also be true if the p-well 5 extended all the way over to the field oxide part 8. In preferred embodiments the magnitude of the threshold voltage can be kept below 3V, preferably below 2V, more preferably below I.4V and yet more preferably below 0.5V.
It could be as low as substantially OV.
The p-well 5 is kept slightly back from the thin-medium oxide (12,11) join region. It terminates in the thin oxide area. As a result, the channel region inverts at a suitably low threshold voltage and can still effectively connect to the drain drift region which starts under the medium gate oxide 11 and proceeds under the thicker field oxide region 8 -eventually terminating in the drain region.
In principle, the (in Figure 1 rightmost) edge of the p-well 5 could be located precisely under the transition from the thinner portion 12 to the thicker portion 11. However, with currently available manufacturing processes and their tolerances it is best to design the device such that the edge of the p-well 5 is kept a certain distance back from the transition, for example 250nm, depending on manufacturing tolerances. This would ensure that despite slight misalignment the p-well 5 does not reach the area covered by the thicker portion 11.
The thicker portion 11 may have the effect that it prevents implant, which may be used during manufacture of the transistor, from entering the material below the thicker portion 11, or at least reduce the amount of implant entering the material below the thicker portion.
It will be appreciated that the transition from the thinner portion 12 to the thicker portion 11 can be any suitable shape. Whilst a step as shown in Figure 1 is preferred for ease of manufacture, a gradient or similar may also be suitable.
Whilst the above embodiment has been described with reference to an oxide layer 11, 12, it will be appreciated that this layer does not have to be an oxide layer but could be any other dielectric layer.
It will further be appreciated that all polarities mentioned above could be reversed, the resulting devices still being in accordance with the present invention.
In the present specification some directional or positional terms (such as "above" or "covered by") have been used. These are to be interpreted in accordance with what is shown in Figure 1, but it will be appreciated that the claims are not limited to devices which are in the same orientation as the device shown in Fig. 1.
Some claims refer to the term "drain edge". Whilst the meaning of this term is believed to be clear to one skilled in the art, in order to provide further guidance it is noted that in Fig. 1 the drain edge would be at the left-hand side of the thick field oxide dielectric 8 which is located to the left of the heavily doped n+ diffusion 13 and the metal silicide 9 of the drain.
Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims (10)

  1. CLAIMS: 1. A transistor comprising: a body; a source; a gate; a drain; a gate dielectric layer for isolating the gate from the body; and a well region at least partially extending under the gate to create a channel region; wherein the gate dielectric layer comprises a thinner and a thicker portion, and wherein the well region does not reach the area covered by the thicker portion of the gate dielectric layer.
  2. 2. A transistor comprising: a body; a source; a gate; a drain; a gate dielectric layer for isolating the gate from the body; and a well region at least partially extending under the gate to create a channel region; wherein the gate dielectric layer comprises a thinner and a thicker portion, and wherein the well region is sufficiently far removed from the area covered by the thicker portion of the gate dielectric layer so that the threshold voltage of the transistor remains below 3V.
  3. 3. A transistor according to claim 1 or 2, further comprising a dielectric portion defining a high voltage drain zone.
  4. 4. A transistor according to claim 3, wherein the thicker portion is thinner than said dielectric portion.
  5. 5. A transistor according to any preceding claim, wherein the thickness of the thinner portion is between 2nm and 5Onm and the thickness of the thicker portion is between I2nm and lOOnm.
  6. 6. A transistor according to any preceding claim, wherein the well region does not touch the drain edge.
  7. 7. A transistor according to claim 6, wherein the transition from the thinner portion to the thicker portion is above a point between the edge of the well region and the drain edge.
  8. 8. A transistor according to any preceding claim, wherein the gate dielectric layer comprises a gate oxide layer.
  9. 9. A transistor according to any preceding claim, further comprising a p-substrate, wherein the well region is a p-well region.
  10. 10. A transistor, substantially as herein described with reference to, or as illustrated in, the accompanying drawings.
GB0714119A 2007-07-20 2007-07-20 Low threshold voltage transistor with non-uniform thickness gate dielectric Withdrawn GB2451122A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB0714119A GB2451122A (en) 2007-07-20 2007-07-20 Low threshold voltage transistor with non-uniform thickness gate dielectric
PCT/GB2008/050606 WO2009013537A1 (en) 2007-07-20 2008-07-21 Mis field-effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0714119A GB2451122A (en) 2007-07-20 2007-07-20 Low threshold voltage transistor with non-uniform thickness gate dielectric

Publications (2)

Publication Number Publication Date
GB0714119D0 GB0714119D0 (en) 2007-08-29
GB2451122A true GB2451122A (en) 2009-01-21

Family

ID=38476640

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0714119A Withdrawn GB2451122A (en) 2007-07-20 2007-07-20 Low threshold voltage transistor with non-uniform thickness gate dielectric

Country Status (2)

Country Link
GB (1) GB2451122A (en)
WO (1) WO2009013537A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120211859A1 (en) * 2011-02-18 2012-08-23 Stribley Paul R Schottky diode

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102646712B (en) * 2012-05-04 2015-05-06 上海先进半导体制造股份有限公司 Laterally diffused metal oxide semiconductor (LDMOS) and manufacturing method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6191453B1 (en) * 1999-12-13 2001-02-20 Philips Electronics North America Corporation Lateral insulated-gate bipolar transistor (LIGBT) device in silicon-on-insulator (SOI) technology
WO2001037346A1 (en) * 1999-11-16 2001-05-25 Koninklijke Philips Electronics N.V. Lateral thin-film soi device having a lateral drift region and method of making such a device
US20020145172A1 (en) * 2001-03-12 2002-10-10 Naoto Fujishima High withstand voltage semiconductor device
WO2003038905A2 (en) * 2001-11-01 2003-05-08 Koninklijke Philips Electronics N.V. Lateral soi field-effect transistor
US20060197149A1 (en) * 2005-03-07 2006-09-07 Keiji Fujimoto Semiconductor device and fabrication process thereof, and application thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003168796A (en) * 2001-11-30 2003-06-13 Sanyo Electric Co Ltd Method for manufacturing semiconductor device
DE102004049246A1 (en) * 2004-10-01 2006-04-06 Atmel Germany Gmbh Lateral DMOS transistor and method for its manufacture
JP3897801B2 (en) * 2005-08-31 2007-03-28 シャープ株式会社 Horizontal double-diffused field effect transistor and integrated circuit having the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001037346A1 (en) * 1999-11-16 2001-05-25 Koninklijke Philips Electronics N.V. Lateral thin-film soi device having a lateral drift region and method of making such a device
US6191453B1 (en) * 1999-12-13 2001-02-20 Philips Electronics North America Corporation Lateral insulated-gate bipolar transistor (LIGBT) device in silicon-on-insulator (SOI) technology
US20020145172A1 (en) * 2001-03-12 2002-10-10 Naoto Fujishima High withstand voltage semiconductor device
WO2003038905A2 (en) * 2001-11-01 2003-05-08 Koninklijke Philips Electronics N.V. Lateral soi field-effect transistor
US20060197149A1 (en) * 2005-03-07 2006-09-07 Keiji Fujimoto Semiconductor device and fabrication process thereof, and application thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120211859A1 (en) * 2011-02-18 2012-08-23 Stribley Paul R Schottky diode
US8513764B2 (en) * 2011-02-18 2013-08-20 X-Fab Semiconductor Foundries Ag Schottky diode

Also Published As

Publication number Publication date
WO2009013537A1 (en) 2009-01-29
GB0714119D0 (en) 2007-08-29

Similar Documents

Publication Publication Date Title
US7602017B2 (en) Short channel LV, MV, and HV CMOS devices
US7091079B2 (en) Method of forming devices having three different operation voltages
US20170263763A1 (en) Semiconductor device
US6172401B1 (en) Transistor device configurations for high voltage applications and improved device performance
US9748383B2 (en) Transistor
US8063444B2 (en) Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability in integrated circuit
US7344947B2 (en) Methods of performance improvement of HVMOS devices
US8288235B2 (en) Self-aligned body fully isolated device
US20080237733A1 (en) Structure and method to enhance channel stress by using optimized sti stress and nitride capping layer stress
US20160351699A1 (en) Field-effect transistors with body dropdowns
US7598585B2 (en) Structure for preventing leakage of a semiconductor device
US20230378296A1 (en) Semiconductor device having multiple wells
US9577094B2 (en) Low cost demos transistor with improved CHC immunity
JP2004179496A (en) Semiconductor device
WO2007072292A1 (en) Asymmetrical field-effect semiconductor device with sti region
US9583613B2 (en) Metal oxide semiconductor devices and fabrication methods
US10256340B2 (en) High-voltage semiconductor device and method for manufacturing the same
US20090325352A1 (en) Methods of forming drain extended transistors
US10128331B1 (en) High-voltage semiconductor device and method for manufacturing the same
GB2451122A (en) Low threshold voltage transistor with non-uniform thickness gate dielectric
US7307320B2 (en) Differential mechanical stress-producing regions for integrated circuit field effect transistors
US20060255429A1 (en) Structure for leakage prevention of a high voltage device
US20070034973A1 (en) Methods and Apparatus for Operating a Transistor Using a Reverse Body Bias
US20140167152A1 (en) Reduced Gate Charge Trench Field-Effect Transistor
US20130062661A1 (en) Integrated circuit device

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)