JP6723775B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
- Publication number
- JP6723775B2 JP6723775B2 JP2016052841A JP2016052841A JP6723775B2 JP 6723775 B2 JP6723775 B2 JP 6723775B2 JP 2016052841 A JP2016052841 A JP 2016052841A JP 2016052841 A JP2016052841 A JP 2016052841A JP 6723775 B2 JP6723775 B2 JP 6723775B2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- concentration diffusion
- conductivity type
- conductivity
- concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 54
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000009792 diffusion process Methods 0.000 claims description 159
- 239000000758 substrate Substances 0.000 claims description 31
- 230000005684 electric field Effects 0.000 claims description 24
- 230000002040 relaxant effect Effects 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims 4
- 239000010410 layer Substances 0.000 description 94
- 239000012535 impurity Substances 0.000 description 18
- 230000015556 catabolic process Effects 0.000 description 16
- 238000010438 heat treatment Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
そこで、本発明は、チャネル幅を増加させずに十分な耐圧とESD耐性を有する半導体装置を提供することを課題とする。
第1導電型半導体基板と、前記基板上にゲート酸化膜を介し設けられたゲート電極と、前記ゲート電極の両側の前記基板上に設けられた第2導電型のソース拡散層とドレイン拡散層と、前記ドレイン拡散層を覆うように前記ゲート酸化膜下に達する電界緩和用の第2導電型低濃度拡散層が形成された半導体装置において、前記電界緩和用の第2導電型低濃度拡散層の中に第2導電型中濃度拡散層を配置し、さらに、熱処理を極力抑えることにより高濃度かつ構造のばらつきの少ない第2導電型高濃度拡散層を前記第2導電型中濃度拡散層の中に配置したことを特徴とする半導体装置とした。
第1の実施例のN型MOSトランジスタは、第1導電型半導体基板100と、半導体基板100上にゲート酸化膜(図示せず)を介し配置されたゲート電極105と、ゲート電極の両側の半導体基板上に配置された第2導電型のソース拡散層106およびLOCOS酸化膜104を介して配置されたドレイン拡散層107と、ドレイン拡散層107を覆うようにゲート酸化膜下に達するように配置された電界緩和用の第2導電型低濃度拡散層101と、第2導電型低濃度拡散層101の中に配置された電界緩和用の第2導電型中濃度拡散層102と、第2導電型中濃度拡散層102の中に配置された電界緩和用の第2導電型高濃度拡散層103と、で構成されている。ソース拡散層106およびドレイン拡散層107は高濃度に不純物が拡散された領域であり、通常配線が接続される領域として使用される。
続いて、レジスト膜108を除去した後に、図5(b)のようにN型領域101Aの内側が開口するようにレジスト膜108をつけ、それをマスクにしてN型不純物をイオン注入してN型領域102Aを形成する。
続いて、図8のように、LOCOS酸化膜104とゲート電極105をマスクとして利用してソース拡散層106、ドレイン拡散層107を形成する。
この作成法を用いれば、素子面積は増加するものの、ソースとドレインの電位を反転させても実施例1と同じように働く半導体装置を得ることができる。
第4の実施例のN型MOSトランジスタは、第1導電型半導体基板100と、基板100上にゲート酸化膜(図示せず)を介し配置されたゲート電極105と、ゲート電極の両側の基板上に配置された第2導電型のソース拡散層106およびLOCOS酸化膜104を介して配置されたドレイン拡散層107と、ドレイン拡散層107に接し、ゲート酸化膜下に達する電界緩和用の第2導電型低濃度拡散層301と、ドレイン拡散層107とチャネルの間からドレイン拡散層107を覆うように配置された第2導電型中濃度拡散層102と、第2導電型中濃度拡散層102の中に配置された第2導電型高濃度拡散層103で構成されている。
101 第2導電型低濃度拡散層
102 第2導電型中濃度拡散層
103 第2導電型高濃度拡散層
104 LOCOS酸化膜
105 ゲート電極
106 ソース拡散層
107 ドレイン拡散層
108 レジスト膜
101A 拡散させる前の第2導電型低濃度拡散層
102A 拡散させる前の第2導電型中濃度拡散層
200 N型半導体基板(Nsub)
201 第1導電型低濃度拡散層
202 第1導電型中濃度拡散層
203 第1導電型高濃度拡散層
301 LOCOS酸化膜下のみに形成した第2導電型低濃度拡散層
Claims (6)
- 第1導電型の半導体基板と、
前記半導体基板上にゲート酸化膜を介し設けられたゲート電極と、
前記ゲート電極の両側の前記半導体基板上に設けられた第2導電型のソース拡散層とドレイン拡散層と、
前記ドレイン拡散層を覆うように配置された、前記ゲート酸化膜下に達する電界緩和用の第2導電型低濃度拡散層と、
前記電界緩和用の第2導電型低濃度拡散層の中に、前記半導体基板の表面において、前記電界緩和用の第2導電型低濃度拡散層の境界から前記ドレイン拡散層に向かう方向に離れて配置された第2導電型中濃度拡散層と、
前記第2導電型中濃度拡散層の中に、前記半導体基板の表面において、前記第2導電型中濃度拡散層の境界から前記ドレイン拡散層に向かう方向に離れて配置された第2導電型高濃度拡散層と、
を有する半導体装置。 - 前記第2導電型高濃度拡散層は、前記第2導電型低濃度拡散層および前記第2導電型中濃度拡散層に比べ、高濃度かつばらつきの少ない拡散層である請求項1記載の半導体装置。
- 前記ソース拡散層を覆うように配置された、前記ゲート酸化膜下に達する電界緩和用の第2の第2導電型低濃度拡散層と、
前記電界緩和用の第2の第2導電型低濃度拡散層の中に配置された第2の第2導電型中濃度拡散層と、
前記第2の第2導電型中濃度拡散層の中に配置された第2の第2導電型高濃度拡散層と、
をさらに有する請求項1または2記載の半導体装置。 - 第1導電型半導体基板と、
前記基板上にゲート酸化膜を介し設けられたゲート電極と、
前記ゲート電極の両側の前記基板上に設けられた第2導電型のソース拡散層およびLOCOS酸化膜を介して設けられたドレイン拡散層と、
前記ドレイン拡散層を覆うように配置された、前記ゲート酸化膜下に達する電界緩和用の第2導電型低濃度拡散層と、
前記電界緩和用の第2導電型低濃度拡散層の中に、前記LOCOS酸化膜の直下において、前記電界緩和用の第2導電型低濃度拡散層の境界から前記ドレイン拡散層に向かう方向に離れて配置された第2導電型中濃度拡散層と、
前記第2導電型中濃度拡散層の中に、前記LOCOS酸化膜の直下において、前記第2導電型中濃度拡散層の境界から前記ドレイン拡散層に向かう方向に離れて配置された第2導電型高濃度拡散層と、
を有する半導体装置。 - 前記電界緩和用の第2導電型低濃度拡散層は、前記LOCOS酸化膜の下にのみ配置されている請求項4記載の半導体装置。
- 第1導電型の半導体基板と、前記半導体基板上にゲート酸化膜を介し設けられたゲート電極と、前記ゲート電極の両側の前記半導体基板上に設けられた第2導電型のソース拡散層とドレイン拡散層と、前記ドレイン拡散層を覆うように配置された、前記ゲート酸化膜下に達する電界緩和用の第2導電型低濃度拡散層と、前記電界緩和用の第2導電型低濃度拡散層の中に配置された第2導電型中濃度拡散層と、前記第2導電型中濃度拡散層の中に配置された第2導電型高濃度拡散層と、を有する半導体装置の製造方法であって、
前記第2導電型低濃度拡散層となる領域をイオン注入により形成する工程と、
前記第2導電型低濃度拡散層となる領域の内側に、前記半導体基板の表面において、前記第2導電型低濃度拡散層となる領域の境界から前記ドレイン拡散層に向かう方向に離れて、前記第2導電型中濃度拡散層となる領域をイオン注入により形成する工程と、
前記第2導電型低濃度拡散層および前記第2導電型中濃度拡散層を熱拡散により形成する工程と、
前記第2導電型中濃度拡散層の内側に、前記半導体基板の表面に置いて、前記第2導電型中濃度拡散層の境界から前記ドレイン拡散層に向かう方向に離れて、前記第2導電型高濃度拡散層をイオン注入により形成する工程と、
前記第2導電型高濃度拡散層をイオン注入により形成した後に、前記第2導電型低濃度拡散層、前記第2導電型中濃度拡散層、及び前記第2導電型高濃度拡散層の上にLOCOS酸化膜を形成する工程と、
を有する半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016052841A JP6723775B2 (ja) | 2016-03-16 | 2016-03-16 | 半導体装置および半導体装置の製造方法 |
TW106108248A TWI726069B (zh) | 2016-03-16 | 2017-03-14 | 半導體裝置以及半導體裝置的製造方法 |
KR1020170031953A KR102255544B1 (ko) | 2016-03-16 | 2017-03-14 | 반도체 장치 및 반도체 장치의 제조 방법 |
US15/459,548 US20170271453A1 (en) | 2016-03-16 | 2017-03-15 | Semiconductor device and method of manufacturing the same |
CN201710152563.6A CN107204370B (zh) | 2016-03-16 | 2017-03-15 | 半导体装置和半导体装置的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016052841A JP6723775B2 (ja) | 2016-03-16 | 2016-03-16 | 半導体装置および半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017168650A JP2017168650A (ja) | 2017-09-21 |
JP6723775B2 true JP6723775B2 (ja) | 2020-07-15 |
Family
ID=59847821
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016052841A Active JP6723775B2 (ja) | 2016-03-16 | 2016-03-16 | 半導体装置および半導体装置の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20170271453A1 (ja) |
JP (1) | JP6723775B2 (ja) |
KR (1) | KR102255544B1 (ja) |
CN (1) | CN107204370B (ja) |
TW (1) | TWI726069B (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI791009B (zh) * | 2018-01-19 | 2023-02-01 | 力智電子股份有限公司 | 半導體元件 |
JP7500247B2 (ja) | 2020-03-31 | 2024-06-17 | エイブリック株式会社 | 半導体装置 |
Family Cites Families (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5306652A (en) * | 1991-12-30 | 1994-04-26 | Texas Instruments Incorporated | Lateral double diffused insulated gate field effect transistor fabrication process |
US5376566A (en) * | 1993-11-12 | 1994-12-27 | Micron Semiconductor, Inc. | N-channel field effect transistor having an oblique arsenic implant for lowered series resistance |
KR0150992B1 (ko) * | 1994-08-31 | 1998-10-01 | 김광호 | 고내압용 모스 트랜지스터 및 그 제조방법 |
US5719425A (en) * | 1996-01-31 | 1998-02-17 | Micron Technology, Inc. | Multiple implant lightly doped drain (MILDD) field effect transistor |
JP3185656B2 (ja) * | 1996-03-22 | 2001-07-11 | 富士電機株式会社 | 横型電界効果トランジスタおよびその製造方法 |
US5747373A (en) * | 1996-09-24 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Nitride-oxide sidewall spacer for salicide formation |
US5847428A (en) * | 1996-12-06 | 1998-12-08 | Advanced Micro Devices, Inc. | Integrated circuit gate conductor which uses layered spacers to produce a graded junction |
US5766969A (en) * | 1996-12-06 | 1998-06-16 | Advanced Micro Devices, Inc. | Multiple spacer formation/removal technique for forming a graded junction |
US5869879A (en) * | 1996-12-06 | 1999-02-09 | Advanced Micro Devices, Inc. | CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions |
US5846866A (en) * | 1997-02-07 | 1998-12-08 | National Semiconductor Corporation | Drain extension regions in low voltage lateral DMOS devices |
KR100302187B1 (ko) * | 1997-10-08 | 2001-11-22 | 윤종용 | 반도체장치제조방법 |
US5977600A (en) * | 1998-01-05 | 1999-11-02 | Advanced Micro Devices, Inc. | Formation of shortage protection region |
US5970353A (en) * | 1998-03-30 | 1999-10-19 | Advanced Micro Devices, Inc. | Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion |
US6020611A (en) * | 1998-06-10 | 2000-02-01 | Motorola, Inc. | Semiconductor component and method of manufacture |
US6117738A (en) * | 1998-11-20 | 2000-09-12 | United Microelectronics Corp. | Method for fabricating a high-bias semiconductor device |
US6198131B1 (en) * | 1998-12-07 | 2001-03-06 | United Microelectronics Corp. | High-voltage metal-oxide semiconductor |
JP2002118177A (ja) * | 2000-10-11 | 2002-04-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP3831598B2 (ja) * | 2000-10-19 | 2006-10-11 | 三洋電機株式会社 | 半導体装置とその製造方法 |
JP3831615B2 (ja) * | 2001-01-16 | 2006-10-11 | 三洋電機株式会社 | 半導体装置とその製造方法 |
JP4408679B2 (ja) * | 2003-10-09 | 2010-02-03 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP4100364B2 (ja) * | 2004-03-15 | 2008-06-11 | セイコーエプソン株式会社 | 半導体装置および半導体装置の製造方法 |
JP5114824B2 (ja) * | 2004-10-15 | 2013-01-09 | 富士通セミコンダクター株式会社 | 半導体装置およびその製造方法 |
US7476947B2 (en) * | 2005-03-02 | 2009-01-13 | Ricoh Company, Ltd | Semiconductor device and method of manufacturing the same |
JP4783050B2 (ja) * | 2005-04-13 | 2011-09-28 | パナソニック株式会社 | 半導体装置及びその製造方法 |
JP2007266473A (ja) | 2006-03-29 | 2007-10-11 | Mitsumi Electric Co Ltd | 半導体装置 |
US7723748B2 (en) * | 2007-10-02 | 2010-05-25 | Ricoh Company, Ltd. | Semiconductor device including electrostatic discharge protection circuit |
JP2009231811A (ja) * | 2008-02-27 | 2009-10-08 | Seiko Instruments Inc | 半導体装置およびその製造方法 |
JP5239548B2 (ja) * | 2008-06-25 | 2013-07-17 | 富士通セミコンダクター株式会社 | 半導体装置及び半導体装置の製造方法 |
US8653607B2 (en) * | 2011-06-17 | 2014-02-18 | Texas Instruments Incorporated | Method for 1/F noise reduction in NMOS devices |
TWI467766B (zh) * | 2012-08-31 | 2015-01-01 | Nuvoton Technology Corp | 金氧半場效電晶體及其製造方法 |
JP2015032767A (ja) * | 2013-08-06 | 2015-02-16 | 株式会社日立製作所 | 半導体装置 |
US20150137230A1 (en) * | 2013-11-20 | 2015-05-21 | United Microelectronics Corp. | Laterally diffused metal oxide semiconductor and manufacturing method thereof |
CN105845688A (zh) * | 2015-02-03 | 2016-08-10 | 精工半导体有限公司 | 半导体非易失性存储元件及其制造方法 |
US9601614B2 (en) * | 2015-03-26 | 2017-03-21 | Nxp Usa, Inc. | Composite semiconductor device with different channel widths |
JP2016207853A (ja) * | 2015-04-23 | 2016-12-08 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP6688653B2 (ja) * | 2016-03-30 | 2020-04-28 | エイブリック株式会社 | 半導体装置および半導体装置の製造方法 |
TWI609486B (zh) * | 2016-12-30 | 2017-12-21 | 新唐科技股份有限公司 | 高壓半導體裝置 |
-
2016
- 2016-03-16 JP JP2016052841A patent/JP6723775B2/ja active Active
-
2017
- 2017-03-14 KR KR1020170031953A patent/KR102255544B1/ko active IP Right Grant
- 2017-03-14 TW TW106108248A patent/TWI726069B/zh active
- 2017-03-15 CN CN201710152563.6A patent/CN107204370B/zh active Active
- 2017-03-15 US US15/459,548 patent/US20170271453A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
TW201803110A (zh) | 2018-01-16 |
CN107204370B (zh) | 2022-01-04 |
US20170271453A1 (en) | 2017-09-21 |
CN107204370A (zh) | 2017-09-26 |
KR102255544B1 (ko) | 2021-05-24 |
JP2017168650A (ja) | 2017-09-21 |
TWI726069B (zh) | 2021-05-01 |
KR20170107913A (ko) | 2017-09-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20050006701A1 (en) | High voltage metal-oxide semiconductor device | |
JP5432750B2 (ja) | 半導体装置及び半導体装置の製造方法 | |
CN107275401B (zh) | 半导体装置和半导体装置的制造方法 | |
JP6723775B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP2024042049A (ja) | 半導体装置および半導体装置の製造方法 | |
TWI608546B (zh) | 橫向雙擴散金屬氧化物半導體元件及其製造方法 | |
JP6956600B2 (ja) | 半導体装置 | |
US10438943B2 (en) | Field-effect transistor and semiconductor device | |
TWI478343B (zh) | 半導體結構及其製程 | |
US9099556B2 (en) | Transistor having an active region with wing structure | |
CN105374854B (zh) | 半导体装置以及半导体装置的制造方法 | |
JP2009302114A (ja) | 半導体装置及びその製造方法 | |
JP6427388B2 (ja) | 半導体装置 | |
JP2010206163A (ja) | 半導体装置 | |
JP6368105B2 (ja) | トレンチ型mosfet半導体装置 | |
JP4950692B2 (ja) | 半導体装置 | |
KR101090049B1 (ko) | 반도체 디바이스 및 그의 제조 방법 | |
JP6099956B2 (ja) | 半導体装置 | |
JP2007184360A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20190111 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20191025 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20191105 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20191225 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200310 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200427 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20200603 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20200624 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6723775 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |