JP6723775B2 - 半導体装置および半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 54
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 238000009792 diffusion process Methods 0.000 claims description 159
- 239000000758 substrate Substances 0.000 claims description 31
- 230000005684 electric field Effects 0.000 claims description 24
- 230000002040 relaxant effect Effects 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims 4
- 239000010410 layer Substances 0.000 description 94
- 239000012535 impurity Substances 0.000 description 18
- 230000015556 catabolic process Effects 0.000 description 16
- 238000010438 heat treatment Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
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Description
そこで、本発明は、チャネル幅を増加させずに十分な耐圧とESD耐性を有する半導体装置を提供することを課題とする。
第1導電型半導体基板と、前記基板上にゲート酸化膜を介し設けられたゲート電極と、前記ゲート電極の両側の前記基板上に設けられた第2導電型のソース拡散層とドレイン拡散層と、前記ドレイン拡散層を覆うように前記ゲート酸化膜下に達する電界緩和用の第2導電型低濃度拡散層が形成された半導体装置において、前記電界緩和用の第2導電型低濃度拡散層の中に第2導電型中濃度拡散層を配置し、さらに、熱処理を極力抑えることにより高濃度かつ構造のばらつきの少ない第2導電型高濃度拡散層を前記第2導電型中濃度拡散層の中に配置したことを特徴とする半導体装置とした。
第1の実施例のN型MOSトランジスタは、第1導電型半導体基板100と、半導体基板100上にゲート酸化膜(図示せず)を介し配置されたゲート電極105と、ゲート電極の両側の半導体基板上に配置された第2導電型のソース拡散層106およびLOCOS酸化膜104を介して配置されたドレイン拡散層107と、ドレイン拡散層107を覆うようにゲート酸化膜下に達するように配置された電界緩和用の第2導電型低濃度拡散層101と、第2導電型低濃度拡散層101の中に配置された電界緩和用の第2導電型中濃度拡散層102と、第2導電型中濃度拡散層102の中に配置された電界緩和用の第2導電型高濃度拡散層103と、で構成されている。ソース拡散層106およびドレイン拡散層107は高濃度に不純物が拡散された領域であり、通常配線が接続される領域として使用される。
続いて、レジスト膜108を除去した後に、図5(b)のようにN型領域101Aの内側が開口するようにレジスト膜108をつけ、それをマスクにしてN型不純物をイオン注入してN型領域102Aを形成する。
続いて、図8のように、LOCOS酸化膜104とゲート電極105をマスクとして利用してソース拡散層106、ドレイン拡散層107を形成する。
この作成法を用いれば、素子面積は増加するものの、ソースとドレインの電位を反転させても実施例1と同じように働く半導体装置を得ることができる。
第4の実施例のN型MOSトランジスタは、第1導電型半導体基板100と、基板100上にゲート酸化膜(図示せず)を介し配置されたゲート電極105と、ゲート電極の両側の基板上に配置された第2導電型のソース拡散層106およびLOCOS酸化膜104を介して配置されたドレイン拡散層107と、ドレイン拡散層107に接し、ゲート酸化膜下に達する電界緩和用の第2導電型低濃度拡散層301と、ドレイン拡散層107とチャネルの間からドレイン拡散層107を覆うように配置された第2導電型中濃度拡散層102と、第2導電型中濃度拡散層102の中に配置された第2導電型高濃度拡散層103で構成されている。
101 第2導電型低濃度拡散層
102 第2導電型中濃度拡散層
103 第2導電型高濃度拡散層
104 LOCOS酸化膜
105 ゲート電極
106 ソース拡散層
107 ドレイン拡散層
108 レジスト膜
101A 拡散させる前の第2導電型低濃度拡散層
102A 拡散させる前の第2導電型中濃度拡散層
200 N型半導体基板(Nsub)
201 第1導電型低濃度拡散層
202 第1導電型中濃度拡散層
203 第1導電型高濃度拡散層
301 LOCOS酸化膜下のみに形成した第2導電型低濃度拡散層
Claims (6)
- 第1導電型の半導体基板と、
前記半導体基板上にゲート酸化膜を介し設けられたゲート電極と、
前記ゲート電極の両側の前記半導体基板上に設けられた第2導電型のソース拡散層とドレイン拡散層と、
前記ドレイン拡散層を覆うように配置された、前記ゲート酸化膜下に達する電界緩和用の第2導電型低濃度拡散層と、
前記電界緩和用の第2導電型低濃度拡散層の中に、前記半導体基板の表面において、前記電界緩和用の第2導電型低濃度拡散層の境界から前記ドレイン拡散層に向かう方向に離れて配置された第2導電型中濃度拡散層と、
前記第2導電型中濃度拡散層の中に、前記半導体基板の表面において、前記第2導電型中濃度拡散層の境界から前記ドレイン拡散層に向かう方向に離れて配置された第2導電型高濃度拡散層と、
を有する半導体装置。 - 前記第2導電型高濃度拡散層は、前記第2導電型低濃度拡散層および前記第2導電型中濃度拡散層に比べ、高濃度かつばらつきの少ない拡散層である請求項1記載の半導体装置。
- 前記ソース拡散層を覆うように配置された、前記ゲート酸化膜下に達する電界緩和用の第2の第2導電型低濃度拡散層と、
前記電界緩和用の第2の第2導電型低濃度拡散層の中に配置された第2の第2導電型中濃度拡散層と、
前記第2の第2導電型中濃度拡散層の中に配置された第2の第2導電型高濃度拡散層と、
をさらに有する請求項1または2記載の半導体装置。 - 第1導電型半導体基板と、
前記基板上にゲート酸化膜を介し設けられたゲート電極と、
前記ゲート電極の両側の前記基板上に設けられた第2導電型のソース拡散層およびLOCOS酸化膜を介して設けられたドレイン拡散層と、
前記ドレイン拡散層を覆うように配置された、前記ゲート酸化膜下に達する電界緩和用の第2導電型低濃度拡散層と、
前記電界緩和用の第2導電型低濃度拡散層の中に、前記LOCOS酸化膜の直下において、前記電界緩和用の第2導電型低濃度拡散層の境界から前記ドレイン拡散層に向かう方向に離れて配置された第2導電型中濃度拡散層と、
前記第2導電型中濃度拡散層の中に、前記LOCOS酸化膜の直下において、前記第2導電型中濃度拡散層の境界から前記ドレイン拡散層に向かう方向に離れて配置された第2導電型高濃度拡散層と、
を有する半導体装置。 - 前記電界緩和用の第2導電型低濃度拡散層は、前記LOCOS酸化膜の下にのみ配置されている請求項4記載の半導体装置。
- 第1導電型の半導体基板と、前記半導体基板上にゲート酸化膜を介し設けられたゲート電極と、前記ゲート電極の両側の前記半導体基板上に設けられた第2導電型のソース拡散層とドレイン拡散層と、前記ドレイン拡散層を覆うように配置された、前記ゲート酸化膜下に達する電界緩和用の第2導電型低濃度拡散層と、前記電界緩和用の第2導電型低濃度拡散層の中に配置された第2導電型中濃度拡散層と、前記第2導電型中濃度拡散層の中に配置された第2導電型高濃度拡散層と、を有する半導体装置の製造方法であって、
前記第2導電型低濃度拡散層となる領域をイオン注入により形成する工程と、
前記第2導電型低濃度拡散層となる領域の内側に、前記半導体基板の表面において、前記第2導電型低濃度拡散層となる領域の境界から前記ドレイン拡散層に向かう方向に離れて、前記第2導電型中濃度拡散層となる領域をイオン注入により形成する工程と、
前記第2導電型低濃度拡散層および前記第2導電型中濃度拡散層を熱拡散により形成する工程と、
前記第2導電型中濃度拡散層の内側に、前記半導体基板の表面に置いて、前記第2導電型中濃度拡散層の境界から前記ドレイン拡散層に向かう方向に離れて、前記第2導電型高濃度拡散層をイオン注入により形成する工程と、
前記第2導電型高濃度拡散層をイオン注入により形成した後に、前記第2導電型低濃度拡散層、前記第2導電型中濃度拡散層、及び前記第2導電型高濃度拡散層の上にLOCOS酸化膜を形成する工程と、
を有する半導体装置の製造方法。
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