CN107204370A - 半导体装置和半导体装置的制造方法 - Google Patents

半导体装置和半导体装置的制造方法 Download PDF

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CN107204370A
CN107204370A CN201710152563.6A CN201710152563A CN107204370A CN 107204370 A CN107204370 A CN 107204370A CN 201710152563 A CN201710152563 A CN 201710152563A CN 107204370 A CN107204370 A CN 107204370A
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diffusion layer
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concentration diffusion
semiconductor device
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CN107204370B (zh
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长尾佳介
森田健士
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Seiko Instruments Inc
Ablic Inc
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Abstract

本发明提供半导体装置和半导体装置的制造方法。该半导体装置形成有以覆盖漏扩散层(107)的方式到达栅氧化膜下的电场缓和用的第2导电型低浓度扩散层(101)，其特征在于，在所述电场缓和用的第2导电型低浓度扩散层(101)中配置第2导电型中浓度扩散层(102)，而且，通过尽可能地抑制热处理而将高浓度且结构变动小的第2导电型高浓度扩散层(103)配置在所述第2导电型中浓度扩散层中。

Description

半导体装置和半导体装置的制造方法
技术领域
本发明涉及半导体装置，特别涉及高耐压规格的半导体装置的结构。
背景技术
近年来，在高耐压的半导体装置中推行缩小面积，实际使用电压和耐压的容限(margin)减小。特别是，被配置成栅始终截止的截止晶体管这样的ESD保护元件的耐压需要被设定得比最大动作电压高且比内部元件的耐压低，但是，难以在减小容限的同时实现期望的耐压。
此外，为了确保可靠性，ESD保护元件还需要具有高的ESD耐性，即，即使电阻低而流过大量的电流也不会毁坏。为了获得高的ESD耐性，增加作为晶体管的沟道宽度的W长度是能够容易获得的对策之一，但却导致面积增大，成为成本上升的主要原因。
图9示出这种改善方案的一例。在本例中，为了减小由P型衬底100和漏的低浓度扩散层101构成的决定耐压的漏侧的P/N结附近的杂质浓度，增加漏扩散层107附近的杂质浓度，以如下方式进行了研究：通过在晶体管的漏扩散层107周围设置第2导电型中浓度扩散层102并配置双层的扩散区域而成为高耐压且低导通电阻(例如，参照专利文献1)。
一般，如果将高浓度的扩散层配置在沟道附近，则沟道端处的电场增大，耐压下降，因此，为了实现高耐压化，需要以远离沟道的方式来配置高浓度的扩散层。这是因为：连接晶体管的源和漏的L方向上的长度增加，因此，其结果导致面积增大。
专利文献1：日本特开2007-266473号公报
在作为改善方案的一例而举出的、将具有双扩散层的晶体管用作为截止晶体管的情况下，需要调节扩散层的结构以使得处于期望的耐压范围。虽然会对耐压产生影响的是沟道与高浓度的扩散层的距离、以及从高浓度的扩散层的沟道方向的端部至接触部(contact)的距离，但是，由于耐压会相对于扩散层的结构或工艺的较小的变化而敏感地发生变化，因此，难以制造出具有容限并能够保护内部元件的ESD保护元件。
发明内容
因此，本发明的课题是提供在不增加沟道宽度的情况下具有足够的耐压和ESD耐性的半导体装置。
为了解决上述课题，本发明如下所述地构成半导体装置。
半导体装置形成有如下部分：第1导电型半导体衬底；隔着栅氧化膜设置在所述半导体衬底上的栅电极；设置在所述栅电极的两侧的所述半导体衬底上的第2导电型的源扩散层和漏扩散层；以及以覆盖所述漏扩散层的方式到达所述栅氧化膜下的电场缓和用的第2导电型低浓度扩散层，其特征在于，在所述电场缓和用的第2导电型低浓度扩散层中配置第2导电型中浓度扩散层，而且，通过尽可能地抑制热处理而将高浓度且结构变动小的第2导电型高浓度扩散层配置在所述第2导电型中浓度扩散层中。
发明效果
通过使用上述手段，能够从沟道起朝向漏扩散层阶段性地赋予浓度梯度，因此，相比于现有技术，能够减小沟道附近的杂质浓度，增加漏扩散层附近的杂质浓度。因此，能够缓和沟道附近的电场，实现高耐压化，并且，能够减小漏扩散层附近的电阻，获得高的ESD耐性。
此外，杂质浓度高的区域集中在漏扩散层附近而在耐压方面产生富余，因此，能够缩短电场缓和层在L长度方向上的长度。同时，伴随着漏区附近的低电阻化而在ESD耐性方面产生富余，因此，能够缩短以往需要增加的作为晶体管的沟道宽度的W方向上的长度。因此，能够缩小晶体管的面积。
而且，由于电场缓和用的第2导电型高浓度扩散层的热处理少，因此，能够抑制由于扩散导致的结构的变动，能够实现在耐压方面具有容限的截止晶体管的设计。
附图说明
图1是示出作为本发明的半导体装置的第1实施例的N型MOS晶体管的示意性的剖视图。
图2是示出作为本发明的半导体装置的第2实施例的P型MOS晶体管的示意性的剖视图。
图3是示出作为本发明的半导体装置的第3实施例的N型MOS晶体管的示意性的剖视图。
图4是示出作为本发明的半导体装置的第4实施例的N型MOS晶体管的示意性的剖视图。
图5的(a)是示出作为本发明的半导体装置的第1实施例的N型MOS晶体管的制造过程的示意性的剖视图，图5的(b)是示出作为本发明的半导体装置的第1实施例的N型MOS晶体管的、与图5的(a)接续的制造过程的示意性的剖视图。
图6的(a)是示出作为本发明的半导体装置的第1实施例的N型MOS晶体管的、与图5的(b)接续的制造过程的示意性的剖视图，图6的(b)是示出作为本发明的半导体装置的第1实施例的N型MOS晶体管的、与图6的(a)接续的制造过程的示意性的剖视图。
图7的(a)是示出作为本发明的半导体装置的第1实施例的N型MOS晶体管的、与图6的(b)接续的制造过程的示意性的剖视图，图7的(b)是示出作为本发明的半导体装置的第1实施例的N型MOS晶体管的、与图7的(a)接续的制造过程的示意性的剖视图。
图8是示出作为本发明的半导体装置的第1实施例的N型MOS晶体管的、与图7的(b)接续的制造过程的示意性的剖视图。
图9是示出用现有的方法制造出的N型MOS晶体管的示例的示意性的剖视图。
附图说明
100：P型半导体衬底；
101：第2导电型低浓度扩散层；
102：第2导电型中浓度扩散层；
103：第2导电型高浓度扩散层；
104：LOCOS氧化膜；
105：栅电极；
106：源扩散层；
107：漏扩散层；
108：抗蚀剂膜；
101A：扩散之前的第2导电型低浓度扩散层；
102A：扩散之前的第2导电型中浓度扩散层；
200：N型半导体衬底(Nsub)；
201：第1导电型低浓度扩散层；
202：第1导电型中浓度扩散层；
203：第1导电型高浓度扩散层；
301：仅在LOCOS氧化膜下形成的第2导电型低浓度扩散层。
具体实施方式
在以下内容中，利用实施例，使用附图对实施发明的方式进行说明。
实施例1
图1是示出作为本发明的半导体装置的第1实施例的N型MOS晶体管的示意性的剖视图。
第1实施例的N型MOS晶体管是由如下部分构成的：第1导电型半导体衬底100；隔着栅氧化膜(未图示)配置在半导体衬底100上的栅电极105；配置在栅电极105的两侧的半导体衬底上的第2导电型的源扩散层106和隔着LOCOS氧化膜104配置的漏扩散层107；配置成以覆盖漏扩散层107的方式到达栅氧化膜下的电场缓和用的第2导电型低浓度扩散层101；配置在第2导电型低浓度扩散层101中的电场缓和用的第2导电型中浓度扩散层102；以及配置在第2导电型中浓度扩散层102中的电场缓和用的第2导电型高浓度扩散层103。源扩散层106和漏扩散层107是以高浓度的方式扩散杂质而形成的区域，通常作为供布线连接的区域使用。
附图中使用的N--、N-、N±、N+和P--、P-、P±、P+的符号表示所扩散的杂质的相对浓度的大小。即，N型的杂质的浓度以N--、N-、N±、N+的顺序增高，P型的杂质的浓度以P--、P-、P±、P+的顺序增高。
通过形成上述结构，能够从沟道起朝向漏扩散层阶段性地赋予浓度梯度，因此，相比于现有技术，能够减小沟道附近的杂质浓度，增加漏扩散层附近的杂质浓度。因此，能够缓和沟道附近的电场，实现高耐压化，并且，能够减小漏扩散层附近的电阻，实现高的ESD耐性。
此外，杂质浓度高的区域集中在漏扩散层附近而在耐压方面产生富余，因此，能够缩短电场缓和层在L长度方向上的长度。同时，伴随着漏附近的低电阻化而在ESD耐性方面产生富余，因此，能够缩短以往需要增大的作为晶体管的沟道宽度的W方向的长度。因此，能够缩小晶体管的面积。
接下来，对第1实施例的N型MOS晶体管的制造方法进行说明。图5的(a)至图8是示出第1实施例的N型MOS晶体管的制造工序的示意性的剖视图。
首先，如图5的(a)那样，例如将P型的半导体衬底100上形成的抗蚀剂膜108作为掩膜，离子注入N型杂质而形成N型区域101A。
接着，去除抗蚀剂膜108之后，如图5的(b)那样，以N型区域101A的内侧开口的方式附加抗蚀剂膜108，将其作为掩膜，离子注入N型杂质而形成N型区域102A。
接着，去除抗蚀剂膜108之后，通过使N型区域101A和N型区域102A扩散而如图6的(a)那样形成N型低浓度扩散层101和N型中浓度扩散层102。
接着，如图6的(b)那样，以N型中浓度扩散层102的内侧开口的方式附加抗蚀剂膜108，将其作为掩膜，离子注入N型杂质而形成N型高浓度扩散层103。还作为阱被利用的N型低浓度扩散层101、N型中浓度扩散层102大范围地扩散而浓度也变小。与之相对，在N型高浓度扩散层103，由于不施加用于阱的扩散的高温及长时间的热处理，因此，能够减少由于热处理导致的变动(ばらつき)，高浓度地形成扩散层。MOS晶体管的耐压会根据该N型高浓度扩散层103与沟道的距离以及从N型高浓度扩散层103的端部至位于漏扩散层107的接触部的距离而大幅变化，因此，在制造与内部元件之间的耐压容限小的截止晶体管时，配置结构变动小的N型高浓度扩散层103是特别有效的。
接着，去除抗蚀剂膜108之后，在源、漏扩散层和成为沟道的部分形成作为氧化防止膜的氮化膜，之后使衬底表面氧化，由此，如图7的(a)那样形成LOCOS氧化膜104。
接着，在形成栅氧化膜(未图示)之后，如图7的(b)那样，在成为沟道的部分以及与沟道相接的LOCOS氧化膜104上以重叠的方式形成栅电极105。
接着，如图8那样，将LOCOS氧化膜104和栅电极105利用为掩膜来形成源扩散层106、漏扩散层107。
以下，虽省略图示的说明，但在栅电极105、源扩散层106、漏扩散层107通过层间绝缘膜层而形成接触部，并形成金属布线和钝化膜，由此完成半导体装置。
根据上述说明的制造工序可知：电场缓和用的第2导电型高浓度扩散层的热处理少，因此，能够抑制由于扩散导致的结构的变动，能够实现在耐压方面具有容限的截止晶体管的设计。
实施例2
图2是示出作为本发明的半导体装置的第2实施例的P型MOS晶体管的示意性的剖视图。通过调换实施例1的衬底和被扩散的杂质的极性来制造P型MOS晶体管。
P型MOS晶体管是由如下部分构成的：第2导电型半导体衬底200；隔着栅氧化膜(未图示)配置在半导体衬底200上的栅电极105；配置在栅电极105的两侧的半导体衬底上的第1导电型的源扩散层206和隔着LOCOS氧化膜104配置的漏扩散层207；配置成以覆盖漏扩散层207的方式到达栅氧化膜下的电场缓和用的第1导电型低浓度扩散层201；配置在第1导电型低浓度扩散层201中的电场缓和用的第1导电型中浓度扩散层202；以及配置在第1导电型中浓度扩散层202中的电场缓和用的第1导电型高浓度扩散层203。
实施例3
图3是示出作为本发明的半导体装置的第3实施例的N型MOS晶体管的示意性的剖视图。通过在源扩散层侧也形成实施例1的位于漏扩散层侧的电场缓和用的第2导电型低浓度扩散层101、配置在第2导电型低浓度扩散层101中的电场缓和用的第2导电型中浓度扩散层102、以及配置在第2导电型中浓度扩散层102中的电场缓和用的第2导电型高浓度扩散层103和LOCOS氧化膜104，从而制作出N型MOS晶体管。
虽然使用该制作方法会增加元件面积，但是，即使调换源和漏的电位也能够获得与实施例1同样地工作的半导体装置。
实施例4
图4是示出作为本发明的半导体装置的第4实施例的N型MOS晶体管的示意性的剖视图。
第4实施例的N型MOS晶体管是由如下部分构成的：第1导电型半导体衬底100；隔着栅氧化膜(未图示)配置在半导体衬底100上的栅电极105；配置在栅电极105的两侧的衬底上的第2导电型的源扩散层106和隔着LOCOS氧化膜104而配置的漏扩散层107；与漏扩散层107相接并到达栅氧化膜下的电场缓和用的第2导电型低浓度扩散层301；以从漏扩散层107与沟道之间起覆盖漏扩散层107的方式配置的第2导电型中浓度扩散层102；以及配置在第2导电型中浓度扩散层102中的第2导电型高浓度扩散层103。
该第2导电型低浓度扩散层301是通过如下方式制造的：在形成LOCOS氧化膜104时，将作为氧化防止膜配置在源、漏区和沟道的氮化膜作为掩膜，仅在LOCOS氧化膜104下加入杂质。
在上述制造方法中，在低浓度扩散层的形成中将氮化膜用作为掩膜，因此，能够削减在形成实施例1中使用的第2导电型低浓度扩散层101时所需的掩膜。

Claims (6)

1.一种半导体装置，其中，所述半导体装置具有：
第1导电型的半导体衬底；
隔着栅氧化膜设置在所述半导体衬底上的栅电极；
设置在所述栅电极的两侧的所述半导体衬底上的第2导电型的源扩散层和漏扩散层；
被配置成覆盖所述漏扩散层且到达所述栅氧化膜下的电场缓和用的第2导电型低浓度扩散层；
配置在所述电场缓和用的第2导电型低浓度扩散层中的第2导电型中浓度扩散层；以及
配置在所述第2导电型中浓度扩散层中的第2导电型高浓度扩散层。
2.根据权利要求1所述的半导体装置，其中，
所述第2导电型高浓度扩散区域是与所述第2导电型低浓度扩散区域和所述第2导电型中浓度扩散区域相比浓度高且变动小的扩散区域。
3.根据权利要求1或2所述的半导体装置，其中，
所述半导体装置还具有：
被配置成覆盖所述源扩散层且到达所述栅氧化膜下的电场缓和用的第2个第2导电型低浓度扩散层；
配置在所述电场缓和用的第2个第2导电型低浓度扩散层中的第2个第2导电型中浓度扩散层；以及
配置在所述第2个第2导电型中浓度扩散层中的第2个第2导电型高浓度扩散层。
4.一种半导体装置，其中，
所述半导体装置具有：
第1导电型半导体衬底；
隔着栅氧化膜设置在所述衬底上的栅电极；
设置在所述栅电极的两侧的所述衬底上的第2导电型的源扩散层和隔着LOCOS氧化膜设置的漏扩散层；
与所述漏扩散层相接且到达所述栅氧化膜下的电场缓和用的第2导电型低浓度扩散层；
以从所述漏扩散层与沟道之间起覆盖所述漏扩散层的方式配置的第2导电型中浓度扩散层；以及
配置在所述第2导电型中浓度扩散层中的第2导电型高浓度扩散层。
5.根据权利要求4所述的半导体装置，其中，
所述电场缓和用的第2导电型低浓度扩散层仅配置在所述LOCOS氧化膜下。
6.一种半导体装置的制造方法，其特征在于，
所述半导体装置具有：第1导电型的半导体衬底；隔着栅氧化膜设置在所述半导体衬底上的栅电极；设置在所述栅电极的两侧的所述半导体衬底上的第2导电型的源扩散层和漏扩散层；被配置成覆盖所述漏扩散层且到达所述栅氧化膜下的电场缓和用的第2导电型低浓度扩散层；配置在所述电场缓和用的第2导电型低浓度扩散层中的第2导电型中浓度扩散层；以及配置在所述第2导电型中浓度扩散层中的第2导电型高浓度扩散层，
所述半导体装置的制造方法具有：
形成所述第2导电型低浓度扩散层和所述第2导电型中浓度扩散层的工序；和
形成所述第2导电型高浓度扩散层的工序，
将形成所述第2导电型高浓度扩散层的工序设置在形成所述第2导电型低浓度扩散层和所述第2导电型中浓度扩散层的工序之后。
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