JP4663028B2 - 埋設導電層を備えた高電圧トランジスタを製造する方法 - Google Patents
埋設導電層を備えた高電圧トランジスタを製造する方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims description 24
- 230000000295 complement effect Effects 0.000 claims description 11
- 238000002513 implantation Methods 0.000 claims description 9
- 239000002019 doping agent Substances 0.000 claims description 8
- 230000005669 field effect Effects 0.000 claims description 8
- 239000007943 implant Substances 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 239000000969 carrier Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 description 38
- 230000015556 catabolic process Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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Description
相補形CMOS装置を製造するための一般的なプロセスとの互換性があるP−チャンネルMOS装置の設計は、米国特許第5,894,154号に記載されている。
12 N−型ウエル領域
14、14a〜14c P−型埋設領域
16 P−型拡散領域
17 P−型拡散領域
18 P+ドレイン拡散領域
19 N+ソース拡散領域
20 N+拡散領域
22 ゲート
23 ポリシリコン電界板部材
28 ドレイン電極
29 ソース電極
30 ゲート絶縁層
31 IGEFTチャンネル領域
52 N−ウエル
69 P+領域
70 N+領域
74 埋設層
80 ゲート酸化物領域
Claims (20)
- 第1の導電型の基板に高電圧トランジスタを製造する方法であって、
基板に第2の導電型のウエル領域を形成する段階と、
前記ウエル領域内の第1の位置に第1の導電型の第1のドレイン領域を形成し、
前記ウエル領域内の第2の位置に第1の導電型の第2のドレイン領域を、前記第1の位置が該第2の位置から隔置されるように形成する段階と、
前記第1のドレイン領域から分離された前記ウエル領域内の第3の位置に第1の導電型のソース領域を形成する段階であって、前記第2の位置、前記第1の位置、前記第3の位置がこの順序で前記ウエル領域内に配置される前記段階と、
第1の導電型のドーパントを高エネルギー打込みで前記ウエル領域に打ち込み、前記第1の位置と前記第2の位置とを接続して前記高電圧トランジスタがオン状態のときに前記第1の位置と前記第2の位置との間に電流が流れるような導電路を与える第1の埋設層を形成する段階であって、
該第1の埋設層が前記ウエル領域の一部分の下方に埋め込まれるように、前記高エネルギー打込みのエネルギーを十分高くし、前記一部分は第2の導電型の前記ウエル領域の残りの部分と同じドーピング・レベルを有する前記段階と、
前記第3の位置から前記第1の位置に延びる絶縁ゲートを形成する段階と、
を含む前記方法。 - 請求項1記載の方法であって、第1の導電型はP型であり、第2の導電型はN型である前記方法。
- 請求項2記載の方法であって、ドーパントはホウ素である前記方法。
- 請求項1記載の方法であって、さらに、
1またはそれ以上の追加の埋設層を高エネルギー打込みで形成する段階を含み、該1またはそれ以上の追加の埋設層は、それぞれ第1の埋設層と平行に配置され、かつ、前記ウエル領域内で異なる深さに配置され、前記追加の埋設層は前記高電圧トランジスタがオン状態のときに前記第1の位置と前記第2の位置との間に電流が流れるような追加の導電路を与え、前記追加の埋設層は第2の導電型の前記ウエル領域の一部分によって分離され、該一部分は第2の導電型の前記ウエル領域の残りの部分と同じドーピング・レベルを有する前記段階を含む前記方法。 - 請求項4記載の方法であって、1またはそれ以上の前記追加の埋設層は、それぞれ第1および第2の位置に接続される前記方法。
- 請求項1記載の方法であって、前記第1のドレイン領域、前記第1の埋設層および前記ウエル領域は、前記高電圧トランジスタがオフ状態で、前記第1のドレイン領域、前記第1の埋設層および前記ウエル領域の自由キャリアが相互に空乏化するように選択されたドーピング・レベルを有する前記方法。
- 高電圧トランジスタを製造する方法であって、
基板に第2の導電型のウェル領域を形成する段階と、
第1の導電型の第1のドレイン領域を前記基板の前記ウェル領域の第1の位置に形成する段階と、
第1の導電型の第2のドレイン領域を、前記ウェル領域の第2の位置に、前記第1のドレイン領域が該第2のドレイン領域から隔置されるように打ち込みで形成する段階と、
第1の導電型のソース領域を、前記第1のドレイン領域から隔置された前記基板の前記ウェル領域の第3の位置に、前記第2のドレイン領域を形成するのと同一の打ち込みで形成する段階であって、前記第2の位置、前記第1の位置、前記第3の位置がこの順序で配置される前記段階と、
第1の導電型のドーパントを高エネルギー打込みで前記基板の前記ウェル領域に打ち込み、前記第1の位置と前記第2の位置とを接続して前記高電圧トランジスタがオン状態のときに前記第1の位置と前記第2の位置との間に電流が流れるような導電路を与える第1の埋設層を形成する段階であって、該第1の埋設層が前記ウェル領域の一部分の下方に埋め込まれるように、前記高エネルギー打込みのエネルギーを十分高くし、前記一部分は第2の導電型の前記ウェル領域の残りの部分と同じドーピング・レベルを有する前記段階と、
前記ソース領域から前記第1のドレイン領域に延びる絶縁ゲートを形成する段階と、
を含む前記方法。 - 請求項7記載の方法であって、さらに、前記ソース領域および前記第2のドレイン領域にそれぞれ接続されたソース電極およびドレイン電極を形成する段階を含む前記方法。
- 請求項8記載の方法であって、前記ソース電極は、前記絶縁ゲートを覆って延びる部分を含む前記方法。
- 請求項7記載の方法であって、第1の導電型はP型であり、第2の導電型はN型である前記方法。
- 請求項7記載の方法であって、さらに、
1またはそれ以上の追加の埋設層を形成する段階を含み、1またはそれ以上の追加の埋設層は、それぞれ前記埋設層と平行に配置され、かつ、前記ウェル領域内で異なる深さで配置され、前記追加の埋設層は前記高電圧トランジスタがオン状態のときに前記第1の位置と前記第2の位置との間に電流が流れるような追加の導電路を与え、前記追加の埋設層は第2の導電型の前記基板の一部分によって分離され、該一部分は第2の導電型の前記ウェル領域の残りの部分と同じドーピング・レベルを有する前記段階を含む前記方法。 - 請求項11記載の方法であって、1またはそれ以上の追加の埋設層は、それぞれ、前記第1および第2のドレイン領域の位置に接続される前記方法。
- 請求項7記載の方法であって、前記第1のドレイン領域は、前記ソース領域と前記第2のドレイン領域の間に配置される前記方法。
- 請求項7記載の方法であって、前記第1のドレイン領域、前記第1の埋設層および前記ウエル領域は、前記高電圧トランジスタがオフ状態で、前記第1のドレイン領域、前記第1の埋設層および前記基板の自由キャリアが相互に空乏化するようなドーピング・レベルを有する前記方法。
- 第1の導電型の基板に高電圧電界効果トランジスタ(HVFET)を製造する方法において、
基板に第1の導電型と反対の第2の導電型のウエルを形成する段階と、
第1の導電型のドーパントを高エネルギー打込みで前記ウエルに打ち込み、前記ウエル内に第1の導電型の横方向に延びた埋設層領域を形成する段階であって、該埋設層領域が前記第2の導電型のウエルの一部分の下方に埋め込まれるように、前記高エネルギー打込みのエネルギーを十分高くし、前記一部分は第2の導電型の前記ウエルの残りの部分と同じドーピング・レベルを有する前記段階と、
前記ウエルの上方に絶縁ゲートを形成する段階と、
前記ウエル内の第1の位置に第1の導電型の第1のドレイン領域を形成する段階と、
前記ウエル内の前記第1の位置から隔置された第3の位置に第1の導電型のソース領域を形成する段階と、
前記第1の位置と隔置され、かつ前記第1の位置と前記第3の位置の間の第2の位置に第1の導電型の第2のドレイン領域を形成し、絶縁ゲートの下方の前記第2の位置と該第3の位置との間で前記ウエル内にチャンネル領域を定める段階と、
を含み、前記第1および第2のドレイン領域は、前記ウエル内を垂直方向下方に延びて前記埋設層領域と接触することにより、前記埋設層領域がHVFETがオン状態のときに電流が横方向に流れるような導通路を与える前記方法。 - 請求項15記載の方法において、第1の導電型はP型であり、ドーパントはホウ素からなる前記方法。
- 請求項15記載の方法において、前記埋設層領域は、前記ウエル内で異なる深さに配置された複数の並列の隔置された埋設層を含む前記方法。
- 請求項15記載の方法において、前記ウエル内に前記埋設層領域を形成するために前記ドーパントを打ち込むことにより、基板内に配置された相補型HVFETの第1の導電型の別の埋設層領域も形成する前記方法。
- 請求項15記載の方法において、さらに、
前記第1のドレイン領域に接続されたドレイン電極を形成する段階と、
前記ソース領域に接続されたソース電極を形成する段階と、
を含む前記方法。 - 請求項15記載の方法において、第1の導電型はP型であり、第2の導電型はN型であり、第1のドレイン領域を形成する段階は、
前記ドレイン電極に接続されたP+領域を形成する段階と、
該P+領域から埋設層領域に下方に延びる追加のP型領域を形成する段階と、
をさらに含む前記方法。
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Also Published As
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JP4512459B2 (ja) | 2010-07-28 |
EP1524701A2 (en) | 2005-04-20 |
JP2006019759A (ja) | 2006-01-19 |
EP1521298A3 (en) | 2008-07-09 |
US20020153560A1 (en) | 2002-10-24 |
US6563171B2 (en) | 2003-05-13 |
US20030062548A1 (en) | 2003-04-03 |
JP2010103557A (ja) | 2010-05-06 |
JP2005026711A (ja) | 2005-01-27 |
US20020153561A1 (en) | 2002-10-24 |
US6818490B2 (en) | 2004-11-16 |
EP1227523A2 (en) | 2002-07-31 |
JP2002319675A (ja) | 2002-10-31 |
US20040036115A1 (en) | 2004-02-26 |
EP1227523A3 (en) | 2008-07-09 |
JP2005026710A (ja) | 2005-01-27 |
EP1524701A3 (en) | 2008-07-09 |
JP4512534B2 (ja) | 2010-07-28 |
US6504209B2 (en) | 2003-01-07 |
US20030178646A1 (en) | 2003-09-25 |
EP1521298A2 (en) | 2005-04-06 |
US20020096691A1 (en) | 2002-07-25 |
US6424007B1 (en) | 2002-07-23 |
US6465291B1 (en) | 2002-10-15 |
US6730585B2 (en) | 2004-05-04 |
JP4512460B2 (ja) | 2010-07-28 |
US6501130B2 (en) | 2002-12-31 |
US20020149052A1 (en) | 2002-10-17 |
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