US20090085148A1 - Multi-directional trenching of a plurality of dies in manufacturing superjunction devices - Google Patents

Multi-directional trenching of a plurality of dies in manufacturing superjunction devices Download PDF

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US20090085148A1
US20090085148A1 US12/031,909 US3190908A US2009085148A1 US 20090085148 A1 US20090085148 A1 US 20090085148A1 US 3190908 A US3190908 A US 3190908A US 2009085148 A1 US2009085148 A1 US 2009085148A1
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trenches
plurality
dies
orientation
die
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Takeshi Ishiguro
Kenji Sugiura
Hugh J. Griffin
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Icemos Tech Ltd
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ICEMOS Tech Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures

Abstract

A method of manufacturing a superjunction device includes providing a semiconductor wafer having a plurality of dies. A first plurality of trenches having a first orientation are formed in a first die. A second plurality of trenches having a second orientation are formed in a second die. The second orientation is different from the first orientation.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This Application claims priority to U.S. Provisional Patent Application No. 60/975,878, filed on Sep. 28, 2007, entitled “Multi-Directional Trenching in Manufacturing Superjunction Devices.”
  • BACKGROUND OF THE INVENTION
  • An embodiment of the present invention relates generally to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a superjunction device with a first plurality of trenches having one orientation and a second plurality of trenches having a second orientation different than the first orientation.
  • Semiconductor wafer manufacture generally refers to the process of making integrated circuits on silicon wafers. A typical semiconductor wafer is generally circular in plan view. Individual electronic circuits or devices are formed across at least one surface of the wafer and then the wafer is typically cut (sawed or diced) into a plurality of individual “dies” for packaging into individual integrated circuits (ICs).
  • Since the invention of superjunction devices by Dr. Xingbi Chen, as disclosed in U.S. Pat. No. 5,216,275, the contents of which are incorporated by reference herein, there have been many attempts to expand and improve on the superjunction effect of his invention. U.S. Pat. Nos. 6,410,958, 6,300,171 and 6,307,246 are examples of such efforts and are incorporated herein by reference.
  • Trench type superjunction devices are expected to replace multi-epi superjunction devices because of the potential lower processing cost. FIG. 1A illustrates a top plan view of a wafer 10 used in the manufacturing of a plurality of trench-type superjunction devices or dies 20. FIG. 1B shows a magnified view of two dies 20 representative of the plurality of dies 20 located on the wafer 10. Each die 20 includes a plurality of trenches 22, each of the trenches 22 traversing the die 20 in a generally horizontal orientation. FIG. 1C shows an alternate configuration wherein the plurality of trenches 22 are each oriented generally vertically on the die 20. In each case, all of the trenches 22 on all of the dies 20 of the wafer 10 have the same orientation. FIG. 1D illustrates an enlarged partial cross-sectional view of a die 20 having a plurality of trenches 22 formed in a silicon layer 12 disposed on a substrate 11. A plurality of corresponding mesas 24 are thereby formed, each mesa 24 being capped by a layer of oxide 26. The trenches 22 are typically filled with a refill material 28.
  • Generally, the cost of semiconductor device manufacturing has been reduced by condensing the design rules (recommended parameters) and enlarging the diameter of the process wafer. The design rules reduction may be applied to trench-type superjunction technology, as described in co-pending {Inser 35UI1 Ap No. when filed}. However, conventional trenching methods tend to cause wafer bowing and warping. Such deformations are especially prevalent when trenching large diameter wafers (e.g., greater than about six inches). Once bowing and warping occurs, a wafer typically can no longer be processed effectively, if at all. Further, even if the wafer remains capable of processing, there is a higher risk of chipping or breakage. The degree of bowing and/or warping is greater when using deep trenching, such as the type of deep trenching used, for example, in the formation of superjunction devices. Thus, the use of conventional trenching methods for manufacturing superjunction devices does not permit the cost reduction achieved by increasing the diameter of the wafer.
  • It is desirable to provide a method of manufacturing trench-type superjunction devices that minimizes and/or eliminates the effects of bowing and warping. It is further desirable to provide a method of manufacturing trench-type superjunction devices that reduces manufacturing costs by enabling the use of larger wafer diameters.
  • BRIEF SUMMARY OF THE INVENTION
  • Briefly stated, embodiments of the present invention comprise a method of manufacturing a superjunction device. One embodiment of the method includes providing a semiconductor wafer having a plurality of dies. The method further includes forming a first plurality of trenches in at least one first die, each of the first plurality of trenches having a first orientation. The method also includes forming a second plurality of trenches in at least one second die, each of the second plurality of trenches having a second orientation that is different from the first orientation.
  • Embodiments of the present invention also comprise superjunction devices. In one embodiment, the superjunction device includes a semiconductor wafer having a plurality of dies. A first plurality of trenches are formed in a first plurality of dies. Each of the first plurality of trenches has a first orientation. A second plurality of trenches is formed in a second plurality of dies. Each of the second plurality of trenches has a second orientation that is different from the first orientation.
  • Yet another embodiment of the present invention comprises other types of semiconductor devices formed on or in a semiconductor wafer. The semiconductor wafer includes a plurality of dies. A first plurality of trenches are formed in a first plurality of dies. Each of the first plurality of trenches has a first orientation. A second plurality of trenches is formed in a second plurality of dies. Each of the second plurality of trenches has a second orientation that is different from the first orientation.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The foregoing summary, as well as the following detailed description of preferred embodiments of the invention, will be better understood when read in conjunction with the appended drawings. For the purpose of illustration, there are shown in the drawings embodiments which are presently preferred. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown.
  • FIG. 1A is a top plan view of a prior art semiconductor wafer having a plurality of dies formed thereon;
  • FIG. 1B is a greatly enlarged top plan view of two adjacent dies from the prior art wafer of FIG. 1A;
  • FIG. 1C is a greatly enlarged top plan view of two alternate adjacent dies from the prior art wafer of FIG. 1A;
  • FIG. 1D is an enlarged partial cross-sectional elevational view of one of the dies from either of FIGS. 1B or 1C;
  • FIGS. 2A-2C are greatly enlarged top plan views of dies manufactured in accordance with preferred embodiments of the present invention;
  • FIGS. 3A and 3B are greatly enlarged top plan views of adjacent dies on a wafer manufactured in accordance with preferred embodiments of the present invention;
  • FIG. 4A is an enlarged cross-sectional elevational view of a portion of a die after an oxide layer is disposed on a silicon layer in accordance with a preferred embodiment;
  • FIG. 4B is an enlarged cross-sectional elevational view of a portion of the die of FIG. 4A after trenches are formed thereon in accordance with a preferred embodiment; and
  • FIG. 4C is an enlarged cross-sectional elevational view of a portion of the die of FIG. 4B after the trenches are filled with a refill material in accordance with a preferred embodiment.
  • DETAILED DESCRIPTION OF THE INVENTION
  • Certain terminology is used in the following description for convenience only and is not limiting. The words “right”, “left”, “lower”, and “upper” designate directions in the drawings to which reference is made. The words “inwardly” and “outwardly” refer to directions toward and away from, respectively, the geometric center of the device and designated parts thereof. The terminology includes the above-listed words, derivatives thereof, and words of similar import. Additionally, the words “a” and “an”, as used in the claims and in the corresponding portions of the specification, mean “at least one.”
  • As used herein, reference to conductivity will be limited to the embodiment described. However, those skilled in the art know that p-type conductivity can be switched with n-type conductivity and the device would still be functionally correct (i.e., a first or a second conductivity type). Therefore, where used herein, reference to n or p can also mean either n or p or p and n can be substituted therefor.
  • Furthermore, n+ and p+ refer to heavily doped n and p regions, respectively; n++ and p++ refer to very heavily doped n and p regions, respectively; n and p refer to lightly doped n and p regions, respectively; and n−− and p−− refer to very lightly doped n and p regions, respectively. However, such relative doping terms should not be construed as limiting.
  • Referring to the drawings in detail, wherein like reference numerals indicate like elements throughout, there is shown in FIG. 2A a top plan view of an individual die 220 a manufactured in accordance with a preferred embodiment of the present invention. A plurality of trenches 222 a are formed on the die 220 a, the trenches 222 a having a first orientation, depicted in FIG. 2A as being vertical. A further plurality of trenches 223 a are also formed on the die 220 a, the trenches 223 a having a second orientation, depicted in FIG. 2A as being horizontal. In the embodiment depicted in FIG. 2A, the first and second trench orientations differ by approximately 90°, but the trenches 222 a, 223 a may be formed at other angles relative to one another, such as, for example, 45°. By utilizing more than one trench direction within the die 220 a, stress is reduced on the die 220 a and the overall wafer.
  • Embodiments of the present invention are not limited to the example illustrated in FIG. 2A. There is no restriction on orientations, angles, lengths, widths, and/or shapes of trenches 222 a, 223 a. There is also no restriction on the number of trenches 222 a, 223 a or combinations available on the die 220 a.
  • In preferred embodiments, an area occupied by trenches 222 a of one orientation should be generally equal in size to an area occupied by trenches 223 a of another orientation. Preferably, the trenches 222 a, 223 a are located on the die 220 a generally symmetrically. The configurations of the trenches 222 a, 223 a reduce the mechanical stress placed on the die 220 a and overall wafer to thereby reduce bowing or warping of the wafer. FIG. 2B illustrates a second embodiment of a die 220 b, including vertical trenches 222 b and horizontal trenches 223 b. Die 220 b maintains about a 1:1 area ratio (as described above) of trenches 222 b, 223 b despite the irregular configuration.
  • FIG. 2C illustrates a further embodiment of a die 220 c, which features a different type of trenching pattern. The die 220 c includes a plurality of trenches 222 c that are angled at about 45° from the horizontal direction and a plurality of trenches 223 c that are angled at about 135° from the horizontal direction. The trenches 222 c, 223 c are grouped with similarly oriented trenches to form square patterns on the die 220 c. FIG. 2C thus illustrates an example where the die 220 c may include trenches 222 c, 223 c of various lengths while continuing to maintain about a 1:1 area ratio convenient for minimizing stress on the wafer.
  • FIG. 3A illustrates an alternative embodiment of the present invention. The dies 320 a, 321 a shown are formed adjacent to one another on a wafer, such as the wafer 10 shown in FIG. 1A. In each die 320 a are formed a plurality of trenches 323 a oriented in a horizontal direction. In each die 321 a are formed a plurality of trenches 322 a oriented in a vertical direction. Unlike in the previous embodiments of FIGS. 2A-2C, each die 320 a, 321 a in FIG. 3A includes trenches 323 a, 322 a formed in only one orientation. The mechanical stress on the overall wafer is thereby reduced by, as shown in FIG. 3A, placing dies 320 a, 321 a having trenches 323 a, 322 a oriented in different directions adjacent to one another. Although the length of each of the trenches 322 a is greater than the length of each of the trenches 323 a, the number of trenches 323 a is greater than the number of trenches 322 a. As a result, the overall area covered by the trenches 322 a and 323 a are about the same. Particularly in FIG. 3A, a wafer would include a pattern of dies 320 a, 321 a wherein every other die 320 a, 321 a in both horizontal and vertical directions on the wafer would include identical trench orientations.
  • FIG. 3B depicts a configuration of the dies 320 b, 321 b as an alternative to that shown in FIG. 3A. Extrapolating the configuration of FIG. 3B over an entire wafer would result in a row (or column) of dies 320 b having horizontally oriented trenches 323 b, a row (or column) of dies 321 b having vertically oriented trenches 322 b, and so forth.
  • It is understood by those skilled in the art that orientations of the trenches 322, 323 in each die 320, 321 are not limited to the embodiments described above. The dies 320, 321 are also not limited to being rectangular in shape and may be designed in any manner convenient for use in superjunction devices, for example, square, rectangular, circular, polygonal, or the like.
  • Embodiments of the present invention may be employed not only in superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET) devices, but also in Schottky devices or any devices that require deep, refilled trenches, including microelectromechanical systems (MEMS).
  • Embodiments of the present invention, such as those shown in FIGS. 2A-2C and 3A-3B, allow for the manufacture of larger diameter semiconductor wafers having a bow of less than 100 microns. Preferably, the wafer bow is reduced to below 50 microns on, for example, an eight inch diameter wafer.
  • Referring to FIGS. 4A-4C, a process for manufacturing a superjunction device in accordance with embodiments of the present invention is described. FIG. 4A shows a partial cross-sectional elevational view of a die 420 as part of a wafer (not shown). The die 420 includes a semiconductor material layer 412 that may be doped as necessary. Preferably, the semiconductor material layer 412 is silicon. But, the semiconductor material layer 412 may be formed of other materials such as silicon carbide, gallium arsenide, germanium, or the like. In the example of FIGS. 4A-4C, the semiconductor material layer 412 is an n-type epitaxial silicon layer that is disposed on a heavily doped substrate layer 411. Although both layers 411, 412 are shown in FIG. 4A as having n-type conductivity, it is understood that one or both layers 411, 412 may instead have p-type conductivity. Other layers not shown may be included in the die 420 as required. A temporary layer used to handle the overall wafer may also be included.
  • An oxide or other dielectric layer 426 is disposed above the silicon layer 412. The oxide layer 426 is applied using one of thermal growth, low pressure (LP) chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), and deposition or some other process. The oxide layer 426 is preferably formed of an oxide. Alternatively, the oxide layer 426 may be a nitride, silicon-oxynitride, or other known dielectrics.
  • Known processing techniques such as grinding, polishing and etching may be performed to obtain a desired thicknesses of the substrate 411, silicon layer 412, oxide layer 426, and any additional layers. Generally, semiconductor wafers are coarsely thinned by a grinding machine having a rough grinding wheel or grinding pad such as a diamond or carbide wheel or pad having for example, diamond impregnated resin teeth. Grinding the wafer also allows for thinner, and therefore, smaller IC packages. Generally, polishing is a finer process using a wet silica-particle slurry which is washed across the surface of the wafer at a predetermined flow rate and is referred to as chemical mechanical polishing (CMP). Optionally, surfaces of the wafer are thinned by grinding and then polishing.
  • Referring to FIG. 4B, trenches 422 are formed in the die 420 through the oxide layer 426 and at least partially through the silicon layer 412, forming mesas 424. In the example of FIG. 4B the trenches 422 extend completely through the silicon layer 412 to the substrate 411, but the trenches 422 may extend to any desired depth. A photoresist patterning layer (not shown) may be disposed above the oxide layer 426 to provide a pattern for etching the trenches 422. Preferably, the trenches 422 are formed by utilizing known techniques such as plasma etching, reactive ion etching (RIE), sputter etching, vapor phase etching, chemical etching, deep RIE, or the like. Deep RIE technology permits deeper trenches 422 with straighter sidewalls. Furthermore, forming deeper trenches 422 that have straighter sidewalls than conventionally etched or formed trenches, in addition to other steps in the process, results in a final superjunction device with enhanced avalanche breakdown voltage (Vb) characteristics as compared to conventional semiconductor-transistor devices.
  • The sidewalls of each trench 422 can be smoothed, if needed, using, for example, one or more of the following process steps: (i) an isotropic plasma etch may be used to remove a thin layer of silicon (typically 100-1000 Angstroms) from the trench 422 surfaces or (ii) a sacrificial silicon dioxide layer may be grown on the surfaces of the trench 422 and then removed using an etch such as a buffered oxide etch or a diluted hydrofluoric (HF) acid etch. The use of the smoothing techniques can produce smooth trench 422 surfaces with rounded corners while removing residual stress and unwanted contaminates. However, where it is desirable to have vertical sidewalls and square corners, an anisotropic etch process may be used instead of the isotropic etch process discussed above. Anisotropic etching, in contrast to isotropic etching, generally means different etch rates in different directions in the material being etched.
  • The trenches 422 shown in FIG. 4B are formed in accordance with embodiments of the present invention described above. That is, sets of trenches 422 are formed having differing orientations on an individual die 420, or alternatively, trenches 422 formed on one die 420 have a different orientation than trenches 422 formed on an adjacent die 420.
  • The sidewalls of the trenches 422 are subsequently implanted or doped with a p-dopant such as boron (P) using any techniques known in the art. However, in some cases n-type doping may be required for the mesas 424 prior to the p-type doping of the trench 422 sidewalls. Preferably, the implants are performed without benefits of a masking step, e.g., at an implantation angle Φ (not shown) determined by the width and the depth of the trenches 422, at a high energy level in the range of about 40 Kilo-electron-volts (KeV) to several Mega-eV. Preferably, the energy level is in the range of about 200 KeV to 1 MeV, but it should be recognized that the energy level should be selected to sufficiently implant the dopant. The use of the predetermined implantation angle Θ ensures that only the sidewalls and not the bottoms of the trenches 422 are implanted.
  • In the manufacture of prior art devices, the implantation angle Θ is typically between 2° and 12°. The wafer is also oriented at one, or often two “twist angles,” i.e., the relative orientation of the wafer in a plane defined by the wafer with respect to the ion beam. The most common angles are 0° and 180°. In accordance with preferred embodiments however, more twist angles may be required, for example, the wafer may be oriented at 45°, 135°, 225°, and 315° during processing. The twist angles required for ion implantation are often governed by restrictions imposed by the manufacturing apparatus. Therefore, embodiments of the present invention are in no way limited to the values or number of twist angles described above.
  • Following implanting the p-type implant on the sidewalls of the trenches 422, a drive-in step (i.e., a diffusion) is performed using any known techniques to create p-type doped regions (see FIG. 4C) proximate the sidewalls of the trenches 422. Preferably, a temperature and a time period for the drive-in step are selected to sufficiently drive in the implanted dopant into the mesas 424. For example, for p-type doping, the drive-in step (i.e., a diffusion) may be performed at a temperature of about 1150-1200° Celsius for about 1-2 hours. Alternatively, for n-type doping, the drive in step may be performed at a temperature of up to about 1200° C. for up to about 24 hours.
  • An optional oxidation step, usually performed in a steam or oxygen ambient, can also be performed with or subsequent to the drive-in step, which forms a silicon dioxide layer (not shown) on the sidewalls and the bottoms of the trenches 422. A thin layer of silicon nitride (not shown) can also be deposited on the sidewalls and the bottoms of the trenches 422. Deposition of silicon nitride on thermally oxidized silicon wafers does not influence the fundamental properties of the Si—SiO2 interface. The existence of silicon nitride makes surface potential stable or unstable according to the structures, partly due to the existence of hydrogen in silicon nitride. Hydrogen can influence electric properties. The layer of silicon nitride also serves the function to isolate and protect the silicon and silicon oxide from a refill material to be deposited in trenches 422.
  • The lining of the trenches 422 with silicon nitride can be performed in general by CVD (thermal or plasma). The lining of the trenches 422 with silicon dioxide can be performed in general by CVD (thermal, plasma, or spun-on-glass (SOG)). The lining of the trenches 422 with silicon dioxide and/or silicon nitride can preferably be performed using application of tetraethylorthosilicate (TEOS) because of the better conformity achieved by TEOS. Preferably, the silicon nitride is about 100 Å to about 10,000 Å thick (1 μm=10,000 Å).
  • Referring to FIG. 4C, the trenches 422 are then filled with a temporary or permanent refill material 428 such as a semi-insulating material, an insulating material, or a combination thereof. The refill material 428 can be a polysilicon, a re-crystalized polysilicon, a single crystal silicon, or a semi-insulating polycrystalline silicon (SIPOS). The trenches 422 may be filled using a SOG technique, CVD, surface reflow, or other methods known in the art. For example, the trenches 422 can be refilled with SIPOS. The amount of oxygen content in the SIPOS is selectively chosen to be between 2% and 80% to improve the electrical characteristics in the die 420. Increasing the amount of oxygen content is desirable for electrical characteristics, but varying the oxygen content also results in altered material properties. Higher oxygen content SIPOS will thermally expand and contract differently than the surrounding silicon which may lead to undesirable fracturing or cracking especially near the interface of differing materials. Accordingly, the oxygen content of the SIPOS is optimally selected to achieve the most desirable electrical characteristics without an undesirable impact on mechanical properties.
  • It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that the invention is not limited to the particular embodiments disclosed, but it is intended to cover modifications within the spirit and scope of the present invention as defined by the appended claims.

Claims (14)

1. A method of manufacturing a superjunction device, the method comprising:
(a) providing a semiconductor wafer, the semiconductor wafer including a plurality of dies;
(b) forming a first plurality of trenches in at least one first die, each of the first plurality of trenches having a first orientation; and
(c) forming a second plurality of trenches in at least one second die, each of the second plurality of trenches having a second orientation that is different from the first orientation.
2. The method of claim 1, wherein the a number of first dies containing the first plurality of trenches is equal to a number of second dies containing the second plurality of trenches.
3. The method of claim 2, wherein
(i) each of the first plurality of trenches has a length dimension, the length dimension of each of the first plurality of trenches being identical; and
(ii) each of the second plurality of trenches has a length dimension, the length dimension of each of the second plurality trenches being identical.
4. The method of claim 1, wherein the steps (a)-(c) are performed sequentially.
5. The method of claim 1, wherein the steps (b) and (c) are performed concurrently.
6. The method of claim 1, wherein prior to commencement of each of the steps (a)-(c), the respective preceding step is substantially completed.
7. The method of claim 1, wherein prior to commencement of each of the steps (a)-(c), the respective preceding step is fully completed.
8. A superjunction device formed by the method of claim 1.
9. A superjunction device comprising:
(a) a semiconductor wafer, the semiconductor wafer including a plurality of dies;
(b) a first plurality of trenches formed in a first plurality of dies, each of the first plurality of trenches having a first orientation; and
(c) a second plurality of trenches formed in a second plurality of dies, each of the second plurality of trenches having a second orientation that is different from the first orientation.
10. The device of claim 9, wherein the first plurality of trenches defines a first area and the second plurality of trenches defines a second area.
11. The device of claim 9, wherein a ratio of the first area to the second area is one-to-one.
12. The device of claim 9, wherein
(i) each of the first plurality of trenches has a length dimension, the length dimension of each of the first plurality of trenches being different from at least one other of the first plurality of trenches; and
(ii) each of the second plurality of trenches has a length dimension, the length dimension of each of the second plurality of trenches being different from at least one other of the second plurality of trenches.
13. The device of claim 9, wherein
(i) each of the first plurality of trenches has a length dimension, the length dimension of each of the first plurality of trenches being identical; and
(ii) each of the second plurality of trenches has a length dimension, the length dimension of each of the second plurality of trenches being identical.
14. A semiconductor device comprising:
(a) a semiconductor wafer, the semiconductor wafer including a plurality of dies;
(b) a first plurality of trenches formed in a first plurality of dies, each of the first plurality of trenches having a first orientation; and
(c) a second plurality of trenches formed in a second plurality of dies, each of the second plurality of trenches having a second orientation that is different from the first orientation.
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* Cited by examiner, † Cited by third party
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US8114751B2 (en) 2008-02-13 2012-02-14 Icemos Technology Ltd. Multi-angle rotation for ion implantation of trenches in superjunction devices
US8502237B2 (en) * 2011-03-03 2013-08-06 Kabushiki Kaisha Toshiba Semiconductor rectifying device
US9543380B2 (en) 2007-09-28 2017-01-10 Michael W. Shore Multi-directional trenching of a die in manufacturing superjunction devices
US9852999B2 (en) 2015-10-02 2017-12-26 International Business Machines Corporation Wafer reinforcement to reduce wafer curvature

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110233605A1 (en) * 2010-03-26 2011-09-29 Force Mos Technology Co. Ltd. Semiconductor power device layout for stress reduction
CN102315253A (en) * 2010-06-30 2012-01-11 力士科技股份有限公司 Layout design of semiconductor power device
ITMI20122226A1 (en) * 2012-12-21 2014-06-22 St Microelectronics Srl Realization of electronic devices in a wafer of semiconductor material with trenches having different directions
TW201430957A (en) * 2013-01-25 2014-08-01 Anpec Electronics Corp Method for fabricating semiconductor power device
JP6063280B2 (en) 2013-02-05 2017-01-18 ルネサスエレクトロニクス株式会社 Semiconductor device
US9461109B1 (en) * 2014-06-26 2016-10-04 Icemos Technology, Ltd. Method of forming superjunction high voltage devices using wafer bonding
CN104617133B (en) * 2015-01-23 2018-02-06 上海华虹宏力半导体制造有限公司 Layout structure and manufacturing method of the trench type superjunction device

Citations (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3404295A (en) * 1964-11-30 1968-10-01 Motorola Inc High frequency and voltage transistor with added region for punch-through protection
US3497777A (en) * 1967-06-13 1970-02-24 Stanislas Teszner Multichannel field-effect semi-conductor device
US3564356A (en) * 1968-10-24 1971-02-16 Tektronix Inc High voltage integrated circuit transistor
US4158206A (en) * 1977-02-07 1979-06-12 Rca Corporation Semiconductor device
US4211582A (en) * 1979-06-28 1980-07-08 International Business Machines Corporation Process for making large area isolation trenches utilizing a two-step selective etching technique
US4238278A (en) * 1979-06-14 1980-12-09 International Business Machines Corporation Polycrystalline silicon oxidation method for making shallow and deep isolation trenches
US4491486A (en) * 1981-09-17 1985-01-01 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device
US4754310A (en) * 1980-12-10 1988-06-28 U.S. Philips Corp. High voltage semiconductor device
US4775881A (en) * 1984-05-30 1988-10-04 Max-Planck-Gesellschaft Zur Forderung Der Wissenschaften E.V. Semiconductor device for detecting electromagnetic radiation or particles
US4821095A (en) * 1987-03-12 1989-04-11 General Electric Company Insulated gate semiconductor device with extra short grid and method of fabrication
US4866004A (en) * 1985-10-05 1989-09-12 Fujitsu Limited Method of forming groove isolation filled with dielectric for semiconductor device
US4868624A (en) * 1980-05-09 1989-09-19 Regents Of The University Of Minnesota Channel collector transistor
US4895810A (en) * 1986-03-21 1990-01-23 Advanced Power Technology, Inc. Iopographic pattern delineated power mosfet with profile tailored recessed source
US4994406A (en) * 1989-11-03 1991-02-19 Motorola Inc. Method of fabricating semiconductor devices having deep and shallow isolation structures
US5019522A (en) * 1986-03-21 1991-05-28 Advanced Power Technology, Inc. Method of making topographic pattern delineated power MOSFET with profile tailored recessed source
US5027180A (en) * 1986-12-11 1991-06-25 Mitsubishi Electric Corporation Double gate static induction thyristor
US5045903A (en) * 1988-05-17 1991-09-03 Advanced Power Technology, Inc. Topographic pattern delineated power MOSFET with profile tailored recessed source
US5105243A (en) * 1987-02-26 1992-04-14 Kabushiki Kaisha Toshiba Conductivity-modulation metal oxide field effect transistor with single gate structure
US5216275A (en) * 1991-03-19 1993-06-01 University Of Electronic Science And Technology Of China Semiconductor power devices with alternating conductivity type high-voltage breakdown regions
US5218226A (en) * 1989-11-01 1993-06-08 U.S. Philips Corp. Semiconductor device having high breakdown voltage
US5219777A (en) * 1991-06-14 1993-06-15 Gold Star Electron Co., Ltd. Metal oxide semiconductor field effect transistor and method of making the same
US5366914A (en) * 1992-01-29 1994-11-22 Nec Corporation Vertical power MOSFET structure having reduced cell area
US5389815A (en) * 1992-04-28 1995-02-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor diode with reduced recovery current
US5395790A (en) * 1994-05-11 1995-03-07 United Microelectronics Corp. Stress-free isolation layer
US5418376A (en) * 1993-03-02 1995-05-23 Toyo Denki Seizo Kabushiki Kaisha Static induction semiconductor device with a distributed main electrode structure and static induction semiconductor device with a static induction main electrode shorted structure
US5430311A (en) * 1991-09-20 1995-07-04 Hitachi, Ltd. Constant-voltage diode for over-voltage protection
US5432113A (en) * 1992-08-04 1995-07-11 Nippon Steel Corporation Method of making a semiconductor memory device
US5435888A (en) * 1993-12-06 1995-07-25 Sgs-Thomson Microelectronics, Inc. Enhanced planarization technique for an integrated circuit
US5438215A (en) * 1993-03-25 1995-08-01 Siemens Aktiengesellschaft Power MOSFET
US5472888A (en) * 1988-02-25 1995-12-05 International Rectifier Corporation Depletion mode power MOSFET with refractory gate and method of making same
US5506421A (en) * 1992-11-24 1996-04-09 Cree Research, Inc. Power MOSFET in silicon carbide
US5510287A (en) * 1994-11-01 1996-04-23 Taiwan Semiconductor Manuf. Company Method of making vertical channel mask ROM
US5519245A (en) * 1989-08-31 1996-05-21 Nippondenso Co., Ltd. Insulated gate bipolar transistor with reverse conducting current
US5572048A (en) * 1992-11-20 1996-11-05 Hitachi, Ltd. Voltage-driven type semiconductor device
US5598018A (en) * 1978-10-13 1997-01-28 International Rectifier Corporation High power MOSFET with low on-resistance and high breakdown voltage
US5726469A (en) * 1994-07-20 1998-03-10 University Of Elec. Sci. & Tech. Of China Surface voltage sustaining structure for semiconductor devices
US5744994A (en) * 1996-05-15 1998-04-28 Siliconix Incorporated Three-terminal power mosfet switch for use as synchronous rectifier or voltage clamp
US5902127A (en) * 1996-06-17 1999-05-11 Samsung Electronics Co., Ltd. Methods for forming isolation trenches including doped silicon oxide
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5939754A (en) * 1996-09-09 1999-08-17 Nissan Motor Co., Ltd. Power MOSFET having a drain heterojunction
US5998292A (en) * 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
US6008106A (en) * 1997-07-15 1999-12-28 Mosel Vitelic Inc. Micro-trench oxidation by using rough oxide mask for field isolation
US6011298A (en) * 1996-12-31 2000-01-04 Stmicroelectronics, Inc. High voltage termination with buried field-shaping region
US6066878A (en) * 1997-11-10 2000-05-23 Intersil Corporation High voltage semiconductor structure
US6174773B1 (en) * 1995-02-17 2001-01-16 Fuji Electric Co., Ltd. Method of manufacturing vertical trench misfet
US6184555B1 (en) * 1996-02-05 2001-02-06 Siemens Aktiengesellschaft Field effect-controlled semiconductor component
US6190970B1 (en) * 1999-01-04 2001-02-20 Industrial Technology Research Institute Method of making power MOSFET and IGBT with optimized on-resistance and breakdown voltage
US6198127B1 (en) * 1999-05-19 2001-03-06 Intersil Corporation MOS-gated power device having extended trench and doping zone and process for forming same
US6214698B1 (en) * 2000-01-11 2001-04-10 Taiwan Semiconductor Manufacturing Company Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer
US6222229B1 (en) * 1999-02-18 2001-04-24 Cree, Inc. Self-aligned shield structure for realizing high frequency power MOSFET devices with improved reliability
US6239463B1 (en) * 1997-08-28 2001-05-29 Siliconix Incorporated Low resistance power MOSFET or other device containing silicon-germanium layer
US6265281B1 (en) * 1997-08-18 2001-07-24 Micron Technology, Inc. Method for forming dielectric within a recess
US6291856B1 (en) * 1998-11-12 2001-09-18 Fuji Electric Co., Ltd. Semiconductor device with alternating conductivity type layer and method of manufacturing the same
US6300171B1 (en) * 1998-12-09 2001-10-09 Stmicroelectronics S.R.L. Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure
US6307246B1 (en) * 1998-07-23 2001-10-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor resurf devices formed by oblique trench implantation
US6310365B1 (en) * 1998-07-23 2001-10-30 University Of Electronic Science And Technology Surface voltage sustaining structure for semiconductor devices having floating voltage terminal
US6362505B1 (en) * 1998-11-27 2002-03-26 Siemens Aktiengesellschaft MOS field-effect transistor with auxiliary electrode
US6391723B1 (en) * 1999-05-31 2002-05-21 Stmicroelectronics S.R.L. Fabrication of VDMOS structure with reduced parasitic effects
US20020070418A1 (en) * 2000-12-07 2002-06-13 International Rectifier Corporation High voltage vertical conduction superjunction semiconductor device
US6410958B1 (en) * 2000-11-27 2002-06-25 Kabushiki Kaisha Toshiba Power MOSFET having laterally three-layered structure formed among element isolation regions
US6426991B1 (en) * 2000-11-16 2002-07-30 Koninklijke Philips Electronics N.V. Back-illuminated photodiodes for computed tomography detectors
US6452230B1 (en) * 1998-12-23 2002-09-17 International Rectifier Corporation High voltage mosgated device with trenches to reduce on-resistance
US6459124B1 (en) * 1996-10-02 2002-10-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and process for manufacturing the same, and electronic device
US6465325B2 (en) * 2001-02-27 2002-10-15 Fairchild Semiconductor Corporation Process for depositing and planarizing BPSG for dense trench MOSFET application
US6495421B2 (en) * 1999-12-15 2002-12-17 Koninklijke Philips Electronics N.V. Manufacture of semiconductor material and devices using that material
US6501130B2 (en) * 2001-01-24 2002-12-31 Power Integrations, Inc. High-voltage transistor with buried conduction layer
US6501146B1 (en) * 1997-06-18 2002-12-31 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing thereof
US6504230B2 (en) * 1999-09-07 2003-01-07 Infineon Technologies Ag Compensation component and method for fabricating the compensation component
US6509220B2 (en) * 2000-11-27 2003-01-21 Power Integrations, Inc. Method of fabricating a high-voltage transistor
US6512267B2 (en) * 2001-04-12 2003-01-28 International Rectifier Corporation Superjunction device with self compensated trench walls
US6534367B2 (en) * 2001-04-28 2003-03-18 Koninklijke Philips Electronics N.V. Trench-gate semiconductor devices and their manufacture
US6566201B1 (en) * 2001-12-31 2003-05-20 General Semiconductor, Inc. Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion
US6613644B2 (en) * 2000-08-22 2003-09-02 Infineon Technologies Ag Method for forming a dielectric zone in a semiconductor substrate
US6624494B2 (en) * 2001-10-04 2003-09-23 General Semiconductor, Inc. Method for fabricating a power semiconductor device having a floating island voltage sustaining layer
US6635906B1 (en) * 1993-10-29 2003-10-21 Third Dimension (3D) Semiconductor Voltage sustaining layer with opposite-doped islands for semi-conductor power devices
US20030222327A1 (en) * 2002-03-18 2003-12-04 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing semiconductor device
US6686244B2 (en) * 2002-03-21 2004-02-03 General Semiconductor, Inc. Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
US6710403B2 (en) * 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
US6710418B1 (en) * 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same
US6713813B2 (en) * 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure
US6762473B1 (en) * 2003-06-25 2004-07-13 Semicoa Semiconductors Ultra thin back-illuminated photodiode array structures and fabrication methods
US6787872B2 (en) * 2001-06-26 2004-09-07 International Rectifier Corporation Lateral conduction superjunction semiconductor device
US6797589B2 (en) * 2001-12-18 2004-09-28 Kionix, Inc. Insulating micro-structure and method of manufacturing same
US20050176192A1 (en) * 2003-12-19 2005-08-11 Third Dimension (3D) Semiconductor, Inc. Planarization method of manufacturing a superjunction device
US6936907B2 (en) * 2002-08-29 2005-08-30 The University Of Electronic Science And Technology Of China Lateral high-voltage semiconductor devices with surface covered by thin film of dielectric material with high permittivity
US6998681B2 (en) * 2003-10-16 2006-02-14 University Of Electronic Science And Technology Lateral low-side and high-side high-voltage devices
US7015104B1 (en) * 2003-05-29 2006-03-21 Third Dimension Semiconductor, Inc. Technique for forming the deep doped columns in superjunction
US7023069B2 (en) * 2003-12-19 2006-04-04 Third Dimension (3D) Semiconductor, Inc. Method for forming thick dielectric regions using etched trenches
US7041560B2 (en) * 2003-12-19 2006-05-09 Third Dimension (3D) Semiconductor, Inc. Method of manufacturing a superjunction device with conventional terminations
US7052982B2 (en) * 2003-12-19 2006-05-30 Third Dimension (3D) Semiconductor, Inc. Method for manufacturing a superjunction device with wide mesas
US7109110B2 (en) * 2003-12-19 2006-09-19 Third Dimension (3D) Semiconductor, Inc. Method of manufacturing a superjunction device
US20100015797A1 (en) * 2005-08-26 2010-01-21 Toshio Saito Manufacturing method of semiconductor device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5238889A (en) 1975-09-22 1977-03-25 Mitsubishi Electric Corp Vertical junction type field effect transistor
US6037671A (en) * 1998-11-03 2000-03-14 Advanced Micro Devices, Inc. Stepper alignment mark structure for maintaining alignment integrity
US7638841B2 (en) 2003-05-20 2009-12-29 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
US6683363B2 (en) 2001-07-03 2004-01-27 Fairchild Semiconductor Corporation Trench structure for semiconductor devices
JP4166627B2 (en) 2003-05-30 2008-10-15 株式会社デンソー Semiconductor device
US20050067667A1 (en) 2003-09-26 2005-03-31 Goushcha Alexander O. Fast silicon photodiodes with high back surface reflectance in a wavelength range close to the bandgap
US7405452B2 (en) 2004-02-02 2008-07-29 Hamza Yilmaz Semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics
US8580651B2 (en) 2007-04-23 2013-11-12 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
US7723172B2 (en) 2007-04-23 2010-05-25 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
US20080272429A1 (en) 2007-05-04 2008-11-06 Icemos Technology Corporation Superjunction devices having narrow surface layout of terminal structures and methods of manufacturing the devices
US7998826B2 (en) * 2007-09-07 2011-08-16 Macronix International Co., Ltd. Method of forming mark in IC-fabricating process
US8012806B2 (en) 2007-09-28 2011-09-06 Icemos Technology Ltd. Multi-directional trenching of a die in manufacturing superjunction devices

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3404295A (en) * 1964-11-30 1968-10-01 Motorola Inc High frequency and voltage transistor with added region for punch-through protection
US3497777A (en) * 1967-06-13 1970-02-24 Stanislas Teszner Multichannel field-effect semi-conductor device
US3564356A (en) * 1968-10-24 1971-02-16 Tektronix Inc High voltage integrated circuit transistor
US4158206A (en) * 1977-02-07 1979-06-12 Rca Corporation Semiconductor device
US5598018A (en) * 1978-10-13 1997-01-28 International Rectifier Corporation High power MOSFET with low on-resistance and high breakdown voltage
US5742087A (en) * 1978-10-13 1998-04-21 International Rectifier Corporation High power MOSFET with low on-resistance and high breakdown voltage
US4238278A (en) * 1979-06-14 1980-12-09 International Business Machines Corporation Polycrystalline silicon oxidation method for making shallow and deep isolation trenches
US4211582A (en) * 1979-06-28 1980-07-08 International Business Machines Corporation Process for making large area isolation trenches utilizing a two-step selective etching technique
US4868624A (en) * 1980-05-09 1989-09-19 Regents Of The University Of Minnesota Channel collector transistor
US4754310A (en) * 1980-12-10 1988-06-28 U.S. Philips Corp. High voltage semiconductor device
US4491486A (en) * 1981-09-17 1985-01-01 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device
US4775881A (en) * 1984-05-30 1988-10-04 Max-Planck-Gesellschaft Zur Forderung Der Wissenschaften E.V. Semiconductor device for detecting electromagnetic radiation or particles
US4866004A (en) * 1985-10-05 1989-09-12 Fujitsu Limited Method of forming groove isolation filled with dielectric for semiconductor device
US4895810A (en) * 1986-03-21 1990-01-23 Advanced Power Technology, Inc. Iopographic pattern delineated power mosfet with profile tailored recessed source
US5019522A (en) * 1986-03-21 1991-05-28 Advanced Power Technology, Inc. Method of making topographic pattern delineated power MOSFET with profile tailored recessed source
US5027180A (en) * 1986-12-11 1991-06-25 Mitsubishi Electric Corporation Double gate static induction thyristor
US5105243A (en) * 1987-02-26 1992-04-14 Kabushiki Kaisha Toshiba Conductivity-modulation metal oxide field effect transistor with single gate structure
US4821095A (en) * 1987-03-12 1989-04-11 General Electric Company Insulated gate semiconductor device with extra short grid and method of fabrication
US5472888A (en) * 1988-02-25 1995-12-05 International Rectifier Corporation Depletion mode power MOSFET with refractory gate and method of making same
US5786619A (en) * 1988-02-25 1998-07-28 International Rectifier Corporation Depletion mode power MOSFET with refractory gate and method of making same
US5045903A (en) * 1988-05-17 1991-09-03 Advanced Power Technology, Inc. Topographic pattern delineated power MOSFET with profile tailored recessed source
US5519245A (en) * 1989-08-31 1996-05-21 Nippondenso Co., Ltd. Insulated gate bipolar transistor with reverse conducting current
US5218226A (en) * 1989-11-01 1993-06-08 U.S. Philips Corp. Semiconductor device having high breakdown voltage
US4994406A (en) * 1989-11-03 1991-02-19 Motorola Inc. Method of fabricating semiconductor devices having deep and shallow isolation structures
US5216275A (en) * 1991-03-19 1993-06-01 University Of Electronic Science And Technology Of China Semiconductor power devices with alternating conductivity type high-voltage breakdown regions
US5219777A (en) * 1991-06-14 1993-06-15 Gold Star Electron Co., Ltd. Metal oxide semiconductor field effect transistor and method of making the same
US5430311A (en) * 1991-09-20 1995-07-04 Hitachi, Ltd. Constant-voltage diode for over-voltage protection
US5366914A (en) * 1992-01-29 1994-11-22 Nec Corporation Vertical power MOSFET structure having reduced cell area
US5389815A (en) * 1992-04-28 1995-02-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor diode with reduced recovery current
US5432113A (en) * 1992-08-04 1995-07-11 Nippon Steel Corporation Method of making a semiconductor memory device
US5572048A (en) * 1992-11-20 1996-11-05 Hitachi, Ltd. Voltage-driven type semiconductor device
US5506421A (en) * 1992-11-24 1996-04-09 Cree Research, Inc. Power MOSFET in silicon carbide
US5418376A (en) * 1993-03-02 1995-05-23 Toyo Denki Seizo Kabushiki Kaisha Static induction semiconductor device with a distributed main electrode structure and static induction semiconductor device with a static induction main electrode shorted structure
US5438215A (en) * 1993-03-25 1995-08-01 Siemens Aktiengesellschaft Power MOSFET
US6936867B2 (en) * 1993-10-29 2005-08-30 Third Dimension Semiconductor, Inc. Semiconductor high-voltage devices
US6635906B1 (en) * 1993-10-29 2003-10-21 Third Dimension (3D) Semiconductor Voltage sustaining layer with opposite-doped islands for semi-conductor power devices
US5435888A (en) * 1993-12-06 1995-07-25 Sgs-Thomson Microelectronics, Inc. Enhanced planarization technique for an integrated circuit
US5395790A (en) * 1994-05-11 1995-03-07 United Microelectronics Corp. Stress-free isolation layer
US5726469A (en) * 1994-07-20 1998-03-10 University Of Elec. Sci. & Tech. Of China Surface voltage sustaining structure for semiconductor devices
US5510287A (en) * 1994-11-01 1996-04-23 Taiwan Semiconductor Manuf. Company Method of making vertical channel mask ROM
US6174773B1 (en) * 1995-02-17 2001-01-16 Fuji Electric Co., Ltd. Method of manufacturing vertical trench misfet
US6184555B1 (en) * 1996-02-05 2001-02-06 Siemens Aktiengesellschaft Field effect-controlled semiconductor component
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5929690A (en) * 1996-05-15 1999-07-27 Siliconix Incorporated Three-terminal power MOSFET switch for use as synchronous rectifier or voltage clamp
US5744994A (en) * 1996-05-15 1998-04-28 Siliconix Incorporated Three-terminal power mosfet switch for use as synchronous rectifier or voltage clamp
US5902127A (en) * 1996-06-17 1999-05-11 Samsung Electronics Co., Ltd. Methods for forming isolation trenches including doped silicon oxide
US5939754A (en) * 1996-09-09 1999-08-17 Nissan Motor Co., Ltd. Power MOSFET having a drain heterojunction
US6459124B1 (en) * 1996-10-02 2002-10-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and process for manufacturing the same, and electronic device
US6011298A (en) * 1996-12-31 2000-01-04 Stmicroelectronics, Inc. High voltage termination with buried field-shaping region
US6501146B1 (en) * 1997-06-18 2002-12-31 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing thereof
US6008106A (en) * 1997-07-15 1999-12-28 Mosel Vitelic Inc. Micro-trench oxidation by using rough oxide mask for field isolation
US6265281B1 (en) * 1997-08-18 2001-07-24 Micron Technology, Inc. Method for forming dielectric within a recess
US6239463B1 (en) * 1997-08-28 2001-05-29 Siliconix Incorporated Low resistance power MOSFET or other device containing silicon-germanium layer
US6066878A (en) * 1997-11-10 2000-05-23 Intersil Corporation High voltage semiconductor structure
US6081009A (en) * 1997-11-10 2000-06-27 Intersil Corporation High voltage mosfet structure
US5998292A (en) * 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
US6307246B1 (en) * 1998-07-23 2001-10-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor resurf devices formed by oblique trench implantation
US6310365B1 (en) * 1998-07-23 2001-10-30 University Of Electronic Science And Technology Surface voltage sustaining structure for semiconductor devices having floating voltage terminal
US6291856B1 (en) * 1998-11-12 2001-09-18 Fuji Electric Co., Ltd. Semiconductor device with alternating conductivity type layer and method of manufacturing the same
US6362505B1 (en) * 1998-11-27 2002-03-26 Siemens Aktiengesellschaft MOS field-effect transistor with auxiliary electrode
US6300171B1 (en) * 1998-12-09 2001-10-09 Stmicroelectronics S.R.L. Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure
US6452230B1 (en) * 1998-12-23 2002-09-17 International Rectifier Corporation High voltage mosgated device with trenches to reduce on-resistance
US6190970B1 (en) * 1999-01-04 2001-02-20 Industrial Technology Research Institute Method of making power MOSFET and IGBT with optimized on-resistance and breakdown voltage
US6359309B1 (en) * 1999-01-04 2002-03-19 Industrial Technology Research Institute Power MOSFET and IGBT with optimized on-resistance and breakdown voltage
US6222229B1 (en) * 1999-02-18 2001-04-24 Cree, Inc. Self-aligned shield structure for realizing high frequency power MOSFET devices with improved reliability
US6198127B1 (en) * 1999-05-19 2001-03-06 Intersil Corporation MOS-gated power device having extended trench and doping zone and process for forming same
US6391723B1 (en) * 1999-05-31 2002-05-21 Stmicroelectronics S.R.L. Fabrication of VDMOS structure with reduced parasitic effects
US6504230B2 (en) * 1999-09-07 2003-01-07 Infineon Technologies Ag Compensation component and method for fabricating the compensation component
US6495421B2 (en) * 1999-12-15 2002-12-17 Koninklijke Philips Electronics N.V. Manufacture of semiconductor material and devices using that material
US6214698B1 (en) * 2000-01-11 2001-04-10 Taiwan Semiconductor Manufacturing Company Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer
US6613644B2 (en) * 2000-08-22 2003-09-02 Infineon Technologies Ag Method for forming a dielectric zone in a semiconductor substrate
US6426991B1 (en) * 2000-11-16 2002-07-30 Koninklijke Philips Electronics N.V. Back-illuminated photodiodes for computed tomography detectors
US6410958B1 (en) * 2000-11-27 2002-06-25 Kabushiki Kaisha Toshiba Power MOSFET having laterally three-layered structure formed among element isolation regions
US6509220B2 (en) * 2000-11-27 2003-01-21 Power Integrations, Inc. Method of fabricating a high-voltage transistor
US20020070418A1 (en) * 2000-12-07 2002-06-13 International Rectifier Corporation High voltage vertical conduction superjunction semiconductor device
US6501130B2 (en) * 2001-01-24 2002-12-31 Power Integrations, Inc. High-voltage transistor with buried conduction layer
US6713813B2 (en) * 2001-01-30 2004-03-30 Fairchild Semiconductor Corporation Field effect transistor having a lateral depletion structure
US6465325B2 (en) * 2001-02-27 2002-10-15 Fairchild Semiconductor Corporation Process for depositing and planarizing BPSG for dense trench MOSFET application
US6512267B2 (en) * 2001-04-12 2003-01-28 International Rectifier Corporation Superjunction device with self compensated trench walls
US6534367B2 (en) * 2001-04-28 2003-03-18 Koninklijke Philips Electronics N.V. Trench-gate semiconductor devices and their manufacture
US6787872B2 (en) * 2001-06-26 2004-09-07 International Rectifier Corporation Lateral conduction superjunction semiconductor device
US6624494B2 (en) * 2001-10-04 2003-09-23 General Semiconductor, Inc. Method for fabricating a power semiconductor device having a floating island voltage sustaining layer
US6797589B2 (en) * 2001-12-18 2004-09-28 Kionix, Inc. Insulating micro-structure and method of manufacturing same
US6566201B1 (en) * 2001-12-31 2003-05-20 General Semiconductor, Inc. Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion
US6710400B2 (en) * 2001-12-31 2004-03-23 General Semiconductor, Inc. Method for fabricating a high voltage power MOSFET having a voltage sustaining region that includes doped columns formed by rapid diffusion
US20030222327A1 (en) * 2002-03-18 2003-12-04 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing semiconductor device
US6686244B2 (en) * 2002-03-21 2004-02-03 General Semiconductor, Inc. Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
US6710403B2 (en) * 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
US6936907B2 (en) * 2002-08-29 2005-08-30 The University Of Electronic Science And Technology Of China Lateral high-voltage semiconductor devices with surface covered by thin film of dielectric material with high permittivity
US6710418B1 (en) * 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same
US7015104B1 (en) * 2003-05-29 2006-03-21 Third Dimension Semiconductor, Inc. Technique for forming the deep doped columns in superjunction
US6762473B1 (en) * 2003-06-25 2004-07-13 Semicoa Semiconductors Ultra thin back-illuminated photodiode array structures and fabrication methods
US6998681B2 (en) * 2003-10-16 2006-02-14 University Of Electronic Science And Technology Lateral low-side and high-side high-voltage devices
US20050176192A1 (en) * 2003-12-19 2005-08-11 Third Dimension (3D) Semiconductor, Inc. Planarization method of manufacturing a superjunction device
US7023069B2 (en) * 2003-12-19 2006-04-04 Third Dimension (3D) Semiconductor, Inc. Method for forming thick dielectric regions using etched trenches
US7041560B2 (en) * 2003-12-19 2006-05-09 Third Dimension (3D) Semiconductor, Inc. Method of manufacturing a superjunction device with conventional terminations
US7052982B2 (en) * 2003-12-19 2006-05-30 Third Dimension (3D) Semiconductor, Inc. Method for manufacturing a superjunction device with wide mesas
US7109110B2 (en) * 2003-12-19 2006-09-19 Third Dimension (3D) Semiconductor, Inc. Method of manufacturing a superjunction device
US20100015797A1 (en) * 2005-08-26 2010-01-21 Toshio Saito Manufacturing method of semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9543380B2 (en) 2007-09-28 2017-01-10 Michael W. Shore Multi-directional trenching of a die in manufacturing superjunction devices
US8114751B2 (en) 2008-02-13 2012-02-14 Icemos Technology Ltd. Multi-angle rotation for ion implantation of trenches in superjunction devices
US8502237B2 (en) * 2011-03-03 2013-08-06 Kabushiki Kaisha Toshiba Semiconductor rectifying device
US9852999B2 (en) 2015-10-02 2017-12-26 International Business Machines Corporation Wafer reinforcement to reduce wafer curvature
US10304783B2 (en) 2015-10-02 2019-05-28 International Business Machines Corporation Wafer reinforcement to reduce wafer curvature

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US8012806B2 (en) 2011-09-06
US20110254137A1 (en) 2011-10-20
US9543380B2 (en) 2017-01-10
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WO2009040650A1 (en) 2009-04-02

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