JP4260405B2 - 半導体集積回路装置の製造方法 - Google Patents

半導体集積回路装置の製造方法 Download PDF

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Publication number
JP4260405B2
JP4260405B2 JP2002032379A JP2002032379A JP4260405B2 JP 4260405 B2 JP4260405 B2 JP 4260405B2 JP 2002032379 A JP2002032379 A JP 2002032379A JP 2002032379 A JP2002032379 A JP 2002032379A JP 4260405 B2 JP4260405 B2 JP 4260405B2
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film
wiring
integrated circuit
semiconductor integrated
circuit device
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Expired - Fee Related
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Japanese (ja)
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JP2003234348A5 (enExample
JP2003234348A (ja
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明 矢島
健一 山本
宏美 阿部
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Renesas Technology Corp
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Renesas Technology Corp
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Priority to JP2002032379A priority Critical patent/JP4260405B2/ja
Priority to US10/341,447 priority patent/US6861344B2/en
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Publication of JP2003234348A5 publication Critical patent/JP2003234348A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2002032379A 2002-02-08 2002-02-08 半導体集積回路装置の製造方法 Expired - Fee Related JP4260405B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002032379A JP4260405B2 (ja) 2002-02-08 2002-02-08 半導体集積回路装置の製造方法
US10/341,447 US6861344B2 (en) 2002-02-08 2003-01-14 Method of manufacturing a semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002032379A JP4260405B2 (ja) 2002-02-08 2002-02-08 半導体集積回路装置の製造方法

Related Child Applications (1)

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JP2006013356A Division JP2006203215A (ja) 2006-01-23 2006-01-23 半導体集積回路装置およびその製造方法

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JP2003234348A JP2003234348A (ja) 2003-08-22
JP2003234348A5 JP2003234348A5 (enExample) 2006-03-09
JP4260405B2 true JP4260405B2 (ja) 2009-04-30

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Families Citing this family (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003017520A (ja) * 2001-06-28 2003-01-17 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP2003017521A (ja) * 2001-06-28 2003-01-17 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP2004063672A (ja) * 2002-07-26 2004-02-26 Oki Electric Ind Co Ltd 有機絶縁膜の形成方法、及び半導体装置の製造方法
FR2854731B1 (fr) * 2003-05-05 2005-08-12 St Microelectronics Sa Circuit integre et procede de test associe
JP3866710B2 (ja) * 2003-12-24 2007-01-10 エルピーダメモリ株式会社 半導体ウェーハ及びそのダイシング方法
JP4415747B2 (ja) * 2004-04-30 2010-02-17 ソニー株式会社 半導体装置の製造方法
JP4609983B2 (ja) * 2004-04-30 2011-01-12 ルネサスエレクトロニクス株式会社 電極パッドを備える素子
US7405108B2 (en) * 2004-11-20 2008-07-29 International Business Machines Corporation Methods for forming co-planar wafer-scale chip packages
KR100602131B1 (ko) * 2004-12-30 2006-07-19 동부일렉트로닉스 주식회사 반도체 소자 및 그의 제조방법
JP4843229B2 (ja) * 2005-02-23 2011-12-21 株式会社東芝 半導体装置の製造方法
TWI268564B (en) * 2005-04-11 2006-12-11 Siliconware Precision Industries Co Ltd Semiconductor device and fabrication method thereof
KR100653715B1 (ko) * 2005-06-17 2006-12-05 삼성전자주식회사 적어도 하나의 개구부를 갖는 최상부 금속층을 구비하는반도체 소자들 및 그 제조방법들
JPWO2007004535A1 (ja) 2005-07-05 2009-01-29 株式会社ルネサステクノロジ 半導体装置およびその製造方法
JP2007073681A (ja) * 2005-09-06 2007-03-22 Renesas Technology Corp 半導体装置およびその製造方法
JP4745007B2 (ja) 2005-09-29 2011-08-10 三洋電機株式会社 半導体装置及びその製造方法
KR100881108B1 (ko) * 2005-11-24 2009-02-02 가부시키가이샤 리코 스크라이브 라인에 의해 분할된 반도체 칩 및 스크라이브라인 상에 형성된 공정-모니터 전극 패드를 포함하는반도체 웨이퍼
KR100970156B1 (ko) * 2005-12-08 2010-07-14 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치
JP2007294899A (ja) * 2006-03-31 2007-11-08 Dowa Electronics Materials Co Ltd 半田層及びそれを用いた電子デバイス接合用基板並びに電子デバイス接合用サブマウント
JP2007299968A (ja) * 2006-05-01 2007-11-15 Matsushita Electric Ind Co Ltd 半導体装置
JP5162851B2 (ja) * 2006-07-14 2013-03-13 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP2008124437A (ja) 2006-10-19 2008-05-29 Matsushita Electric Ind Co Ltd 半導体ウェハ、その製造方法、および半導体チップの製造方法
US7834449B2 (en) * 2007-04-30 2010-11-16 Broadcom Corporation Highly reliable low cost structure for wafer-level ball grid array packaging
US7872347B2 (en) * 2007-08-09 2011-01-18 Broadcom Corporation Larger than die size wafer-level redistribution packaging process
US8030775B2 (en) * 2007-08-27 2011-10-04 Megica Corporation Wirebond over post passivation thick metal
JP5064157B2 (ja) * 2007-09-18 2012-10-31 新光電気工業株式会社 半導体装置の製造方法
US8872329B1 (en) * 2009-01-09 2014-10-28 Amkor Technology, Inc. Extended landing pad substrate package structure and method
JP2010192867A (ja) 2009-01-20 2010-09-02 Renesas Electronics Corp 半導体集積回路装置および半導体集積回路装置の製造方法
KR20100104377A (ko) * 2009-03-17 2010-09-29 삼성전자주식회사 내부 스트레스를 줄일 수 있는 반도체 패키지
JP2010287592A (ja) * 2009-06-09 2010-12-24 Renesas Electronics Corp 半導体装置、半導体ウェハおよびその製造方法
US8643164B2 (en) * 2009-06-11 2014-02-04 Broadcom Corporation Package-on-package technology for fan-out wafer-level packaging
JP5559599B2 (ja) * 2010-05-25 2014-07-23 ローム株式会社 半導体装置およびその製造方法ならびに半導体ウエハ
JP5607994B2 (ja) * 2010-06-15 2014-10-15 ルネサスエレクトロニクス株式会社 半導体集積回路装置およびその製造方法
US9773744B2 (en) * 2011-07-12 2017-09-26 Globalfoundries Inc. Solder bump cleaning before reflow
JP5503626B2 (ja) * 2011-11-24 2014-05-28 ラピスセミコンダクタ株式会社 半導体ウェハおよびそれにより形成した半導体装置
US9257333B2 (en) 2013-03-11 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9368398B2 (en) 2012-01-12 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US9263839B2 (en) 2012-12-28 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved fine pitch joint
US10015888B2 (en) 2013-02-15 2018-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect joint protective layer apparatus and method
US9401308B2 (en) 2013-03-12 2016-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices, methods of manufacture thereof, and packaging methods
US9607921B2 (en) * 2012-01-12 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package interconnect structure
US9589862B2 (en) 2013-03-11 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9082776B2 (en) 2012-08-24 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having protective layer with curved surface and method of manufacturing same
US9472515B2 (en) 2014-03-11 2016-10-18 Intel Corporation Integrated circuit package
CN105225944A (zh) * 2014-06-06 2016-01-06 北大方正集团有限公司 一种金属层去除方法
WO2016075791A1 (ja) 2014-11-13 2016-05-19 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP6507007B2 (ja) * 2015-03-27 2019-04-24 東レエンジニアリング株式会社 Ｌｅｄモジュールおよびｌｅｄモジュールの製造方法
JP6552040B2 (ja) * 2015-07-14 2019-07-31 Ｊｘ金属株式会社 半導体用ウェハの処理液、および半導体用ウェハの処理方法
JP6639141B2 (ja) * 2015-08-05 2020-02-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
KR102357937B1 (ko) 2015-08-26 2022-02-04 삼성전자주식회사 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지
KR102372349B1 (ko) * 2015-08-26 2022-03-11 삼성전자주식회사 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지
JP2017045900A (ja) * 2015-08-27 2017-03-02 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
KR102450326B1 (ko) * 2015-10-06 2022-10-05 삼성전자주식회사 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof
US9865516B2 (en) * 2016-01-10 2018-01-09 Micron Technology, Inc. Wafers having a die region and a scribe-line region adjacent to the die region
JP6846117B2 (ja) * 2016-04-12 2021-03-24 ローム株式会社 半導体装置および半導体装置の製造方法
CN108277349A (zh) * 2018-02-01 2018-07-13 燕山大学 一种钛铝层状复合材料的选择性反应分离及回收方法
US10651100B2 (en) * 2018-05-16 2020-05-12 Micron Technology, Inc. Substrates, structures within a scribe-line area of a substrate, and methods of forming a conductive line of a redistribution layer of a substrate and of forming a structure within a scribe-line area of the substrate
US10847482B2 (en) 2018-05-16 2020-11-24 Micron Technology, Inc. Integrated circuit structures and methods of forming an opening in a material
JP6937283B2 (ja) * 2018-09-19 2021-09-22 株式会社東芝 半導体装置の製造方法
US10522488B1 (en) 2018-10-31 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Patterning polymer layer to reduce stress
JP7332304B2 (ja) 2019-02-14 2023-08-23 キオクシア株式会社 半導体装置およびその製造方法
JP7613029B2 (ja) * 2020-09-09 2025-01-15 株式会社ソシオネクスト 半導体装置
CN112888154B (zh) * 2021-01-14 2023-05-16 京东方科技集团股份有限公司 柔性线路板及制备方法、显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000188332A (ja) * 1998-12-22 2000-07-04 Seiko Epson Corp 半導体装置及びその製造方法
JP2000294607A (ja) 1999-04-08 2000-10-20 Hitachi Ltd 半導体装置の製造方法
AT409429B (de) * 1999-07-15 2002-08-26 Sez Semiconduct Equip Zubehoer Verfahren zum ätzbehandeln von halbleitersubstraten zwecks freilegen einer metallschicht
KR100314133B1 (ko) * 1999-11-26 2001-11-15 윤종용 가장자리에 흡습방지막이 형성된 반도체 칩 및 이흡습방지막의 형성방법
US6727185B1 (en) * 1999-11-29 2004-04-27 Texas Instruments Incorporated Dry process for post oxide etch residue removal
JP2001185552A (ja) * 1999-12-27 2001-07-06 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6573113B1 (en) * 2001-09-04 2003-06-03 Lsi Logic Corporation Integrated circuit having dedicated probe pads for use in testing densely patterned bonding pads
US6660624B2 (en) * 2002-02-14 2003-12-09 Taiwan Semiconductor Manufacturing Co., Ltd. Method for reducing fluorine induced defects on a bonding pad surface
US6582983B1 (en) * 2002-07-12 2003-06-24 Keteca Singapore Singapore Method and wafer for maintaining ultra clean bonding pads on a wafer

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US20030153172A1 (en) 2003-08-14
JP2003234348A (ja) 2003-08-22
US6861344B2 (en) 2005-03-01

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