JP4201128B2 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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- JP4201128B2 JP4201128B2 JP2003274771A JP2003274771A JP4201128B2 JP 4201128 B2 JP4201128 B2 JP 4201128B2 JP 2003274771 A JP2003274771 A JP 2003274771A JP 2003274771 A JP2003274771 A JP 2003274771A JP 4201128 B2 JP4201128 B2 JP 4201128B2
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- 239000004065 semiconductor Substances 0.000 title claims description 70
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0278—Arrangements for impedance matching
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/28—Impedance matching networks
- H03H11/30—Automatic matching of source impedance to load impedance
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0005—Modifications of input or output impedance
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
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- Computer Hardware Design (AREA)
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- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Dram (AREA)
- Memory System (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
1,2…出力バッファ、3,4…出力プリバッファ、100〜122…Nチャネル出力MOSFET、200〜222…Pチャネル出力MOSFET、300〜322,400〜422…出力プリバッファ、40〜43…PチャネルMOSFET、50〜53…NチャネルMOSFET、60〜62…ゲート回路、
PBF…出力プリバッファ、
MUL0〜MUL7、MUR0〜MUR7、MLL0〜MLL7、MLR0〜MLR7…セルアレー、MWD…メインワードドライバ、CK/ADR/CNTL…入力回路、DI/DQ…データ入出力回路、I/O…入出力回路、REG/PDEC…プリデコーダ等、DLLC…同期化回路、JTAG/TAP…テスト回路、VG…内部電源電圧発生回路、Fuse …ヒューズ回路、VREF…参照電圧発生回路、
DQ−A〜DQ−D…データ入出力端子、VC1〜VC4…電圧比較回路、CLM1〜4…リミッタ回路、ADD/CON…アドレス/コントロール端子、
CLK…クロック端子、JTAG…テストインターファイス回路。
Claims (4)
- 第1インピーダンスコードにより出力インピーダンスが可変にされてなる複数の出力回路と、
外部端子に接続された第1抵抗素子に対応して上記第1インピーダンスコードを生成する第1インピーダンス制御回路とを備え、
上記第1インピーダンス制御回路は、上記第1抵抗素子と上記出力回路と同等に形成されレプリカ回路とのインピーダンス比較を行い、上記出力インピーダンスを増加させる第1信号と、出力インピーダンスを減少させる第2信号とを形成する1つの第1インピーダンス比較回路と、上記1つの第1インピーダンス比較回路と第1の本数の信号線で接続され、上記第1信号を受けてカウント値を増加させ、上記第2信号を受けてカウント値を減少させて上記インピーダンスコードを生成する複数の第1カウンタからなり、
上記複数の第1カウンタは、出力インピーダンスを制御する出力回路に上記第1の本数より多い第2の本数の信号線でそれぞれ接続され、かつ出力インピーダンスを制御する出力回路に隣接してそれぞれ配置され、
上記1つの第1インピーダンス比較回路で形成された上記第1信号と第2信号が上記複数の第1カウンタに供給されてなることを特徴とする半導体集積回路装置。 - 第1インピーダンスコードにより出力インピーダンスが可変にされる複数の出力回路と、
外部端子に接続された第1抵抗素子に対応して上記第1インピーダンスコードを生成する第1インピーダンス制御回路とを備え、
上記第1インピーダンス制御回路は、上記第1抵抗素子と上記出力回路と同等に形成されレプリカ回路とのインピーダンス比較を行い、上記出力インピーダンスを増加させる第1信号と、出力インピーダンスを減少させる第2信号とを形成する第1インピーダンス比較回路と、上記1つの第1インピーダンス比較回路と第1の本数の配線で接続され、上記第1信号を受けてカウント値を増加させ、上記第2信号を受けてカウント値を減少させて上記インピーダンスコードを生成する複数の第1カウンタとを有し、
上記第1インピーダンス比較回路は、上記複数の複数の第1カウンタに対し共通に設けられ、
上記複数の第1カウンタは、出力インピーダンスを制御する関係にある出力回路に上記第1の本数より多い第2の本数の配線でそれぞれ接続され、かつ出力インピーダンスを制御する関係にある出力回路に隣接してそれぞれ配置され、
上記第1インピーダンス比較回路で上記第1信号と第2信号が上記複数の第1カウンタに供給されてなることを特徴とする半導体集積回路装置。 - 上記複数の出力回路は、出力回路間の距離が、制御関係にある出力回路と第1カウンタとの距離に比べ、長いものを有することを特徴とする、請求項1または2に記載の半導体集積回路装置。
- 前記半導体集積回路装置は、四角形のチップであり、
前記複数の出力回路は、前記四角形の複数の辺に沿って分散して配置されていることを特徴とする請求項3に記載の半導体集積回路装置。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003274771A JP4201128B2 (ja) | 2003-07-15 | 2003-07-15 | 半導体集積回路装置 |
TW093119602A TW200514351A (en) | 2003-07-15 | 2004-06-30 | Semiconductor integrated circuit device |
US10/889,037 US7038486B2 (en) | 2003-07-15 | 2004-07-13 | Semiconductor integrated circuit device |
KR1020040054624A KR20050008501A (ko) | 2003-07-15 | 2004-07-14 | 반도체 집적 회로 장치 |
CNA2004100716075A CN1578143A (zh) | 2003-07-15 | 2004-07-15 | 半导体集成电路器件 |
US11/375,109 US7323901B2 (en) | 2003-07-15 | 2006-03-15 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003274771A JP4201128B2 (ja) | 2003-07-15 | 2003-07-15 | 半導体集積回路装置 |
Related Child Applications (1)
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JP2008222996A Division JP2009022029A (ja) | 2008-09-01 | 2008-09-01 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
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JP2005039549A JP2005039549A (ja) | 2005-02-10 |
JP4201128B2 true JP4201128B2 (ja) | 2008-12-24 |
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JP2003274771A Expired - Fee Related JP4201128B2 (ja) | 2003-07-15 | 2003-07-15 | 半導体集積回路装置 |
Country Status (5)
Country | Link |
---|---|
US (2) | US7038486B2 (ja) |
JP (1) | JP4201128B2 (ja) |
KR (1) | KR20050008501A (ja) |
CN (1) | CN1578143A (ja) |
TW (1) | TW200514351A (ja) |
Families Citing this family (90)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100583636B1 (ko) * | 2003-08-19 | 2006-05-26 | 삼성전자주식회사 | 단일의 기준 저항기를 이용하여 종결 회로 및 오프-칩구동 회로의 임피던스를 제어하는 장치 |
JP4086757B2 (ja) * | 2003-10-23 | 2008-05-14 | Necエレクトロニクス株式会社 | 半導体集積回路の入出力インターフェース回路 |
KR100610007B1 (ko) * | 2004-06-14 | 2006-08-08 | 삼성전자주식회사 | 임피던스 랜지 시프팅 기능을 갖는 반도체 장치의프로그래머블 임피던스 콘트롤 회로 및 그에 따른임피던스 랜지 시프팅 방법 |
US7888962B1 (en) | 2004-07-07 | 2011-02-15 | Cypress Semiconductor Corporation | Impedance matching circuit |
US7746096B1 (en) * | 2004-08-03 | 2010-06-29 | Cypress Semiconductor Corporation | Impedance buffer and method |
US7961000B1 (en) * | 2004-09-01 | 2011-06-14 | Cypress Semiconductor Corporation | Impedance matching circuit and method |
DE102004044422B3 (de) * | 2004-09-14 | 2006-03-30 | Infineon Technologies Ag | Kalibrierungsschaltung für eine Treibersteuerschaltung und Treibersteuerschaltung |
KR100703728B1 (ko) * | 2005-01-11 | 2007-04-05 | 삼성전자주식회사 | 전자 기기 |
US7613237B1 (en) * | 2005-01-13 | 2009-11-03 | Advanced Micro Devices, Inc. | Built-in test feature to facilitate system level stress testing of a high-speed serial link that uses a forwarding clock |
JP4159553B2 (ja) * | 2005-01-19 | 2008-10-01 | エルピーダメモリ株式会社 | 半導体装置の出力回路及びこれを備える半導体装置、並びに、出力回路の特性調整方法 |
US7167020B2 (en) * | 2005-01-20 | 2007-01-23 | Hewlett-Packard Development Company, L.P. | Apparatus and method of tuning a digitally controlled input/output driver |
US7221193B1 (en) * | 2005-01-20 | 2007-05-22 | Altera Corporation | On-chip termination with calibrated driver strength |
JP2006270331A (ja) * | 2005-03-23 | 2006-10-05 | Nec Corp | インピーダンス調整回路及び集積回路装置 |
KR100575006B1 (ko) * | 2005-04-12 | 2006-04-28 | 삼성전자주식회사 | Ocd 회로와 odt 회로를 제어할 수 있는 반도체 장치및 제어 방법 |
US7391221B2 (en) * | 2005-06-24 | 2008-06-24 | Hewlett-Packard Development Company, L.P. | On-die impedance calibration |
JP2007006277A (ja) * | 2005-06-24 | 2007-01-11 | Nec Electronics Corp | インピーダンス制御回路およびインピーダンス制御方法 |
JP4618600B2 (ja) * | 2005-10-17 | 2011-01-26 | エルピーダメモリ株式会社 | キャリブレーション回路及びこれを備えた半導体装置 |
US8036846B1 (en) | 2005-10-20 | 2011-10-11 | Cypress Semiconductor Corporation | Variable impedance sense architecture and method |
US7626416B2 (en) * | 2005-12-12 | 2009-12-01 | Micron Technology, Inc. | Method and apparatus for high resolution ZQ calibration |
JP2007208785A (ja) * | 2006-02-03 | 2007-08-16 | Alps Electric Co Ltd | スプリッタ回路 |
KR100738961B1 (ko) * | 2006-02-22 | 2007-07-12 | 주식회사 하이닉스반도체 | 반도체 메모리의 출력 드라이빙 장치 |
JP5527918B2 (ja) * | 2006-03-28 | 2014-06-25 | ピーエスフォー ルクスコ エスエイアールエル | 半導体集積回路装置及びその試験方法 |
US7420386B2 (en) * | 2006-04-06 | 2008-09-02 | Altera Corporation | Techniques for providing flexible on-chip termination control on integrated circuits |
US7417452B1 (en) * | 2006-08-05 | 2008-08-26 | Altera Corporation | Techniques for providing adjustable on-chip termination impedance |
US7423450B2 (en) * | 2006-08-22 | 2008-09-09 | Altera Corporation | Techniques for providing calibrated on-chip termination impedance |
JP4205744B2 (ja) | 2006-08-29 | 2009-01-07 | エルピーダメモリ株式会社 | キャリブレーション回路及びこれを備える半導体装置、並びに、半導体装置の出力特性調整方法 |
JP4159587B2 (ja) * | 2006-08-29 | 2008-10-01 | エルピーダメモリ株式会社 | 半導体装置の出力回路及びこれを備える半導体装置 |
JP2008072460A (ja) | 2006-09-14 | 2008-03-27 | Renesas Technology Corp | 半導体装置およびインピーダンス調整方法 |
KR100772533B1 (ko) | 2006-09-27 | 2007-11-01 | 주식회사 하이닉스반도체 | 온 다이 터미네이션 회로 및 그의 구동 방법 |
JP4891029B2 (ja) * | 2006-11-02 | 2012-03-07 | ルネサスエレクトロニクス株式会社 | 半導体集積回路 |
KR100808598B1 (ko) | 2006-12-27 | 2008-03-03 | 주식회사 하이닉스반도체 | 데이타 출력 드라이버 |
US7443193B1 (en) | 2006-12-30 | 2008-10-28 | Altera Corporation | Techniques for providing calibrated parallel on-chip termination impedance |
US7642809B2 (en) * | 2007-02-06 | 2010-01-05 | Rapid Bridge Llc | Die apparatus having configurable input/output and control method thereof |
KR100862316B1 (ko) * | 2007-03-08 | 2008-10-13 | 주식회사 하이닉스반도체 | 반도체 메모리장치, 반도체 메모리장치의 zq캘리브래이션동작 제어회로 및 반도체 메모리장치의 zq캘리브래이션방법 |
KR100821585B1 (ko) * | 2007-03-12 | 2008-04-15 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 온 다이 터미네이션 회로 |
TWI339494B (en) | 2007-03-19 | 2011-03-21 | Chimei Innolux Corp | Impedance matching circuit and impedance matching method and personal computer using the impedance matching circuit |
CN101272134B (zh) * | 2007-03-23 | 2011-08-31 | 群康科技(深圳)有限公司 | 阻抗匹配电路、阻抗匹配方法和个人电脑 |
JP5495477B2 (ja) * | 2007-04-23 | 2014-05-21 | ピーエスフォー ルクスコ エスエイアールエル | 出力インピーダンス調節回路を備えた半導体装置及び出力インピーダンスの試験方法 |
JP4934522B2 (ja) * | 2007-06-22 | 2012-05-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR100861373B1 (ko) * | 2007-06-27 | 2008-10-02 | 주식회사 하이닉스반도체 | 스큐신호 생성회로 및 이를 이용한 반도체 메모리 장치 |
KR100861308B1 (ko) | 2007-06-29 | 2008-10-01 | 주식회사 하이닉스반도체 | 온 다이 터미네이션 장치 |
WO2009042236A1 (en) * | 2007-09-27 | 2009-04-02 | Cypress Semiconductor Corporation | Circuits and methods for programming integrated circuit input and output impedance |
JP4966803B2 (ja) * | 2007-09-28 | 2012-07-04 | 株式会社日立製作所 | 半導体回路およびそれを用いた計算機ならびに通信装置 |
KR100863535B1 (ko) * | 2007-11-02 | 2008-10-15 | 주식회사 하이닉스반도체 | 온 다이 터미네이션 장치 및 이를 포함하는 반도체메모리장치 |
JP5059580B2 (ja) * | 2007-12-20 | 2012-10-24 | ルネサスエレクトロニクス株式会社 | 終端回路 |
JP5006231B2 (ja) * | 2008-02-26 | 2012-08-22 | ルネサスエレクトロニクス株式会社 | インピーダンス調整回路 |
US20090248945A1 (en) * | 2008-03-31 | 2009-10-01 | Navindra Navaratnam | Noise reducing methods and circuits |
JP5157607B2 (ja) | 2008-04-11 | 2013-03-06 | 日本電気株式会社 | 半導体装置及び半導体装置のインピーダンス調整方法 |
JP5675035B2 (ja) * | 2008-05-22 | 2015-02-25 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | Zqキャリブレーション回路 |
US7919986B2 (en) * | 2008-08-21 | 2011-04-05 | Texas Instruments Incorporated | Power up biasing in a system having multiple input biasing modes |
JP5584401B2 (ja) * | 2008-08-23 | 2014-09-03 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びこれを備えるデータ処理システム |
KR20100043971A (ko) * | 2008-10-21 | 2010-04-29 | 삼성전자주식회사 | 출력신호의 전압 스윙을 조절할 수 있는 출력 회로, 이를 포함하는 반도체 장치, 및 반도체 장치들을 포함하는 통신 시스템 |
JP2010219751A (ja) * | 2009-03-16 | 2010-09-30 | Elpida Memory Inc | 半導体装置 |
US7940079B2 (en) * | 2009-03-27 | 2011-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and methods for providing impedance of driver to drive data |
US8253440B2 (en) * | 2009-08-31 | 2012-08-28 | Intel Corporation | Methods and systems to calibrate push-pull drivers |
JP2011101143A (ja) * | 2009-11-05 | 2011-05-19 | Elpida Memory Inc | 半導体装置及びそのシステムとキャリブレーション方法 |
US7973553B1 (en) * | 2010-03-11 | 2011-07-05 | Altera Corporation | Techniques for on-chip termination |
US9251873B1 (en) | 2010-05-20 | 2016-02-02 | Kandou Labs, S.A. | Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications |
KR101138834B1 (ko) * | 2010-05-25 | 2012-05-10 | 에스케이하이닉스 주식회사 | 임피던스 코드 생성회로 및 이를 포함하는 반도체 장치, 터미네이션 임피던스 값 설정방법 |
JP2012049838A (ja) * | 2010-08-27 | 2012-03-08 | Elpida Memory Inc | 半導体装置およびその特性調整方法 |
KR101166643B1 (ko) * | 2010-09-07 | 2012-07-23 | 에스케이하이닉스 주식회사 | 데이터 출력 회로 |
KR101086884B1 (ko) * | 2010-09-30 | 2011-11-25 | 주식회사 하이닉스반도체 | 임피던스 제어신호 발생 회로 및 반도체 회로의 임피던스 제어 방법 |
JP5618772B2 (ja) * | 2010-11-11 | 2014-11-05 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
JP5512498B2 (ja) * | 2010-11-29 | 2014-06-04 | 株式会社東芝 | 半導体装置 |
JP2013021528A (ja) * | 2011-07-12 | 2013-01-31 | Elpida Memory Inc | 半導体装置、及び出力バッファのインピーダンスを調整する方法 |
JP2013134792A (ja) * | 2011-12-26 | 2013-07-08 | Elpida Memory Inc | 半導体装置 |
JP5757888B2 (ja) * | 2012-01-17 | 2015-08-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9078301B2 (en) | 2012-03-07 | 2015-07-07 | Novatek Microelectronics Corp. | Output stage circuit for gate driving circuit in LCD |
US9048824B2 (en) * | 2012-12-12 | 2015-06-02 | Intel Corporation | Programmable equalization with compensated impedance |
JP2014187162A (ja) * | 2013-03-22 | 2014-10-02 | Toshiba Corp | 半導体装置とそのトリミング方法 |
EP3111607B1 (en) | 2014-02-28 | 2020-04-08 | Kandou Labs SA | Clock-embedded vector signaling codes |
JP2014146409A (ja) * | 2014-03-12 | 2014-08-14 | Ps4 Luxco S A R L | 半導体集積回路装置及びその試験方法 |
US9509437B2 (en) | 2014-05-13 | 2016-11-29 | Kandou Labs, S.A. | Vector signaling code with improved noise margin |
US9912498B2 (en) * | 2015-03-05 | 2018-03-06 | Micron Technology, Inc. | Testing impedance adjustment |
US9531382B1 (en) * | 2015-09-01 | 2016-12-27 | Sandisk Technologies Llc | Search for impedance calibration |
US10056903B2 (en) * | 2016-04-28 | 2018-08-21 | Kandou Labs, S.A. | Low power multilevel driver |
US9712257B1 (en) * | 2016-08-12 | 2017-07-18 | Xilinx, Inc. | Digitally-controlled impedance control for dynamically generating drive strength for a transmitter |
KR102628533B1 (ko) * | 2016-08-16 | 2024-01-25 | 에스케이하이닉스 주식회사 | 반도체장치 및 반도체시스템 |
US10348270B2 (en) | 2016-12-09 | 2019-07-09 | Micron Technology, Inc. | Apparatuses and methods for calibrating adjustable impedances of a semiconductor device |
US10193711B2 (en) | 2017-06-22 | 2019-01-29 | Micron Technology, Inc. | Timing based arbitration methods and apparatuses for calibrating impedances of a semiconductor device |
US10615798B2 (en) | 2017-10-30 | 2020-04-07 | Micron Technology, Inc. | Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance |
TWI645414B (zh) * | 2017-11-07 | 2018-12-21 | 瑞昱半導體股份有限公司 | 記憶體控制器 |
US10467177B2 (en) | 2017-12-08 | 2019-11-05 | Kandou Labs, S.A. | High speed memory interface |
CN110070905B (zh) * | 2018-01-22 | 2022-11-01 | 长鑫存储技术有限公司 | 半导体存储器件的检测电路及检测方法 |
US10431293B1 (en) | 2018-07-23 | 2019-10-01 | Micron Technology, Inc. | Systems and methods for controlling data strobe signals during read operations |
KR102621098B1 (ko) * | 2018-07-23 | 2024-01-04 | 삼성전자주식회사 | 반도체 메모리 장치 및 이를 포함하는 메모리 시스템 |
US10747245B1 (en) | 2019-11-19 | 2020-08-18 | Micron Technology, Inc. | Apparatuses and methods for ZQ calibration |
KR102376939B1 (ko) | 2020-04-23 | 2022-03-18 | 이근형 | 고선명 오프셋 인쇄시트 및 이의 제조 방법 |
KR20210158223A (ko) * | 2020-06-23 | 2021-12-30 | 에스케이하이닉스 주식회사 | 반도체 장치 및 이의 동작 방법 |
EP4276836A4 (en) | 2022-03-25 | 2024-03-06 | Changxin Memory Technologies, Inc. | CONTROL METHOD, SEMICONDUCTOR MEMORY AND ELECTRONIC DEVICE |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10242835A (ja) | 1997-02-27 | 1998-09-11 | Hitachi Ltd | 出力回路、半導体集積回路、及び電子回路装置 |
US7124221B1 (en) * | 1999-10-19 | 2006-10-17 | Rambus Inc. | Low latency multi-level communication interface |
JP3830020B2 (ja) * | 2000-10-30 | 2006-10-04 | 株式会社日立製作所 | 半導体集積回路装置 |
EP1334593A2 (en) * | 2000-11-13 | 2003-08-13 | Primarion, Inc. | Method and circuit for pre-emphasis equalization in high speed data communications |
US6384621B1 (en) * | 2001-02-22 | 2002-05-07 | Cypress Semiconductor Corp. | Programmable transmission line impedance matching circuit |
US6535047B2 (en) * | 2001-05-17 | 2003-03-18 | Intel Corporation | Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation |
US6545522B2 (en) * | 2001-05-17 | 2003-04-08 | Intel Corporation | Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting |
JP3788928B2 (ja) * | 2001-11-01 | 2006-06-21 | 株式会社ルネサステクノロジ | 抵抗可変器 |
KR100495660B1 (ko) * | 2002-07-05 | 2005-06-16 | 삼성전자주식회사 | 온-다이 종결 회로를 구비한 반도체 집적 회로 장치 |
US6842035B2 (en) * | 2002-12-31 | 2005-01-11 | Intel Corporation | Apparatus and method for bus signal termination compensation during detected quiet cycle |
JP4277979B2 (ja) * | 2003-01-31 | 2009-06-10 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
JP4428504B2 (ja) * | 2003-04-23 | 2010-03-10 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
US6894529B1 (en) * | 2003-07-09 | 2005-05-17 | Integrated Device Technology, Inc. | Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control |
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US20060158216A1 (en) | 2006-07-20 |
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US7323901B2 (en) | 2008-01-29 |
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