JP3911901B2 - Ｓｏｉウエーハおよびｓｏｉウエーハの製造方法 - Google Patents

Ｓｏｉウエーハおよびｓｏｉウエーハの製造方法 Download PDF

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Publication number
JP3911901B2
JP3911901B2 JP10269899A JP10269899A JP3911901B2 JP 3911901 B2 JP3911901 B2 JP 3911901B2 JP 10269899 A JP10269899 A JP 10269899A JP 10269899 A JP10269899 A JP 10269899A JP 3911901 B2 JP3911901 B2 JP 3911901B2
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JP
Japan
Prior art keywords
wafer
oxide film
soi
heat treatment
surface roughness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP10269899A
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English (en)
Japanese (ja)
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JP2000294470A (ja
Inventor
順一郎 降籏
清 三谷
徳弘 小林
昌次 秋山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
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Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP10269899A priority Critical patent/JP3911901B2/ja
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Priority to PCT/JP2000/002074 priority patent/WO2000062343A1/fr
Priority to KR1020007013961A priority patent/KR100688629B1/ko
Priority to US09/701,280 priority patent/US6461939B1/en
Priority to EP11008509A priority patent/EP2413352A3/fr
Priority to EP00913020A priority patent/EP1100127A4/fr
Priority to TW89106452A priority patent/TW575902B/zh
Publication of JP2000294470A publication Critical patent/JP2000294470A/ja
Application granted granted Critical
Publication of JP3911901B2 publication Critical patent/JP3911901B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Recrystallisation Techniques (AREA)
JP10269899A 1999-04-09 1999-04-09 Ｓｏｉウエーハおよびｓｏｉウエーハの製造方法 Expired - Fee Related JP3911901B2 (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP10269899A JP3911901B2 (ja) 1999-04-09 1999-04-09 Ｓｏｉウエーハおよびｓｏｉウエーハの製造方法
KR1020007013961A KR100688629B1 (ko) 1999-04-09 2000-03-31 Ｓｏｉ웨이퍼 및 그 제조방법
US09/701,280 US6461939B1 (en) 1999-04-09 2000-03-31 SOI wafers and methods for producing SOI wafer
EP11008509A EP2413352A3 (fr) 1999-04-09 2000-03-31 Plaquette a silicium sur isolant et procédé de production de plaquette à silicium sur isolant
PCT/JP2000/002074 WO2000062343A1 (fr) 1999-04-09 2000-03-31 Plaquette a silicium sur isolant et procede de production de plaquette a silicium sur isolant
EP00913020A EP1100127A4 (fr) 1999-04-09 2000-03-31 Plaquette a silicium sur isolant et procede de production de plaquette a silicium sur isolant
TW89106452A TW575902B (en) 1999-04-09 2000-04-07 SOI wafer and manufacturing method of SOI wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10269899A JP3911901B2 (ja) 1999-04-09 1999-04-09 Ｓｏｉウエーハおよびｓｏｉウエーハの製造方法

Publications (2)

Publication Number Publication Date
JP2000294470A JP2000294470A (ja) 2000-10-20
JP3911901B2 true JP3911901B2 (ja) 2007-05-09

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP10269899A Expired - Fee Related JP3911901B2 (ja) 1999-04-09 1999-04-09 Ｓｏｉウエーハおよびｓｏｉウエーハの製造方法

Country Status (6)

Country Link
US (1) US6461939B1 (fr)
EP (2) EP1100127A4 (fr)
JP (1) JP3911901B2 (fr)
KR (1) KR100688629B1 (fr)
TW (1) TW575902B (fr)
WO (1) WO2000062343A1 (fr)

Families Citing this family (32)

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US6717212B2 (en) * 2001-06-12 2004-04-06 Advanced Micro Devices, Inc. Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure
FR2827078B1 (fr) * 2001-07-04 2005-02-04 Soitec Silicon On Insulator Procede de diminution de rugosite de surface
JP3808763B2 (ja) * 2001-12-14 2006-08-16 株式会社東芝 半導体メモリ装置およびその製造方法
JP2003204048A (ja) * 2002-01-09 2003-07-18 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
FR2874455B1 (fr) * 2004-08-19 2008-02-08 Soitec Silicon On Insulator Traitement thermique avant collage de deux plaquettes
FR2839385B1 (fr) * 2002-05-02 2004-07-23 Soitec Silicon On Insulator Procede de decollement de couches de materiau
KR100465527B1 (ko) * 2002-11-21 2005-01-13 주식회사 실트론 Ｓｏｉ 웨이퍼의 결함 제거 및 표면 경면화 방법
FR2847714B1 (fr) 2002-11-27 2005-02-18 Soitec Silicon On Insulator Procede et dispositif de recuit de tranche de semiconducteur
US7190051B2 (en) * 2003-01-17 2007-03-13 Second Sight Medical Products, Inc. Chip level hermetic and biocompatible electronics package using SOI wafers
TW200428637A (en) 2003-01-23 2004-12-16 Shinetsu Handotai Kk SOI wafer and production method thereof
JP2004259970A (ja) * 2003-02-26 2004-09-16 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
US7256104B2 (en) 2003-05-21 2007-08-14 Canon Kabushiki Kaisha Substrate manufacturing method and substrate processing apparatus
JP2005005674A (ja) * 2003-05-21 2005-01-06 Canon Inc 基板製造方法及び基板処理装置
FR2858715B1 (fr) 2003-08-04 2005-12-30 Soitec Silicon On Insulator Procede de detachement de couche de semiconducteur
JP4830290B2 (ja) 2004-11-30 2011-12-07 信越半導体株式会社 直接接合ウェーハの製造方法
JP4876442B2 (ja) * 2005-06-13 2012-02-15 株式会社Ｓｕｍｃｏ Ｓｉｍｏｘウェーハの製造方法およびｓｉｍｏｘウェーハ
US7691730B2 (en) * 2005-11-22 2010-04-06 Corning Incorporated Large area semiconductor on glass insulator
JP4715470B2 (ja) * 2005-11-28 2011-07-06 株式会社Ｓｕｍｃｏ 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ
JP2006191125A (ja) * 2006-01-27 2006-07-20 Ftl:Kk Ｓｏｉウェーハの製造方法
JP5061489B2 (ja) * 2006-04-05 2012-10-31 株式会社Ｓｕｍｃｏ Ｓｉｍｏｘウェーハの製造方法
KR100765639B1 (ko) * 2006-07-03 2007-10-10 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 웨이퍼의 표면 거칠기 개선 방법
US7575988B2 (en) 2006-07-11 2009-08-18 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating a hybrid substrate
FR2903808B1 (fr) * 2006-07-11 2008-11-28 Soitec Silicon On Insulator Procede de collage direct de deux substrats utilises en electronique, optique ou opto-electronique
FR2903809B1 (fr) 2006-07-13 2008-10-17 Soitec Silicon On Insulator Traitement thermique de stabilisation d'interface e collage.
JP5167654B2 (ja) * 2007-02-26 2013-03-21 信越半導体株式会社 シリコン単結晶ウエーハの製造方法
JP5143477B2 (ja) * 2007-05-31 2013-02-13 信越化学工業株式会社 Ｓｏｉウエーハの製造方法
EP2075830A3 (fr) * 2007-10-11 2011-01-19 Sumco Corporation Procédé de production de plaquette fixée
EP2261954B1 (fr) * 2008-04-01 2020-01-22 Shin-Etsu Chemical Co., Ltd. Procede de fabrication d'un substrat silicium sur isolant
CN103311110B (zh) 2012-03-12 2016-08-31 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法，晶体管的形成方法
CN108780776B (zh) 2015-11-20 2023-09-29 环球晶圆股份有限公司 使半导体表面平整的制造方法
JP6443394B2 (ja) * 2016-06-06 2018-12-26 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
CN113284797B (zh) * 2020-02-20 2022-10-18 长鑫存储技术有限公司 半导体存储器的制作方法

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JPS6050970A (ja) 1983-08-31 1985-03-22 Toshiba Corp 半導体圧力変換器
JP2766992B2 (ja) 1989-07-14 1998-06-18 富士通株式会社 半導体装置の製造方法
JPH03109731A (ja) 1989-09-25 1991-05-09 Seiko Instr Inc 半導体基板の製造方法
JP2801704B2 (ja) 1989-12-11 1998-09-21 株式会社東芝 半導体基板の製造方法
JP2850502B2 (ja) 1990-07-20 1999-01-27 富士通株式会社 Ｓｏｉ基板の製造方法
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JPH05205987A (ja) 1992-01-29 1993-08-13 Fujitsu Ltd 半導体装置の製造方法
DE69333619T2 (de) 1992-01-30 2005-09-29 Canon K.K. Herstellungsverfahren für Halbleitersubstrate
JP2994837B2 (ja) 1992-01-31 1999-12-27 キヤノン株式会社 半導体基板の平坦化方法、半導体基板の作製方法、及び半導体基板
JPH06112451A (ja) * 1992-09-29 1994-04-22 Nagano Denshi Kogyo Kk Ｓｏｉ基板の製造方法
JPH0750234A (ja) 1993-08-04 1995-02-21 Komatsu Electron Metals Co Ltd 半導体ウェーハ製造装置および製造方法
JPH07183477A (ja) 1993-12-22 1995-07-21 Nec Corp 半導体基板の製造方法
JPH07220987A (ja) 1994-01-28 1995-08-18 Nippon Telegr & Teleph Corp <Ntt> 単結晶Ｓｉ基板とその製造方法
JP3036619B2 (ja) 1994-03-23 2000-04-24 コマツ電子金属株式会社 Ｓｏｉ基板の製造方法およびｓｏｉ基板
JPH07283382A (ja) * 1994-04-12 1995-10-27 Sony Corp シリコン基板のはり合わせ方法
JPH08330198A (ja) 1995-05-29 1996-12-13 Toshiba Microelectron Corp 半導体装置の製造方法
JPH1084101A (ja) 1996-09-06 1998-03-31 Shin Etsu Handotai Co Ltd Ｓｏｉ基板の作製方法およびｓｏｉ基板
JP2933050B2 (ja) * 1997-02-03 1999-08-09 サンケン電気株式会社 半導体基体及び半導体装置の製造方法
JPH10275905A (ja) 1997-03-31 1998-10-13 Mitsubishi Electric Corp シリコンウェーハの製造方法およびシリコンウェーハ
US6191007B1 (en) * 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
US6171982B1 (en) * 1997-12-26 2001-01-09 Canon Kabushiki Kaisha Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same
FR2777115B1 (fr) * 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
JP3500063B2 (ja) * 1998-04-23 2004-02-23 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
JP3746153B2 (ja) * 1998-06-09 2006-02-15 信越半導体株式会社 シリコンウエーハの熱処理方法
JP2000114501A (ja) 1998-10-01 2000-04-21 Komatsu Electronic Metals Co Ltd Ｓｏｉウェハの製造方法

Also Published As

Publication number Publication date
US6461939B1 (en) 2002-10-08
EP1100127A1 (fr) 2001-05-16
KR20010025120A (ko) 2001-03-26
EP2413352A2 (fr) 2012-02-01
KR100688629B1 (ko) 2007-03-09
JP2000294470A (ja) 2000-10-20
WO2000062343A1 (fr) 2000-10-19
EP2413352A3 (fr) 2012-03-07
EP1100127A4 (fr) 2002-04-24
TW575902B (en) 2004-02-11

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