JP4876442B2 - Simoxウェーハの製造方法およびsimoxウェーハ - Google Patents
Simoxウェーハの製造方法およびsimoxウェーハ Download PDFInfo
- Publication number
- JP4876442B2 JP4876442B2 JP2005172715A JP2005172715A JP4876442B2 JP 4876442 B2 JP4876442 B2 JP 4876442B2 JP 2005172715 A JP2005172715 A JP 2005172715A JP 2005172715 A JP2005172715 A JP 2005172715A JP 4876442 B2 JP4876442 B2 JP 4876442B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- oxygen
- wafer
- simox
- temperature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000001301 oxygen Substances 0.000 claims description 68
- 229910052760 oxygen Inorganic materials 0.000 claims description 68
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 42
- 238000010438 heat treatment Methods 0.000 claims description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- -1 oxygen ions Chemical class 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 19
- 239000007789 gas Substances 0.000 claims description 13
- 238000002844 melting Methods 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 48
- 238000005468 ion implantation Methods 0.000 description 20
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 14
- 238000002513 implantation Methods 0.000 description 14
- 125000004429 atom Chemical group 0.000 description 13
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 229910052786 argon Inorganic materials 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000002245 particle Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000007689 inspection Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 239000002244 precipitate Substances 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/42—Bombardment with radiation
- H01L21/423—Bombardment with radiation with high-energy radiation
- H01L21/425—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Description
2 酸素の高濃度層
3 アモルファス層
4 BOX層
5 酸化膜
6 SOI層
Claims (2)
- シリコンウェーハを300℃以上に加熱して酸素イオンを注入し、前記シリコンウェーハの内部に酸素の高濃度層を形成する第1の工程と、該第1の工程で得られた前記シリコンウェーハを300℃未満に冷却して酸素イオンを注入し、前記シリコンウェーハにアモルファス層を形成する第2の工程と、該第2の工程で得られた前記シリコンウェーハを熱処理して埋め込み酸化膜を形成する第3の工程とを備えるSIMOXウェーハの製造方法において、
前記第3の工程は、酸素分圧比が5%以上の混合ガス雰囲気下、1280℃〜1320℃の温度域で所定時間かけて熱処理した後、1350℃以上シリコンの融点未満の温度域まで昇温し、該温度域で酸素分圧比が5%未満の混合ガス雰囲気下、所定時間保持することを特徴とするSIMOXウェーハの製造方法。 - 前記第3の工程は、直線的又は段階的に昇温させることを特徴とする請求項1に記載のSIMOXウェーハの製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005172715A JP4876442B2 (ja) | 2005-06-13 | 2005-06-13 | Simoxウェーハの製造方法およびsimoxウェーハ |
US11/450,562 US7514343B2 (en) | 2005-06-13 | 2006-06-08 | Method for manufacturing SIMOX wafer and SIMOX wafer |
TW095120710A TWI321335B (en) | 2005-06-13 | 2006-06-09 | Method for manufacturing simox wafer and simox wafer |
EP06011986A EP1734575A1 (en) | 2005-06-13 | 2006-06-09 | Method for manufacturing simox wafer and simox wafer |
KR1020060052116A KR100775799B1 (ko) | 2005-06-13 | 2006-06-09 | Simox 웨이퍼의 제조 방법 및 simox 웨이퍼 |
US12/389,299 US20090152671A1 (en) | 2005-06-13 | 2009-02-19 | Method for manufacturing simox wafer and simox wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005172715A JP4876442B2 (ja) | 2005-06-13 | 2005-06-13 | Simoxウェーハの製造方法およびsimoxウェーハ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006351632A JP2006351632A (ja) | 2006-12-28 |
JP4876442B2 true JP4876442B2 (ja) | 2012-02-15 |
Family
ID=36950156
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005172715A Expired - Fee Related JP4876442B2 (ja) | 2005-06-13 | 2005-06-13 | Simoxウェーハの製造方法およびsimoxウェーハ |
Country Status (5)
Country | Link |
---|---|
US (2) | US7514343B2 (ja) |
EP (1) | EP1734575A1 (ja) |
JP (1) | JP4876442B2 (ja) |
KR (1) | KR100775799B1 (ja) |
TW (1) | TWI321335B (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060228492A1 (en) * | 2005-04-07 | 2006-10-12 | Sumco Corporation | Method for manufacturing SIMOX wafer |
JP5061489B2 (ja) * | 2006-04-05 | 2012-10-31 | 株式会社Sumco | Simoxウェーハの製造方法 |
JP2009054837A (ja) * | 2007-08-28 | 2009-03-12 | Sumco Corp | Simoxウェーハ製造方法およびsimoxウェーハ |
JP2011029618A (ja) * | 2009-06-25 | 2011-02-10 | Sumco Corp | Simoxウェーハの製造方法、simoxウェーハ |
US8168507B2 (en) | 2009-08-21 | 2012-05-01 | International Business Machines Corporation | Structure and method of forming enhanced array device isolation for implanted plate EDRAM |
WO2011118205A1 (ja) * | 2010-03-26 | 2011-09-29 | 株式会社Sumco | Soiウェーハの製造方法 |
JP6443394B2 (ja) * | 2016-06-06 | 2018-12-26 | 信越半導体株式会社 | 貼り合わせsoiウェーハの製造方法 |
US10269617B2 (en) | 2016-06-22 | 2019-04-23 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising an isolation region |
US10651281B1 (en) * | 2018-12-03 | 2020-05-12 | Globalfoundries Inc. | Substrates with self-aligned buried dielectric and polycrystalline layers |
US11114466B2 (en) | 2020-01-28 | 2021-09-07 | Globalfoundries U.S. Inc. | IC products formed on a substrate having localized regions of high resistivity and methods of making such IC products |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1255764B (it) | 1992-05-15 | 1995-11-15 | Enichem | Struttura soi con ossido sottile e profondo ottenuta per impiantazioneionica ad alta energia e successivi trattamenti termici. |
JP3036619B2 (ja) * | 1994-03-23 | 2000-04-24 | コマツ電子金属株式会社 | Soi基板の製造方法およびsoi基板 |
JP3204855B2 (ja) * | 1994-09-30 | 2001-09-04 | 新日本製鐵株式会社 | 半導体基板の製造方法 |
KR100195833B1 (ko) * | 1995-12-07 | 1999-06-15 | 윤종용 | 팩시밀리에서 자체진단 구현방법 |
JP2856157B2 (ja) | 1996-07-16 | 1999-02-10 | 日本電気株式会社 | 半導体装置の製造方法 |
US6043166A (en) * | 1996-12-03 | 2000-03-28 | International Business Machines Corporation | Silicon-on-insulator substrates using low dose implantation |
JPH10223551A (ja) * | 1997-02-12 | 1998-08-21 | Nec Corp | Soi基板の製造方法 |
US6090689A (en) * | 1998-03-04 | 2000-07-18 | International Business Machines Corporation | Method of forming buried oxide layers in silicon |
US5930643A (en) * | 1997-12-22 | 1999-07-27 | International Business Machines Corporation | Defect induced buried oxide (DIBOX) for throughput SOI |
JP3911901B2 (ja) * | 1999-04-09 | 2007-05-09 | 信越半導体株式会社 | Soiウエーハおよびsoiウエーハの製造方法 |
US6417078B1 (en) * | 2000-05-03 | 2002-07-09 | Ibis Technology Corporation | Implantation process using sub-stoichiometric, oxygen doses at different energies |
JP2002231651A (ja) * | 2001-02-02 | 2002-08-16 | Nippon Steel Corp | Simox基板およびその製造方法 |
EP1391931A4 (en) * | 2001-05-29 | 2009-04-08 | Nippon Steel Corp | SOI substrate |
US6784072B2 (en) | 2002-07-22 | 2004-08-31 | International Business Machines Corporation | Control of buried oxide in SIMOX |
JP4228676B2 (ja) * | 2002-12-06 | 2009-02-25 | 株式会社Sumco | Simoxウェーハの製造方法 |
US20050170570A1 (en) * | 2004-01-30 | 2005-08-04 | International Business Machines Corporation | High electrical quality buried oxide in simox |
-
2005
- 2005-06-13 JP JP2005172715A patent/JP4876442B2/ja not_active Expired - Fee Related
-
2006
- 2006-06-08 US US11/450,562 patent/US7514343B2/en not_active Expired - Fee Related
- 2006-06-09 TW TW095120710A patent/TWI321335B/zh not_active IP Right Cessation
- 2006-06-09 EP EP06011986A patent/EP1734575A1/en not_active Withdrawn
- 2006-06-09 KR KR1020060052116A patent/KR100775799B1/ko not_active IP Right Cessation
-
2009
- 2009-02-19 US US12/389,299 patent/US20090152671A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20060281233A1 (en) | 2006-12-14 |
KR20060129957A (ko) | 2006-12-18 |
JP2006351632A (ja) | 2006-12-28 |
EP1734575A1 (en) | 2006-12-20 |
US7514343B2 (en) | 2009-04-07 |
US20090152671A1 (en) | 2009-06-18 |
TWI321335B (en) | 2010-03-01 |
KR100775799B1 (ko) | 2007-11-12 |
TW200705555A (en) | 2007-02-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4876442B2 (ja) | Simoxウェーハの製造方法およびsimoxウェーハ | |
JP5940238B2 (ja) | シリコンウエハの製造方法 | |
JP4830290B2 (ja) | 直接接合ウェーハの製造方法 | |
JP5061489B2 (ja) | Simoxウェーハの製造方法 | |
US7727867B2 (en) | Method for manufacturing SIMOX wafer | |
JP2007005563A (ja) | Simoxウェーハの製造方法 | |
JP2007208023A (ja) | Simoxウェーハの製造方法 | |
JP2010027959A (ja) | 高抵抗simoxウェーハの製造方法 | |
JPS59124136A (ja) | 半導体ウエハの処理方法 | |
JP6812992B2 (ja) | Soiウェーハの製造方法 | |
JP4228676B2 (ja) | Simoxウェーハの製造方法 | |
US20060228492A1 (en) | Method for manufacturing SIMOX wafer | |
WO2014192207A1 (ja) | 貼り合わせウェーハの製造方法 | |
US7799660B2 (en) | Method for manufacturing SOI substrate | |
JP2008028415A (ja) | Soiウエーハの製造方法及びsoiウエーハ | |
JPH1041241A (ja) | 半導体装置の製造方法 | |
US9779964B2 (en) | Thermal processing method for wafer | |
US9793138B2 (en) | Thermal processing method for wafer | |
JP2006108404A (ja) | Soiウェーハの製造方法 | |
JP4598241B2 (ja) | Simox基板の製造方法 | |
JPS60176241A (ja) | 半導体基板の製造方法 | |
JP2008159868A (ja) | Simox基板の製造方法 | |
WO2011118205A1 (ja) | Soiウェーハの製造方法 | |
JP2002246458A (ja) | Simox基板の製造方法 | |
JP2006261192A (ja) | シリコンウェーハの処理方法及び該方法を実施する装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20071114 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110621 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110623 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110817 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20111101 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20111114 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20141209 Year of fee payment: 3 |
|
LAPS | Cancellation because of no payment of annual fees |