JP2022177212A - 貫通電極基板及び半導体装置 - Google Patents
貫通電極基板及び半導体装置 Download PDFInfo
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- JP2022177212A JP2022177212A JP2022150556A JP2022150556A JP2022177212A JP 2022177212 A JP2022177212 A JP 2022177212A JP 2022150556 A JP2022150556 A JP 2022150556A JP 2022150556 A JP2022150556 A JP 2022150556A JP 2022177212 A JP2022177212 A JP 2022177212A
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Abstract
Description
本開示の一実施形態に係るインターポーザーは、絶縁層を、金属等を含む導電層で挟み込んだ構造を有する。図1は、本開示の第1実施形態に係るインターポーザー10を示す概略平面図である。図2は、本開示の第1実施形態におけるインターポーザー10を示す概略断面図(図1のA-A線断面図)である。図3は、本開示の第1実施形態に係るインターポーザー10に含まれるキャパシタ100を示す概略断面図(図1のB-B線断面図)である。なお、図1及び図3においては、基板11、第1導電層12、第1絶縁層13及び第2導電層14の位置関係がわかりやすくなるように、一部の構成が省略されている。インターポーザー10は、例えば、絶縁層を金属で挟み込んだ構造であるMIM(Metal-Insulator-Metal)構造を有する。以下、MIM構造は、誘電体層である絶縁層を上部電極と下部電極とで挟んだキャパシタ100であるものとして説明する。この場合、第1導電層12が下部電極、第1絶縁層13が誘電体層、第2導電層14が上部電極として用いられる。
ンタル(Ta2O5)、酸化アルミニウム(Al2O3)、又は、窒化アルミニウム(AlN)、酸化ハフニウム(HfO2)、アルミニウムを添加した酸化ハフニウムを用いること
ができる。第1絶縁層13は、キャパシタ100の周囲に存在する絶縁層(例えば、樹脂層22)よりも高い比誘電率を有することが望ましい。第1絶縁層13の比誘電率は、例えば2.0~9.0、より好ましくは5.0~8.0の範囲である。なかでも比誘電率と絶縁破壊電圧の観点から窒化ケイ素(SixNy)、酸窒化ケイ素(SiOxNy)を好適に用いることができる。第1絶縁層13の厚み(後述するT1)は、50nm~800nmであってもよい。
施してもよい。これにより、第1導電層12の表面の酸化物を除去することができる。これにより、第1導電層12と第1絶縁層13との間の密着性を高めることができる。
図5は、本開示の第2実施形態に係るキャパシタ100Aを示す概略断面図である。本実施形態では、第1絶縁層13Aの第3部分13Acが、基板11の第1面11a上に広がるように延びずに、下地層17の側面17aを覆うようになっている。この構成によれば、第1絶縁層13Aの第2部分13bが第1導電層12の側面12b及び下地層17の側面17aを覆い、かつ、第2部分13bから基板11と接触するまで第1絶縁層13Aの第3部分13Acまで延びている。したがって、第1導電層12及び下地層17が、第2導電層14とショートすることを防ぐことができる。
図6は、本開示の第3実施形態に係るキャパシタ100Bを示す概略断面図である。本実施形態では、第1絶縁層13Bの第2部分13Bbが、第1部分13aから、第1導電層12の側面12bの上端12cと下端12dの間の位置まで延びている。このように、第1絶縁層13Bの第2部分13bは、第1導電層12の側面12bの全面を覆う必要はなく、第1導電層12の側面12bの少なくとも一部を覆っている構成であればよい。この構成によれば、第1絶縁層13Bの第2部分13Bbが、第1部分13aから連続して延びて第1導電層12の側面12bの一部を覆っている。したがって、第1導電層12が、第2導電層14とショートすることを防ぐことができる。
図7は、本開示の第4実施形態に係るキャパシタ100Cを示す概略断面図である。本実施形態では、下地層17Cの平面サイズが、第1導電層12の平面サイズより大きい。すなわち、下地層17Cが、第1導電層12の側面12bよりも距離D1だけ外側に拡がり、第1導電層12の側面12bよりも下地層17Cの側面17Caが外側に存在する。すなわち、下地層17Cの端部において第1導電層12に覆われていない上面17Cfが現れる。第1絶縁層13Cの第2部分13Cbが第1導電層12の側面12b、下地層17の一部(端部)の上面17Cf及び側面17Caを覆い、かつ、第2部分12Cbから基板11と接触するまで第1絶縁層13Cの第3部分13Ccまで延びている。したがって、第1導電層12及び下地層17Cが、第2導電層14とショートすることを防ぐことができる。なお、距離D1は、20nm~1000nmであることが好ましい。
図8は、本開示の第5実施形態に係るキャパシタ100Dを示す概略断面図である。本実施形態では、下地層17Dの平面サイズが、第1導電層12の平面サイズより小さい。すなわち、下地層17Dが、第1導電層12の側面12bよりも距離D2だけ内側に入り込んだ側面17Daを有する。これによって、第1導電層12、基板11及び下地層17Dによってリセス部17Dbが形成される。このリセス部17Dbと第1絶縁層13とによって、第1導電層12の下方に空間18が形成されている。第1絶縁層13の第2部分13b及び第3部分13cは、空間18の少なくとも一部を残すように配置されている。このように、空間18の少なくとも一部が空隙として残った状態でも、第1絶縁層13の第3部分13cの絶縁効果により、第1導電層12及び下地層17が、第2導電層14とショートすることを防ぐことができる。
図9は、本開示の第6実施形態に係るキャパシタ100Eを示す概略断面図である。本実施形態では、第1絶縁層13Eの第2部分13Eb及び第3部分13Ecが、リセス部17Db(図8参照)を充填するように配置されている。この構成によれば、第1絶縁層13Eの第2部分13Eb及び第3部分13Ecが、第1導電層12の下方のリセス部17Dbを埋めている。したがって、図8の構成に比べて、第1導電層12及び下地層17Dが、第2導電層14とショートすることをより効果的に防ぐことができる。また、第1絶縁層13Eがリセス部17Dbに入り込むため、第1導電層12と下地層17Dとの密着性も向上する。このようなショートの防止及び密着性の向上の観点から、下地層17Dのリセス部17Dbのサイズ、すなわち、第1絶縁層13から下地層17の側面17Daまでの距離D2は、20nm~1000nmであることが好ましい。
図10は、本開示の第7実施形態に係るキャパシタ100Fを示す概略断面図である。本実施形態では、図9の構成において、第2導電層14Fが、第1絶縁層13Eの第1部分13a、第2部分13Eb及び第3部分13Ecにわたって配置されている。この構成によれば、第2導電層14Fと第1絶縁層13Eとの密着面積が大きいので、接着性がよい。また、この構成では、第2導電層14Fと第1導電層12及び下地層17Dとの間の距離が近くなるが、第1絶縁層13Eの第2部分13Eb及び第3部分13Ecが第1導電層12の下方のリセス部17Dbを埋めているため、第1導電層12及び下地層17Dが、第2導電層14Fとショートすることを防ぐことができる。
図11は、本開示の第8実施形態に係るキャパシタ100Gを示す概略断面図である。本実施形態では、図3に示す第1実施形態のキャパシタ100において、下地層17を用いずに第1導電層12Gが形成された場合に対応する。この構成によれば、第1絶縁層13が、第2部分13bによって第1導電層12Gの側面12Gbを覆うとともに、第3部分13cによって基板11の第1面11aまで覆っている。したがって、第2導電層14の位置がずれた場合でも、第1導電層12Gが、第2導電層14とショートすることを防ぐことができる。また、第1絶縁層13の第3部分13cが、基板11の第1面11aと接触していることにより、第1絶縁層13の剥がれに対する耐性が高くなる。
図12は、本開示の第9実施形態に係るキャパシタ100Hを示す概略断面図である。本実施形態では、図5に示す第2実施形態のキャパシタ100Aにおいて、下地層17を用いずに第1導電層12Gが形成された場合に対応する。すなわち、第1絶縁層13Aの第2部分13bが、第1導電層12Gの側面12Gbの上端12Gcと下端12Gdとの間の全体を覆っている。この構成によれば、第1絶縁層13Aの第2部分13bが、第1部分13aから連続して延びて第1導電層12Gの側面12Gbを全体的に覆っている。したがって、第1導電層12Gが、第2導電層14とショートすることを防ぐことができる。
図13は、本開示の第10実施形態に係るキャパシタ100Iを示す概略断面図である。本実施形態では、図6に示す第3実施形態のキャパシタ100Bにおいて、下地層17を用いずに第1導電層12Gが形成された場合に対応する。すなわち、第1絶縁層13Bの第2部分13Bbが、第1導電層12Gの側面12Gbの上端12Gcと下端12Gdとの間の位置まで覆っている。この構成によれば、第1絶縁層13Bの第2部分13Bbが、第1部分13aから連続して延びて第1導電層12Gの側面12Gbの一部を覆っている。したがって、第1導電層12Gが、第2導電層14とショートすることを防ぐことができる。
図14は、本開示の第11実施形態に係るキャパシタ100Jを示す概略断面図である。キャパシタ100Jのように、第1導電層12の側面12b及び下地層17の側面17aを覆う絶縁層は、第1絶縁層13と異なる材料の第2絶縁層19で形成されてもよい。本実施形態では、第1絶縁層13Jは、第1導電層12と第2導電層14の間に配置された第1部分13aで構成されている。すなわち、第1絶縁層13Jは、第1導電層12の上面12aのみに配置されている。第2絶縁層19は、第1部分19a、第2部分19b及び第3部分19cを有する。第1部分19aは、第1絶縁層13Jの上に配置されている。第2部分19bは、第1部分19aから連続的に延びて第1導電層12の側面12b及び下地層17の側面17aを覆う。第3部分19cは、第2部分19bから連続的に延びて基板11の第1面11aの少なくとも一部を覆う。
図16は、本開示の第12実施形態に係るキャパシタ100Kを示す概略断面図である。キャパシタ100Kのように、複数の領域に区分されていてもよい。例えば、図16では、基板11上に、キャパシタ100K-1、100K-2、100K-3が配置されている。図16では、複数の領域が3つの場合を示しているが、複数の領域は3つに限定されない。キャパシタ100K-1とキャパシタ100K-2との間には、空間SP1が配置されている。キャパシタ100K-2とキャパシタ100K-3との間には、空間SP2が配置されている。すなわち、キャパシタ100K-2は、キャパシタ100K-1とキャパシタ100K-3との間に配置されている。
図17は、本開示の第13実施形態に係るキャパシタ100Lを示す概略断面図である。本実施形態のキャパシタ100Lは、第1導電層12Lと第1絶縁層13Lとの間に中間層26をさらに備える。中間層26は、第1導電層12Lと第1絶縁層13Lとの間の密着性を高めるための導電材料が好ましく、例えば、チタン(Ti)、窒化チタン(TiN)、ニッケル(Ni)、ニッケル-金合金(Ni-Au)などを使用することができる。中間層26の厚みは、好ましくは、20nm~200nmである。なお、中間層26は省略されてもよい。中間層26として密着性を高める導電材料を採用することで、以下で説明するリフトオフによって第2レジスト層32(図18E参照)を除去するときに、第1絶縁層13Lが剥がれにくくなる。
図20A~図20Eは、第1実施形態に係るキャパシタ100を製造する別の方法を説明する図である。製造方法が異なるため、第14実施形態として示した。図20Aは、図4Cの状態の第1面11a側の拡大図である。図20Aに示すように、基板11の第1面11aに第1導電層12が形成されている。次に、図20Bに示すように、第1導電層12の上面12a及び側面12bと、基板11の第1面11aとに第1絶縁層13を形成する。次に、図20Cに示すように、第1導電層12の上面12aに対応する第1絶縁層13の部分に第2導電層14を形成する。次に、図20Dに示すように、第2導電層14を覆い、かつ、第1絶縁層13の第2部分13bから基板11の第1面11a上に延びる第3部分13cの一部(すなわち、第1絶縁層13の裾野部分)を覆うように、レジスト層33を形成する。次に、図20Eに示すように、レジスト層33に覆われていない第1絶縁層13をエッチング又はミリング処理)等により除去する。その後、レジスト層33を除去する。これにより、図3に示すキャパシタ100を製造することができる。ここで、エッチングは、例えば、反応性イオンエッチング(RIE)が挙げられる。また、ミリング処理は、例えば、Arミリング処理が挙げられる。
次に、図22~図24を用いて、第15実施形態~第19実施形態に係るキャパシタ(第1導電層、第1絶縁層及び第2導電層)の構成について説明する。これらの図面で説明する構成は、上述した全ての実施形態におけるキャパシタの構成として適用可能である。
次に、複数のキャパシタ(MIM構造)が隣接して配置された構成について説明する。以下で説明する構成は、上述した全ての実施形態に適用可能である。図25Aは、本開示の第20実施形態に係るキャパシタ100Rの第1導電層12-1、12-2と第1絶縁層13Rとの位置関係を示す概略平面図である。図25Bは、本開示の第21実施形態に係るキャパシタ100Sの第1導電層12-1、12-2と第1絶縁層13Sとの位置関係を示す概略平面図である。図25Cは、本開示の第22実施形態に係るキャパシタ100Tの第1導電層12-1、12-2と第1絶縁層13Tとの位置関係を示す概略平面図である。これらの概略平面図は、基板11の第1面11aを上から見たときの平面図である。図25A~図25Cにおいて第2導電層14の図示は省略されている。
図27は、本開示の第23実施形態に係るキャパシタ100Pが隣接配置された場合の概略断面図である。この例は、図24Aの構成の変形例を示す。第1絶縁層13P-1上の第2導電層14P-1が、互いに分離した複数の導電部分(第1導電部分14P-1a及び第2導電部分14P-1b)から構成されてもよい。また、第1絶縁層13P-2上の第2導電層14P-2が、複数の導電部分(第1導電部分14P-2a及び第2導電部分14P-2b)から構成されてもよい。このような構成において、第2導電層14P-1の一部と第2導電層14P-2の一部とが電気的に接続されてもよい。図27の例では、第2導電層14P-1の第2導電部分14P-1bと第2導電層14P-2の第1導電部分14P-2aとが接続部24を介して接続されている。
図28は、本開示の第24実施形態に係るインターポーザー10Uに含まれるキャパシタ100U及びインダクタ27を示す概略平面図である。この概略平面図は、基板11の第1面11a側の第1導電層12Uを示す平面図である。図28において、接続部24等の一部の構成要素は省略されている。図29は、本開示の第24実施形態に係るインターポーザーを示す概略断面図(図28のD-D線断面図)である。
-10% ≦ (Th1-Th2)/Th1≦ +10%
図30は、本開示の第25実施形態に係るキャパシタ100Vを示す概略平面図である。本実施形態では、第1実施形態におけるキャパシタ100の第2導電層14が、接続部24と共用された例を示している。樹脂層22に形成されたビアホール23Vは、第1導電層12等の導電層を露出するためのビアホール23、例えば、図2のビアホール23とは別に設けられ、第1絶縁層13の第1部分13aを露出するように形成されている。この例では、ビアホール23が形成されるときに、ビアホール23Vについても形成される。また、ビアホール23に対応して接続部24が形成されるときに、ビアホール23Vにおいても接続部24Vが形成される。なお、ビアホール23とビアホール23Vは別々に形成されてもよい。また、接続部24とも接続部24Vも別々に形成されてもよい。この構造によっても、接続部24Vの下部14Vは、第1実施形態における第2導電層14と同等に機能する。なお、下部14Vは、第1絶縁層13に接する部分を含んでいる。
第26実施形態では、第1実施形態におけるインターポーザー10を用いて製造される半導体装置について説明する。
本開示は上述した実施形態に限定されるものではなく、他の様々な変形例が含まれる。例えば、上述した実施形態は本開示を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施形態の構成の一部を他の実施形態の構成に置き換えることがあり、また、ある実施形態の構成に他の実施形態の構成を加えることも可能である。また、各実施形態の構成の一部について、他の構成の追加・削除・置換をすることが可能である。以下、一部の変形例について説明する。
Claims (1)
- 第1面と前記第1面に対向する第2面とを有する基板と、
前記基板を貫通する複数の貫通電極と、
前記基板の前記第1面側に配置され、複数の前記貫通電極の少なくとも1つと電気的に接続された第1キャパシタとを有し、
前記第1キャパシタは、
前記基板の前記第1面側に配置され、前記貫通電極と電気的に接続された第1導電層と、
前記第1導電層の上に配置された絶縁層と、
前記絶縁層の上に配置された第2導電層と、を含み、
前記絶縁層は、
前記第1導電層と前記第2導電層の間に配置された第1部分と、
前記第1導電層の側面の少なくとも一部を覆う第2部分と、
を有する、貫通電極基板。
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