JPWO2017057422A1 - 薄膜型lc部品およびその実装構造 - Google Patents
薄膜型lc部品およびその実装構造 Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 105
- 239000003990 capacitor Substances 0.000 claims abstract description 104
- 239000010410 layer Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 19
- 230000008569 process Effects 0.000 claims abstract description 18
- 239000004020 conductor Substances 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 239000010408 film Substances 0.000 claims description 72
- 239000004065 semiconductor Substances 0.000 claims description 21
- 229910052454 barium strontium titanate Inorganic materials 0.000 claims description 14
- 238000009413 insulation Methods 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 22
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
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- 238000004544 sputter deposition Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
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- 238000002955 isolation Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
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- 229910052712 strontium Inorganic materials 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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Abstract
Description
互いに対向する第1面および第2面を有する基板と、
前記第1面に薄膜プロセスによって形成された薄膜キャパシタと、
前記第2面のうち、平面視で前記薄膜キャパシタと少なくとも一部が重なる領域に、薄膜プロセスによって形成された薄膜インダクタと、
前記基板に形成され、前記薄膜キャパシタと前記薄膜インダクタとを接続する層間接続導体と、
前記第1面側に形成され、前記薄膜キャパシタを覆う絶縁層と、
前記絶縁層の表面に形成され、前記薄膜キャパシタおよび前記薄膜インダクタに接続された端子電極と、
を有することを特徴とする。
前記半導体チップは、前記基板にバンプを介してフェイスダウン実装され、
前記キャパシタおよび前記インダクタは、
互いに対向する第1面および第2面を有する基板と、
前記第1面に薄膜プロセスによって形成された薄膜キャパシタと、
前記第2面のうち平面視で前記薄膜キャパシタとほぼ重なる領域に、薄膜プロセスによって形成された薄膜インダクタと、
前記基板に形成され、前記薄膜キャパシタと前記薄膜インダクタとを接続する層間接続導体と、
前記第1面側に形成され、前記薄膜キャパシタを覆う絶縁層と、
前記絶縁層の表面に形成され、前記薄膜キャパシタおよび前記薄膜インダクタに接続された端子電極と、
を有する薄膜型LC部品として構成され、
前記薄膜型LC部品は、前記実装基板と前記半導体チップとの間隙に配置されたことを特徴とする。
図1(A)は第1の実施形態に係る薄膜型LC部品101の平面図、図1(C)は薄膜型LC部品101の下面図、図1(B)は、図1(A)(B)におけるX−Xラインでの、薄膜型LC部品101の縦断面図である。
第2の実施形態では、個別に作成した薄膜キャパシタと薄膜インダクタとを一体化した薄膜型LC部品102について示す。
第3の実施形態では、薄膜型LC部品の実装構造、および薄膜型LC部品を備えた電子部品の例を示す。
第4の実施形態では、複数の電源電圧で動作する回路を含むマイクロプロセッサに薄膜型LC部品を適用した例を示す。
第5の実施形態では、複数の薄膜インダクタを備える薄膜型LC部品の例を示す。
第1の実施形態では、基板10の平面視で、薄膜インダクタTFLは、そのほぼ全体が薄膜キャパシタTFCと重なる領域に形成されている例を示したが、薄膜インダクタTFLの一部が薄膜キャパシタTFCと重なる領域に形成されていてもよい。薄膜インダクタTFLの少なくとも一部が薄膜キャパシタTFCと重なる領域に形成されていれば、薄膜キャパシタおよび薄膜インダクタの形成領域の、平面視での面積が縮小化される。
H61,H62…開口
L1,L2,L3,L4…薄膜インダクタ
P1,P2,P3…ポート
P11,P12,P13,P14…ポート
PSa,PSb,PSc,PSd…電源回路
S1…第1面
S2…第2面
TFC…薄膜キャパシタ
TFL…薄膜インダクタ
TSV…Si貫通電極
10,10C,10L…基板
21,23,25…BST膜
22,24…Pt電極膜
31,32…ソルダーレジスト膜(絶縁層)
41,42,43…ビア
51,52,53…端子電極
61,62…Si貫通電極
70…導体パターン
80…実装基板
81,91…はんだボール
82…封止樹脂
90…半導体チップ
98…マイクロプロセッサチップ
101,102…薄膜型LC部品
101a,101b,101c,101d…平滑回路
200…回路基板
201…電子部品
221,222…Pt電極膜
互いに対向する第1面および第2面を有する基板と、
前記第1面に形成された薄膜キャパシタと、
前記第2面のうち、平面視で前記薄膜キャパシタと少なくとも一部が重なる領域に形成された薄膜インダクタと、
前記基板に形成され、前記薄膜キャパシタと前記薄膜インダクタとを接続する層間接続導体と、
前記第1面側に形成され、前記薄膜キャパシタを覆う絶縁層と、
前記絶縁層の表面に形成され、前記薄膜キャパシタおよび前記薄膜インダクタに接続されるとともに、実装基板上の回路に接続される複数の端子電極と、
を有することを特徴とする。
半導体チップ、キャパシタおよびインダクタの、実装基板への実装構造であって、
前記半導体チップは、前記実装基板にバンプを介してフェイスダウン実装され、
前記キャパシタおよび前記インダクタは、
互いに対向する第1面および第2面を有する基板と、
前記第1面に形成された薄膜キャパシタと、
前記第2面のうち平面視で前記薄膜キャパシタとほぼ重なる領域に形成された薄膜インダクタと、
前記基板に形成され、前記薄膜キャパシタと前記薄膜インダクタとを接続する層間接続導体と、
前記第1面側に形成され、前記薄膜キャパシタを覆う絶縁層と、
前記絶縁層の表面に形成され、前記薄膜キャパシタおよび前記薄膜インダクタに接続された端子電極と、
を有する薄膜型LC部品として構成され、
前記薄膜型LC部品は、前記実装基板と前記半導体チップとの間隙に配置され、前記端子電極が前記実装基板上の回路に接続されることで、前記実装基板に実装される、
ことを特徴とする。
Claims (6)
- 互いに対向する第1面および第2面を有する基板と、
前記第1面に薄膜プロセスによって形成された薄膜キャパシタと、
前記第2面のうち、平面視で前記薄膜キャパシタと少なくとも一部が重なる領域に、薄膜プロセスによって形成された薄膜インダクタと、
前記基板に形成され、前記薄膜キャパシタと前記薄膜インダクタとを接続する層間接続導体と、
前記第1面側に形成され、前記薄膜キャパシタを覆う絶縁層と、
前記絶縁層の表面に形成され、前記薄膜キャパシタおよび前記薄膜インダクタに接続された複数の端子電極と、
を有することを特徴とする、薄膜型LC部品。 - 前記薄膜インダクタおよび前記薄膜キャパシタはそれぞれ第1端と第2端を有し、
前記薄膜キャパシタの第1端と前記薄膜インダクタの第2端とは接続され、
前記複数の端子電極は、前記薄膜キャパシタの第1端、前記薄膜キャパシタの第2端、前記薄膜インダクタの第1端にそれぞれ接続された少なくとも3つの端子電極で構成される、
請求項1に記載の薄膜型LC部品。 - 前記薄膜インダクタは、それぞれ第1端と第2端を有する複数の薄膜インダクタで構成され、
前記複数の端子電極は、前記複数の薄膜インダクタの第1端にそれぞれ接続された端子電極を含む、請求項2に記載の薄膜型LC部品。 - 前記薄膜キャパシタは、前記第1面に平行な第1電極膜と、当該第1電極膜に対向する第2電極膜と、前記第1電極膜と前記第2電極膜との間に介在する誘電体薄膜とで構成され、前記誘電体薄膜はチタン酸バリウムストロンチウム薄膜である、請求項1から3のいずれかに記載の薄膜型LC部品。
- 前記基板、前記薄膜キャパシタ、前記薄膜インダクタおよび前記絶縁層を含む全体の厚みは100μm以下である、請求項1から4のいずれかに記載の薄膜型LC部品。
- 半導体チップ、キャパシタおよびインダクタの、実装基板への実装構造であって、
前記半導体チップは、前記基板にバンプを介してフェイスダウン実装され、
前記キャパシタおよび前記インダクタは、
互いに対向する第1面および第2面を有する基板と、
前記第1面に薄膜プロセスによって形成された薄膜キャパシタと、
前記第2面のうち平面視で前記薄膜キャパシタとほぼ重なる領域に、薄膜プロセスによって形成された薄膜インダクタと、
前記基板に形成され、前記薄膜キャパシタと前記薄膜インダクタとを接続する層間接続導体と、
前記第1面側に形成され、前記薄膜キャパシタを覆う絶縁層と、
前記絶縁層の表面に形成され、前記薄膜キャパシタおよび前記薄膜インダクタに接続された端子電極と、
を有する薄膜型LC部品として構成され、
前記薄膜型LC部品は、前記実装基板と前記半導体チップとの間隙に配置された、
薄膜型LC部品の実装構造。
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US11450469B2 (en) | 2019-08-28 | 2022-09-20 | Analog Devices Global Unlimited Company | Insulation jacket for top coil of an isolated transformer |
US11387316B2 (en) | 2019-12-02 | 2022-07-12 | Analog Devices International Unlimited Company | Monolithic back-to-back isolation elements with floating top plate |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5830119A (ja) * | 1981-08-17 | 1983-02-22 | ティーディーケイ株式会社 | 複合型回路部品 |
JPH07161528A (ja) * | 1993-12-09 | 1995-06-23 | Alps Electric Co Ltd | 薄膜素子 |
JPH11195531A (ja) * | 1997-12-29 | 1999-07-21 | Taiyosha Denki Kk | チップ部品、チップネットワーク部品 |
JP2004128219A (ja) * | 2002-10-02 | 2004-04-22 | Shinko Electric Ind Co Ltd | 付加機能を有する半導体装置及びその製造方法 |
WO2010016171A1 (ja) * | 2008-08-04 | 2010-02-11 | 株式会社 村田製作所 | 誘電体薄膜キャパシタの製造方法、及び誘電体薄膜キャパシタ |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0547586A (ja) * | 1991-08-16 | 1993-02-26 | Toshiba Corp | コンデンサ部品 |
JPH1098269A (ja) * | 1996-09-21 | 1998-04-14 | Ngk Spark Plug Co Ltd | 回路基板 |
JP2007142109A (ja) * | 2005-11-17 | 2007-06-07 | Tdk Corp | 電子部品 |
JP5445357B2 (ja) * | 2010-06-30 | 2014-03-19 | Tdk株式会社 | 電子部品及び電子デバイス |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5830119A (ja) * | 1981-08-17 | 1983-02-22 | ティーディーケイ株式会社 | 複合型回路部品 |
JPH07161528A (ja) * | 1993-12-09 | 1995-06-23 | Alps Electric Co Ltd | 薄膜素子 |
JPH11195531A (ja) * | 1997-12-29 | 1999-07-21 | Taiyosha Denki Kk | チップ部品、チップネットワーク部品 |
JP2004128219A (ja) * | 2002-10-02 | 2004-04-22 | Shinko Electric Ind Co Ltd | 付加機能を有する半導体装置及びその製造方法 |
WO2010016171A1 (ja) * | 2008-08-04 | 2010-02-11 | 株式会社 村田製作所 | 誘電体薄膜キャパシタの製造方法、及び誘電体薄膜キャパシタ |
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