JP2012104577A - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 230000002093 peripheral effect Effects 0.000 claims abstract description 44
- 239000010410 layer Substances 0.000 claims description 73
- 230000015556 catabolic process Effects 0.000 claims description 37
- 239000012535 impurity Substances 0.000 claims description 20
- 239000002344 surface layer Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 5
- 230000008569 process Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000007423 decrease Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 238000005192 partition Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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Abstract
【解決手段】素子活性部にオン状態で電流を流し、オフ状態では電圧を保持する並列pn層を有し、この並列pn層を囲む周縁耐圧構造部の並列pn層の第2導電型半導体領域の幅が前記素子活性部側の端部から外側に向かって所定の比率で狭くなっている半導体装置とする。
【選択図】 図1
Description
さらに、素子活性部の並列pn構造の外周の周縁耐圧構造部において、周縁耐圧構造部の並列pn層を素子活性部の並列pn層のピッチ、不純物濃度と同じにするとともに、周縁耐圧構造部の並列pn層の表面層の各pn層にそれぞれ、低不純物濃度領域を設ける構造およびまたは並列pn層の表面層にn型の低不純物濃度領域を設け、そのn型の低不純物濃度領域の中に高不純物濃度のp型領域を備えた構造が知られている。これら構造によれば、素子活性部付近の周縁耐圧構造部の表面電界が緩和され、高耐圧が保持されるとある(特許文献3、4)。
実施例3は実施例2の変形例であり、実施例2と異なるのはガードリング32a、32b、32cの表面に導電接触するフィールドプレートが金属ではなく、ポリシリコンフィールドプレート34a、34b、34cにされている点である。ポリシリコンのパターンエッチングにはRIE(Reactive Ion Etching)などのドライエッチングを使用でき、寸法精度を高めることができるので、初期耐圧、耐電荷性の安定化により大きな効果がある。
2 p型仕切領域
3 pベース領域
4 表面n型ドリフト領域
5 pコンタクト領域
6 n+ソース領域
7 ゲート絶縁膜
8 ゲート電極
9 層間絶縁膜
10 ソース電極
11 ドレイン領域
12 ドレイン電極
13 チャネルストッパー領域
14 p型表面領域
15 絶縁膜
16 チャネルストッパー電極
21 n型半導体領域
22 p型半導体領域
32a、32b、32c ガードリング
33a、33b、33c フィールドプレート
34a、34b、34c ポリシリコンフィールドプレート
50a、50b 並列pn層
P1、P2 ピッチ
T1 ドリフト層
K 素子活性部
S 周縁耐圧構造部
Claims (3)
- 第1導電型高不純物濃度の半導体基板の表面に垂直に配向する柱状または層状の第1導電型半導体領域と第2導電型半導体領域とが、沿面方向に繰り返し交互に隣接する並列pn層を構成するとともに、オン状態で電流を流し、オフ状態では電圧を阻止するドリフト層となり、該並列pn層の表面側に、主電流を流す素子活性部を構成する表面構造と該素子活性部を取り巻く周縁耐圧構造部とを備える半導体装置において、前記周縁耐圧構造部内の並列pn層の第2導電型半導体領域の幅が前記素子活性部側の端部から外側に向かって所定の比率で狭くなっていることを特徴とする半導体装置。
- 前記周縁耐圧構造部が並列pn層の表面層に相互に離間して配置される複数のガードリングを備えることを特徴とする請求項1に記載の半導体装置。
- 前記周縁耐圧構造部が並列pn層の表面層に配置される前記ガードリングの表面に導電接触する導電性フィールドプレートを備えることを特徴とする請求項2に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2010250427A JP5664142B2 (ja) | 2010-11-09 | 2010-11-09 | 半導体装置 |
CN201110364464.7A CN102468337B (zh) | 2010-11-09 | 2011-11-02 | 半导体器件 |
US13/290,508 US8735982B2 (en) | 2010-11-09 | 2011-11-07 | Semiconductor device with superjunction structure |
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JP2010250427A JP5664142B2 (ja) | 2010-11-09 | 2010-11-09 | 半導体装置 |
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JP2012104577A true JP2012104577A (ja) | 2012-05-31 |
JP5664142B2 JP5664142B2 (ja) | 2015-02-04 |
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JP2010250427A Active JP5664142B2 (ja) | 2010-11-09 | 2010-11-09 | 半導体装置 |
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US (1) | US8735982B2 (ja) |
JP (1) | JP5664142B2 (ja) |
CN (1) | CN102468337B (ja) |
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JP2015070184A (ja) * | 2013-09-30 | 2015-04-13 | サンケン電気株式会社 | 半導体装置 |
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JP5664142B2 (ja) | 2015-02-04 |
CN102468337A (zh) | 2012-05-23 |
CN102468337B (zh) | 2016-09-21 |
US8735982B2 (en) | 2014-05-27 |
US20120112306A1 (en) | 2012-05-10 |
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