CN105206674A - 一种超结终端的vdmos结构 - Google Patents

一种超结终端的vdmos结构 Download PDF

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CN105206674A
CN105206674A CN201510486955.7A CN201510486955A CN105206674A CN 105206674 A CN105206674 A CN 105206674A CN 201510486955 A CN201510486955 A CN 201510486955A CN 105206674 A CN105206674 A CN 105206674A
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region
type semiconductor
silicon substrate
vdmos
drift region
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周炳
石英学
张志娟
郝建勇
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ZHANGJIAGANG EVER POWER SEMICONDUCTOR CO Ltd
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ZHANGJIAGANG EVER POWER SEMICONDUCTOR CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明涉及半导体器件技术领域，一种超结终端的VDMOS结构，包括硅衬底和设置在硅衬底上的漂移区；所述的漂移区包括有源区和围绕在有源区四周区域的终端区；所述的有源区上设置有阱区和源区，所述终端区沿其宽度和长度方向均设置有交替排列的P型半导体柱和N型半导体柱；硅衬底上表面的有源区设置有栅极G和源极S，硅衬底下表面设置有漏极D。有益效果：本发明采用超结结构能够协调好击穿电压和导通电阻之间的关系，P型半导体柱和N型半导体柱在终端区的宽度和长度方向交替排列，能够更好的达到电荷的平衡，提高耐压，减小导通电阻，减小终端区的面积，进一步的减小芯片面积，降低成本。

Description

一种超结终端的VDMOS结构
技术领域
本发明涉及半导体器件技术领域，尤其涉及一种超结终端的VDMOS结构。
背景技术
VDMOS(垂直双扩散金属-氧化物半导体场效应晶体管)广泛应用于电力电子系统中，在理想的关态情况下，能够承受很高的电压，导通时具有较小的压降，较大的电流密度，且开关速度快，开关损耗小。然而，在实际上往往不能达到理想的性能。在高压应用领域内，传统的VDMOS需要增加漂移区的厚度和降低外延层的掺杂浓度来提高击穿电压，这势必会增大器件的导通电阻，增加功耗。超结概念是以关态时达到电荷平衡为基础，采用交叠的P型半导体柱和N型半导体柱组成器件的漂移区。因此，超结的阻断能力对P型半导体柱和N型半导体柱间电荷的不平衡非常敏感，这给器件制造带来了很大的挑战和风险。
发明内容
本发明的目的在于解决VDMOS的击穿电压与导通电阻之间的矛盾，在保证高耐压的同时具有低的导通电阻，同时减小芯片的面积，提出了一种特殊超结终端的VDMOS结构。本发明针对上述问题，提出了一种特殊超结终端的VDMOS结构，终端区沿其宽度和长度方向均设置有交替排列的P型半导体柱和N型半导体柱，能够更好地达到电荷平衡，既解决了击穿电压和导通电阻之间的矛盾，又减小了终端区所占面积，提高电流的处理能力，降低了成本。
本发明解决其技术问题所采用的技术方案是：一种超结终端的VDMOS结构，包括硅衬底和设置在硅衬底上的漂移区；所述的漂移区包括有源区和围绕在有源区四周区域的终端区；所述的有源区上设置有阱区和源区，所述终端区沿其宽度和长度方向均设置有交替排列的P型半导体柱和N型半导体柱；硅衬底上表面的有源区设置有栅极G和源极S，硅衬底下表面设置有漏极D。
进一步地，所述的硅衬底为N+硅衬底，所述漂移区为N-漂移区，所述阱区为P-阱区，所述的源区为N+源区。
作为上述方案的替代，所述的硅衬底为P型硅衬底，所述漂移区为P型漂移区，所述阱区为N-阱区，所述的源区为P+源区。
进一步地，所述的有源区为平面结构、沟槽结构或超结结构。
作为优选，所述终端区的P型半导体柱和N型半导体柱深度等于漂移区的厚度。
有益效果：本发明采用超结结构能够协调好击穿电压和导通电阻之间的关系，P型半导体柱和N型半导体柱在终端区的宽度和长度方向交替排列，能够更好的达到电荷的平衡，提高耐压，减小导通电阻，减小终端区的面积，进一步的减小芯片面积，降低成本。
附图说明
下面结合附图和具体实施方式对本发明作进一步详细的说明。
图1是本发明超结终端VDMOS结构俯视图；
图2是本发明超结终端VDMOS结构剖面图。
其中:1.有源区，2.终端区，21.P型半导体柱，22.N型半导体柱，3.硅衬底，4.漂移区，5.阱区，6.源区。
具体实施方式
为使本发明的目的、技术方案更加清楚明白，下面结合附图和具体实施方式对本发明做进一步的描述。
实施例1
如图1所示，本发明VDMOS结构分为有源区1和终端区2两部分，终端区2围绕在有源区1四周，其中有源区1可以是平面结构、沟槽结构或者超结结构。本发明的终端区2设有P型半导体柱21和N型半导体柱22，其中P型半导体柱21和N型半导体柱22不仅在终端区2宽度方向交替排列，在终端区2长度方向也交替排列。
本实施例有源区1以超结结构为例，如图2所示，为本发明的剖面结构，其结构是在N+硅衬底上生长轻掺杂的N-漂移区，通过光刻刻蚀工艺在终端区2和有源区1挖出沟槽，用填槽工艺形成P型半导体柱21和N型半导体柱22，P型半导体柱21和N型半导体柱22深度度等于漂移区4厚度，光刻刻蚀多晶形成栅极G，离子注入形成P-阱区和N+源区，沉积金属Al，形成源极S，背面淀积金属Ti/Ni/Ag，形成漏极D。(若将硅衬底3替换为P型硅衬底，则漂移区相应为P型漂移区，阱区5为N-阱区，所述的源区6为P+源区)
本发明采用超结结构能够协调好击穿电压和导通电阻之间的关系，提高耐压，减小导通电阻。P型半导体柱21和N型半导体柱22在其宽度和长度方向均交替排列。与现有的只在其宽度方向交替排列或只在其长度方向交替排列的单一方向交替排列相比，终端区2从大面积的P型半导体柱21和N型半导体柱22交替排列变为小面积的P型半导体柱21和N型半导体柱22交替排列组合而成，其工艺更容易控制，工艺宽容度较高，可以从原来的2％增加到5％(即工艺偏差达到5％仍可以达到参数要求)，更容易达到电荷平衡，耐压可以提高10％，同时减小终端区2的面积，进一步的减小芯片面积，降低成本。
应当理解，以上所描述的具体实施例仅用于解释本发明，并不用于限定本发明。由本发明的精神所引伸出的显而易见的变化或变动仍处于本发明的保护范围之中。

Claims (5)

1.一种超结终端的VDMOS结构，其特征在于：包括硅衬底(3)和设置在硅衬底(3)上的漂移区(4)；所述的漂移区(4)包括有源区(1)和围绕在有源区(1)四周区域的终端区(2)；所述的有源区(1)上设置有阱区(5)和源区(6)，所述终端区(2)沿其宽度和长度方向均设置有交替排列的P型半导体柱(21)和N型半导体柱(22)；硅衬底(3)上表面的有源区(1)设置有栅极G和源极S，硅衬底(3)下表面设置有漏极D。
2.根据权利要求1所述的超结终端的VDMOS结构，其特征在于：所述的硅衬底(3)为N+硅衬底，所述漂移区(4)为N-漂移区，所述阱区(5)为P-阱区，所述的源区(6)为N+源区。
3.根据权利要求1所述的超结终端的VDMOS结构，其特征在于：所述的硅衬底(3)为P型硅衬底，所述漂移区(4)为P型漂移区，所述阱区(5)为N-阱区，所述的源区(6)为P+源区。
4.根据权利要求1所述的超结终端的VDMOS结构，其特征在于：所述的有源区(1)为平面结构、沟槽结构或超结结构。
5.根据权利要求1所述的超结终端的VDMOS结构，其特征在于：所述终端区(2)的P型半导体柱(21)和N型半导体柱(22)深度等于漂移区(4)的厚度。
CN201510486955.7A 2015-08-11 2015-08-11 一种超结终端的vdmos结构 Pending CN105206674A (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109119341A (zh) * 2018-08-22 2019-01-01 盛世瑶兰（深圳）科技有限公司 一种vdmos器件终端结构及其制作方法
CN111244151A (zh) * 2018-11-29 2020-06-05 株洲中车时代电气股份有限公司 一种功率半导体器件超级结终端结构

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CN102468337A (zh) * 2010-11-09 2012-05-23 富士电机株式会社 半导体器件
CN103493207A (zh) * 2011-07-14 2014-01-01 富士电机株式会社 高击穿电压半导体器件
CN104638004A (zh) * 2013-11-15 2015-05-20 上海华虹宏力半导体制造有限公司 超级结mosfet器件的结构

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Publication number Priority date Publication date Assignee Title
JP2005203565A (ja) * 2004-01-15 2005-07-28 Fuji Electric Holdings Co Ltd 半導体装置およびその製造方法
CN102468337A (zh) * 2010-11-09 2012-05-23 富士电机株式会社 半导体器件
CN103493207A (zh) * 2011-07-14 2014-01-01 富士电机株式会社 高击穿电压半导体器件
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109119341A (zh) * 2018-08-22 2019-01-01 盛世瑶兰（深圳）科技有限公司 一种vdmos器件终端结构及其制作方法
CN111244151A (zh) * 2018-11-29 2020-06-05 株洲中车时代电气股份有限公司 一种功率半导体器件超级结终端结构
CN111244151B (zh) * 2018-11-29 2023-06-23 株洲中车时代半导体有限公司 一种功率半导体器件超级结终端结构

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