WO2014087522A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2014087522A1 WO2014087522A1 PCT/JP2012/081661 JP2012081661W WO2014087522A1 WO 2014087522 A1 WO2014087522 A1 WO 2014087522A1 JP 2012081661 W JP2012081661 W JP 2012081661W WO 2014087522 A1 WO2014087522 A1 WO 2014087522A1
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- 239000004065 semiconductor Substances 0.000 title claims description 45
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Definitions
- the present invention relates to a semiconductor device for forming a high voltage power module of 600 V or higher.
- a termination region is disposed around an active region where a transistor is formed.
- a plurality of P-type ring layers separated from each other and one or more P-type layers connected to each other in the termination region see, for example, Patent Document 1.
- the allowable range of the dose amount of the P-type layer is narrow, so that process control is difficult and the defect rate is high.
- a high electric field is generated at the end of the P-type layer on the active region side or outside, thereby limiting the upper limit of the breakdown voltage.
- a plurality of P-type layers are formed, a plurality of photolithography and ion implantation steps are required, which complicates the manufacturing process and increases the product cost.
- the present invention has been made to solve the above-described problems, and its purpose is to reduce the chip area without impairing the electrical characteristics, improve the turn-off cutoff capability, and widen the allowable range of the P-type dose.
- a semiconductor device that can be manufactured by a simple manufacturing process is obtained.
- a semiconductor device is a semiconductor device in which an active region in which a transistor is formed and a termination region disposed around the active region are provided on a silicon substrate and have a breakdown voltage equal to or higher than a target breakdown voltage.
- the termination region has a ring region, and the ring region is provided with a plurality of ring-shaped P-type ring layers arranged periodically, and the ring region includes a plurality of P-type ring layers.
- the chip area can be reduced without impairing the electrical characteristics, the turn-off cutoff capability can be improved, the allowable range of the P-type dose can be widened, and the device can be manufactured by a simple manufacturing process.
- FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 is a cross-sectional view taken along the line II of FIG. It is a figure which shows the model used for the two-dimensional simulation of correction coefficient (gamma), M. It is a figure which shows the relationship between the total number of impurities calculated by two-dimensional simulation, and a proof pressure. It is a figure which shows the relationship of the proof pressure BV CES and the P type impurity total number N when the conditions 2 and 3 are satisfy
- FIG. 7 is a cross-sectional view showing a semiconductor device according to Comparative Example 1.
- FIG. 10 is a cross-sectional view showing a semiconductor device according to Comparative Example 2.
- FIG. 10 is a cross-sectional view showing a semiconductor device according to Comparative Example 3.
- FIG. 10 is a cross-sectional view showing a semiconductor device according to Comparative Example 1.
- FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1 of the present invention.
- An active region in which a transistor is formed, a termination region disposed around the active region, and a main PN junction region disposed therebetween are provided on the silicon substrate.
- the transistor When the transistor is turned on, the main current flows in the active region, but the main current does not flow in the termination region.
- the transistor When the transistor is turned off, a depletion layer extends in the lateral direction of the device in the termination region by bias application, and the withstand voltage is maintained.
- the semiconductor device has a breakdown voltage equal to or higher than the target breakdown voltage.
- FIG. 2 is a cross-sectional view taken along the line II of FIG.
- an N-type layer 2 and a P-type emitter layer 3 are sequentially provided on the N ⁇ -type drift layer 1.
- a plurality of trench gates 4 are provided so as to penetrate the N-type layer 2 and the P-type emitter layer 3.
- a P + -type contact layer 5 is provided on a part of the P-type emitter layer 3 between the plurality of trench gates 4.
- An emitter electrode 6 on the silicon substrate is connected to the P + type contact layer 5.
- the emitter electrode 6 and the trench gate 4 are insulated by an interlayer insulating film 7.
- An N-type layer 8 and a P-type collector layer 9 are sequentially provided below the N ⁇ -type drift layer 1.
- a collector electrode 10 is connected to the P-type collector layer 9.
- a P-type layer 11 is provided on the N ⁇ -type drift layer 1 in the main PN junction region.
- the termination region has a ring region LNFLR (Linearly-Narrowed Field Limit Ring).
- LNFLR Linearly-Narrowed Field Limit Ring
- a plurality of ring-shaped P-type ring layers 12 a to 12 f are periodically arranged on the N ⁇ -type drift layer 1.
- a channel stopper region is provided on the outer peripheral side.
- An N-type layer 13 is provided on the N ⁇ -type drift layer 1 in the channel stopper region.
- An electrode 14 is connected to the N-type layer 13.
- the upper surfaces of the main PN junction region and the termination region are covered with insulating films 15 and 16.
- the boundary between the main PN junction region and the active region is the end of the outermost peripheral P + -type contact layer 5 on the main PN junction region side.
- the boundary between the main PN junction region and the termination region is the end of the P-type layer 11 on the termination region side.
- Ring region LNFLR is divided into a plurality of units each including one of a plurality of P-type ring layers 12a-12f, and the width SandL of each unit is constant. The following conditions are satisfied, where the total number of ionized P-type impurities in the ring region LNFLR is N, the target breakdown voltage is BV [V], the width of each unit is SandL [ ⁇ m], and the number of units is num.
- the widths of the P-type ring layers 12a to 12f of the plurality of units are linearly reduced toward the outside of the termination region (Condition 3).
- the change amount ⁇ is 0 ⁇ ⁇ 1.5.
- the correction coefficients ⁇ and M are used to correct the influence of the material, the two- and three-dimensional effects, and the device design (device shape, diffusion layer formation, etc.), and are extracted using device simulation software. Here, the case of two-dimensional simulation will be described.
- FIG. 3 is a diagram showing a model used for the two-dimensional simulation of the correction coefficients ⁇ and M.
- the model shown in FIG. 3 is created.
- the dimensions and impurity distribution of each part other than the P-type ring layer 12 are matched with those of the actual chip.
- the width of the P-type ring layer 12 and the width of the unit in which it is included are arbitrary.
- the breakdown voltage under the condition of the total number N of each impurity is calculated by simulation.
- FIG. 4 is a diagram showing the relationship between the total number of impurities and the breakdown voltage calculated by two-dimensional simulation.
- FIG. 5 is a diagram showing the relationship between the breakdown voltage BV CES and the total number N of P-type impurities when the conditions 2 and 3 are satisfied.
- the vertical axis is a value obtained by standardizing the withstand voltage BV CES with reference to the target withstand voltage BV in each withstand voltage class.
- the normalized breakdown voltage BV CES becomes 1 or more when the normalized total number N of P-type impurities is 1 or more. Therefore, it was confirmed that the target withstand voltage BV can be realized if the conditions 1 and 3 are further satisfied when the conditions 2 and 3 are satisfied.
- the correction coefficient ⁇ in condition 2 is to correct the influence of 2, 3D effects and device design (shape, etc.), and is extracted using device simulation software. Here, the case of two-dimensional simulation will be described.
- FIGS. 6 and 7 are diagrams showing models used for the two-dimensional simulation of the correction coefficient ⁇ .
- FIG. 6 shows a one-dimensional step-type PN junction model.
- FIG. 7 shows a model of cylindrical junction with Gaussian distribution, and this impurity distribution is matched with the actual chip.
- the withstand voltage is calculated using the models shown in FIGS.
- FIG. 8 is a diagram showing the relationship between the withstand voltage BV CES and SandL ⁇ num when the conditions 1 and 3 are satisfied.
- the vertical axis is a value obtained by standardizing the withstand voltage BV CES with reference to the target withstand voltage BV of each withstand voltage class.
- Condition 3 is a condition of the width of the P-type region in the unit necessary for satisfying the target breakdown voltage BV.
- FIG. 9 is a diagram illustrating the relationship between the withstand voltage BV CES and the change amount ⁇ when the conditions 1 and 2 are satisfied. The vertical axis is a value obtained by standardizing the withstand voltage BV CES with reference to the target withstand voltage BV of each withstand voltage class.
- FIG. 10 is a diagram showing the electric field distribution on the surface (I-II in FIG. 2) of the termination region of the 4500 V class IGBT. ⁇ 0 is an optimum value of ⁇ , ⁇ 1 is a value smaller than the optimum value, and ⁇ 2 is a value larger than the optimum value.
- the horizontal axis is a value obtained by standardizing the distance based on the width of the termination region.
- Table 1 shows the allowable range of ⁇ .
- FIG. 11 is a cross-sectional view showing a semiconductor device according to Comparative Example 1.
- a plurality of P-type ring layers 17a to 17n are provided in the termination region.
- the concentration, depth, number, etc. of the P-type ring layers 17a to 17n are different design parameters depending on the withstand voltage to be held.
- the electric field in the lateral direction is shared by the N-type drift layer 1 between the P-type ring layers 17a to 17n at intervals.
- the chip area increases.
- a high electric field is generated where the curvature of the outermost P-type ring layer 17n is high, limiting the upper limit of the breakdown voltage, and the turn-off cutoff capability is reduced.
- FIG. 12 is a cross-sectional view showing a semiconductor device according to Comparative Example 2.
- One P-type layer 18 is provided in the termination region.
- the concentration, depth, etc. of the P-type layer 18 are different design parameters depending on the withstand voltage to be held.
- the surface concentration of the P-type layer 18 decreases toward the outside of the termination region.
- the allowable range of the dose amount of the P-type layer 18 is narrow, process control is difficult and the defect rate is high.
- a high electric field is generated at the end of the P-type layer 18 on the active region side or outside, thereby limiting the upper limit of the breakdown voltage.
- FIG. 13 is a cross-sectional view showing a semiconductor device according to Comparative Example 3.
- a plurality of P-type layers 18a and 18b are provided in the termination region.
- the concentration, depth, etc. of the P-type layers 18a, 18b are different design parameters depending on the withstand voltage to be held.
- the surface concentration of the P-type layers 18a and 18b decreases toward the outside of the termination region, and the depth decreases toward the outside of the termination region.
- a plurality of photoengraving and ion implantation steps are required, which complicates the manufacturing process and increases the product cost.
- FIG. 14 is a diagram showing an evaluation circuit diagram used in an evaluation experiment of the withstand voltage characteristic.
- An IGBT structure device having a withstand voltage of 4500 V is used.
- the evaluation conditions are Vcc 4500V, VGE 0V, temperature 398K, and DC mode.
- the breakdown voltage leakage current characteristics are evaluated under these evaluation conditions.
- FIG. 15 is a diagram showing the evaluation results of the breakdown voltage leakage current characteristics.
- the leakage current J CES (@ 4500 V) in the first embodiment was reduced by 90% from that in Comparative Example 1.
- the width of the termination region in the first embodiment can be reduced by 50% compared to the first comparative example.
- the surface electric field in the termination region can be suppressed, drift current due to a high electric field can be reduced, and local impact ionization can be suppressed.
- FIG. 17 is a diagram showing the relationship between the breakdown voltage and the P-type dose amount deviation.
- An IGBT structure device having a withstand voltage of 4500 V is used.
- the vertical axis is a value obtained by standardizing the withstand voltage BV CES with the target withstand voltage BV as a reference.
- the horizontal axis represents the dose deviation ratio value.
- the allowable range of the dose amount is as follows: Embodiments 2-6, 8-12> Embodiment 7> Embodiment 1> Comparative Example 2. Therefore, according to the present embodiment, the allowable range of the P-type dose can be widened as compared with Comparative Example 2.
- FIG. 18 is a diagram showing an evaluation circuit used in an evaluation experiment for turn-off characteristics.
- An IGBT structure device having a withstand voltage of 4500 V is used.
- the turn-off characteristics are evaluated under these evaluation conditions.
- FIG. 19 is a diagram showing the evaluation results of the turn-off characteristics.
- the temperature is 398K.
- the turn-off loss is substantially constant as compared with Comparative Example 1, the width of the termination region is reduced, and the amount of holes from the termination region during the turn-off operation is reduced. For this reason, the tail current can be reduced.
- Figure 20 is a diagram showing the relationship between turn-off blocking capacity (J C (break)) V CC.
- An IGBT structure device having a withstand voltage of 4500 V is used.
- this embodiment reduces the chip area without impairing the electrical characteristics (ON voltage, breakdown voltage, turn-off loss, short-circuit resistance, etc.), improves the turn-off cutoff capability, and widens the allowable range of the P-type dose. be able to. Further, since the plurality of P-type ring layers 12a to 12f can be collectively formed, they can be manufactured by a simple manufacturing process.
- FIG. FIG. 21 is a top view and a sectional view showing a semiconductor device according to the second embodiment of the present invention.
- the structure of the P-type ring layers 12a to 12f is different from that of the first embodiment, and the P-type ring layers 12a to 12f have a plurality of stripe structures 19 arranged periodically in plan view. Electric field concentration occurs at the boundary of each stripe structure 19 in the P-type ring layers 12a to 12f. By using the field limiting ring effect to share the electric field distribution, local high electric fields can be suppressed.
- the breakdown voltage is shared by the boundary portion of the stripe structure 19, the depletion layer does not extend to the inside of the stripe structure 19. Thereby, complete depletion of impurities in the stripe structure 19 can be prevented, and the dependency of the breakdown voltage on the dose amount of the P-type impurity in the ring region LNFLR can be relaxed.
- FIG. FIG. 22 is a top view and cross-sectional view showing a semiconductor device according to the third embodiment of the present invention.
- the structure of the P-type ring layers 12a to 12f is different from that of the first embodiment, and the P-type ring layers 12a to 12f have a plurality of dot structures 20 that are periodically arranged in plan view. Electric field concentration occurs at the boundary of each dot structure 20 in the P-type ring layers 12a to 12f. By using the field limiting ring effect to share the electric field distribution, local high electric fields can be suppressed. Further, since the breakdown voltage is shared by the boundary portion of the dot structure 20, the depletion layer does not extend to the inside of the dot structure 20.
- the dot structure 20 is a square, but is not limited thereto.
- FIG. 23 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention.
- a P-type layer 21 that overlaps at least a part of the ring region LNFLR is provided in the termination region.
- the surface concentration of the P-type layer 21 is smaller than the surface concentration of the P-type ring layers 12a to 12f.
- the depth d2 of the P-type layer 21 is deeper than the depth d1 of the P-type ring layers 12a to 12f.
- the portion having a voltage is the outermost periphery of the P-type layer 21 having a low PN curvature or the boundary between the P-type ring layers 12a to 12f in the ring region LNFLR. For this reason, the concentration of the electric field can be relaxed and dispersed. As a result, the turn-off cutoff capability can be further improved and the surface electric field can be relaxed.
- FIG. FIG. 24 is a top view and a cross-sectional view showing a semiconductor device according to the fifth embodiment of the present invention.
- This embodiment has the features of both the second and fourth embodiments, and the effects of both can be obtained.
- FIG. 25 is a top view and a sectional view showing a semiconductor device according to the sixth embodiment of the present invention.
- the present embodiment has the features of both the third and fourth embodiments, and the effects of both can be obtained.
- FIG. FIG. 26 is a sectional view showing a semiconductor device according to the seventh embodiment of the present invention.
- the termination region has a plurality of ring regions LNFLR1 and LNFLR2.
- a plurality of ring-shaped P-type ring layers 12a to 12f are periodically arranged.
- Each ring region is divided into a plurality of units each including a plurality of P-type ring layers 12a-12f. Within the same ring area, the width of each unit is constant.
- the ring regions LNFLR1 and LNFLR2 have different unit widths Sand1 and Sand2.
- the total number of ionized P-type impurities in the i-th ring region from the active region to the outside is N (i)
- the target breakdown voltage is BV [V]
- the i-th ring region LNFLR is shared.
- the breakdown voltage is BV (i) [V]
- the width of each unit of the i-th ring region LNFLR is SandL (i) [ ⁇ m]
- the number of the plurality of units in the i-th ring region LNFLR is num (i). Satisfy the relationship.
- the widths SandL1 and SandL2 of the P-type ring layers 12a to 12f of the plurality of units linearly decrease toward the outside of the termination region.
- the rate of change ⁇ 1 in the ring region LNFLR1 and the rate of change ⁇ 2 in the ring region LNFLR2 satisfy ⁇ 2> ⁇ 1> 0.
- the termination region is designed in stages, and the LNFLR structure is formed in each part according to the above rules.
- the electric field distribution can be made more uniform than in the first embodiment, so that the process allowable range can be further expanded.
- FIG. 27 is a cross-sectional view showing a modification of the semiconductor device according to the seventh embodiment of the present invention.
- FIG. FIG. 28 is a sectional view showing a semiconductor device according to the eighth embodiment of the present invention.
- the structure of the P-type ring layers 12a to 12f is different from that of the seventh embodiment, and the P-type ring layers 12a to 12f have a plurality of stripe structures 19 that are periodically arranged in plan view. Thereby, the dependency of the breakdown voltage on the dose amount of the P-type impurity in the ring region LNFLR can be relaxed as in the second embodiment.
- FIG. 29 is a sectional view showing a semiconductor device according to the ninth embodiment of the present invention.
- the structure of the P-type ring layers 12a to 12f is different from that of the seventh embodiment, and the P-type ring layers 12a to 12f have a plurality of dot structures 20 that are periodically arranged in plan view. Thereby, the dependency of the breakdown voltage on the dose amount of the P-type impurity in the ring region LNFLR can be relaxed as in the third embodiment.
- FIG. FIG. 30 is a sectional view showing a semiconductor device according to the tenth embodiment of the present invention.
- a P-type layer 21 that overlaps at least a part of the ring region LNFLR is provided in the termination region.
- the surface concentration of the P-type layer 21 is smaller than the surface concentration of the P-type ring layers 12a to 12f.
- the depth of the P-type layer 21 is deeper than the depth of the P-type ring layers 12a to 12f.
- the portion having a voltage is the outermost periphery of the P-type layer 21 having a low PN curvature or the boundary between the P-type ring layers 12a to 12f in the ring region LNFLR. For this reason, the concentration of the electric field can be relaxed and dispersed. As a result, the turn-off cutoff capability can be further improved and the surface electric field can be relaxed.
- FIG. 31 is a top view and cross-sectional view showing a semiconductor device according to Embodiment 11 of the present invention.
- This embodiment has the features of both the eighth and tenth embodiments, and the effects of both can be obtained.
- FIG. FIG. 32 is a top view and cross-sectional view showing a semiconductor device according to Embodiment 12 of the present invention.
- This embodiment has the features of both the ninth and tenth embodiments, and the effects of both can be obtained.
- the semiconductor device of the high withstand voltage class of 4500 V has been described, but the present invention can be applied regardless of the withstand voltage class.
- the case where the transistor in the active region is an IGBT having a trench gate structure has been described.
- the present invention can also be applied to an IGBT or a diode having a planar gate structure.
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Abstract
Description
図1は、本発明の実施の形態1に係る半導体装置を示す平面図である。シリコン基板に、トランジスタが形成された活性領域と、活性領域の周囲に配置された終端領域と、両者の間に配置された主PN接合領域とが設けられている。トランジスタのON時に活性領域には主電流が流れるが、終端領域には主電流が流れない。トランジスタのOFF時にバイアス印加により終端領域で空乏層がデバイス横方向に伸び、耐圧を保持する。これにより、半導体装置は目標耐圧以上の耐圧を持つ。
N≧(M×BV)γ、M=104~105、γ=0.55~1.95 (条件1)
SandL×num×Ecri≧2×α×BV、Ecri=2.0~3.0×105[V/cm]、α=100~101 (条件2)
図21は、本発明の実施の形態2に係る半導体装置を示す上面図及び断面図である。実施の形態1とはP型リング層12a~12fの構造が異なり、P型リング層12a~12fは、平面視で周期的に配置された複数のストライプ構造19を有する。P型リング層12a~12f内の各ストライプ構造19の境界に電界集中が発生する。field limiting ring効果を生かして電界分布を分担することで、局所的な高電界を抑えることができる。また、ストライプ構造19の境界部に耐圧を分担するため、ストライプ構造19の内部まで空乏層が伸ばない。これにより、ストライプ構造19内の不純物の完全な空乏化を防止し、リング領域LNFLR内のP型不純物のドーズ量に対する耐圧の依存性を緩和することができる。
図22は、本発明の実施の形態3に係る半導体装置を示す上面図及び断面図である。実施の形態1とはP型リング層12a~12fの構造が異なり、P型リング層12a~12fは、平面視で周期的に配置された複数のドット構造20を有する。P型リング層12a~12f内の各ドット構造20の境界に電界集中が発生する。field limiting ring効果を生かして電界分布を分担することで、局所的な高電界を抑えることができる。また、ドット構造20の境界部に耐圧を分担するため、ドット構造20の内部まで空乏層が伸ばない。これにより、ドット構造20内の不純物の完全な空乏化を防止し、リング領域LNFLR内のP型不純物のドーズ量に対する耐圧の依存性を緩和することができる。なお、本実施の形態ではドット構造20は正方形であるが、これに限らない。
図23は、本発明の実施の形態4に係る半導体装置を示す断面図である。実施の形態1の構成に加えて、終端領域において、リング領域LNFLRの少なくとも一部と重なるP型層21が設けられている。P型層21の表面濃度はP型リング層12a~12fの表面濃度より小さい。P型層21の深さd2はP型リング層12a~12fの深さd1より深い。
N1+N2≧(M×BV)γ、M=104~105、γ=0.55~1.95
図24は、本発明の実施の形態5に係る半導体装置を示す上面図及び断面図である。本実施の形態は実施の形態2,4の両方の特徴を備えており、その両方の効果を得ることができる。
図25は、本発明の実施の形態6に係る半導体装置を示す上面図及び断面図である。本実施の形態は実施の形態3,4の両方の特徴を備えており、その両方の効果を得ることができる。
図26は、本発明の実施の形態7に係る半導体装置を示す断面図である。実施の形態1とは異なり終端領域は複数のリング領域LNFLR1,LNFLR2を有する。それらのリング領域には、リング状の複数のP型リング層12a~12fが周期的に並んで設けられている。各リング領域は、複数のP型リング層12a~12fをそれぞれ含む複数のユニットに分けられている。同じリング領域内では各ユニットの幅は一定である。ただし、リング領域LNFLR1,LNFLR2は互いに異なるユニットの幅Sand1,Sand2を持つ。
N(i)≧(M×BV(i))γ、M=104~105、γ=0.55~1.95
Σ[SandL(i)×num(i)×Emax(i)]≧2×α×BV
BV=ΣBV(i)、Emax(i)≦Ecri、Ecri=2.0~3.0×105[V/cm]、α=100~101、β(i+1)>β(i)
図28は、本発明の実施の形態8に係る半導体装置を示す断面図である。実施の形態7とはP型リング層12a~12fの構造が異なり、P型リング層12a~12fは、平面視で周期的に配置された複数のストライプ構造19を有する。これにより、実施の形態2と同様にリング領域LNFLR内のP型不純物のドーズ量に対する耐圧の依存性を緩和することができる。
図29は、本発明の実施の形態9に係る半導体装置を示す断面図である。実施の形態7とはP型リング層12a~12fの構造が異なり、P型リング層12a~12fは、平面視で周期的に配置された複数のドット構造20を有する。これにより、実施の形態3と同様にリング領域LNFLR内のP型不純物のドーズ量に対する耐圧の依存性を緩和することができる。
図30は、本発明の実施の形態10に係る半導体装置を示す断面図である。実施の形態7の構成に加えて、終端領域において、リング領域LNFLRの少なくとも一部と重なるP型層21が設けられている。P型層21の表面濃度はP型リング層12a~12fの表面濃度より小さい。P型層21の深さはP型リング層12a~12fの深さより深い。
N1+N2≧(M×BV)γ、M=104~105、γ=0.55~1.95
図31は、本発明の実施の形態11に係る半導体装置を示す上面図及び断面図である。本実施の形態は実施の形態8,10の両方の特徴を備えており、その両方の効果を得ることができる。
図32は、本発明の実施の形態12に係る半導体装置を示す上面図及び断面図である。本実施の形態は実施の形態9,10の両方の特徴を備えており、その両方の効果を得ることができる。
Claims (5)
- トランジスタが形成された活性領域と、前記活性領域の周囲に配置された終端領域とがシリコン基板に設けられ、目標耐圧以上の耐圧を持つ半導体装置であって、
前記終端領域はリング領域を有し、
前記リング領域には、リング状の複数のP型リング層が周期的に並んで設けられ、
前記リング領域は、前記複数のP型リング層をそれぞれ含む複数のユニットに分けられ、
各ユニットの幅は一定であり、
前記リング領域内のP型不純物総数をN、前記目標耐圧をBV[V]、各ユニットの幅をSandL[μm]、前記複数のユニットの数をnumとして以下の関係を満たし、
N≧(M×BV)γ、M=104~105、γ=0.55~1.95
SandL×num×Ecri≧2×α×BV
Ecri=2.0~3.0×105[V/cm]、α=100~101
前記複数のユニットの前記P型リング層の幅は前記終端領域の外側に向かって線形的に小さくなることを特徴とする半導体装置。 - トランジスタが形成された活性領域と、前記活性領域の周囲に配置された終端領域とがシリコン基板に設けられ、目標耐圧以上の耐圧を持つ半導体装置であって、
前記終端領域は複数のリング領域を有し、
各リング領域には、リング状の複数のP型リング層が周期的に並んで設けられ、
各リング領域は、前記複数のP型リング層をそれぞれ含む複数のユニットに分けられ、
同じリング領域内では各ユニットの幅は一定であり、
前記複数のリング領域のうちi番目のリング領域内のP型不純物総数をN(i)、前記目標耐圧をBV[V]、前記i番目のリング領域が分担する耐圧をBV(i)[V]、前記i番目のリング領域の各ユニットの幅をSandL(i)[μm]、前記i番目のリング領域内の前記複数のユニットの数をnum(i)として以下の関係を満たし、
N(i)≧(M×BV(i))γ、M=104~105、γ=0.55~1.95
Σ[SandL(i)×num(i)×Emax(i)]≧2×α×BV
BV=ΣBV(i)、Emax(i)≦Ecri、Ecri=2.0~3.0×105[V/cm]、α=100~101
前記複数のユニットの前記P型リング層の幅は前記終端領域の外側に向かって線形的に小さくなることを特徴とする半導体装置。 - 前記P型リング層は、平面視で周期的に配置された複数のストライプ構造を有することを特徴とする請求項1又は2に記載の半導体装置。
- 前記P型リング層は、平面視で周期的に配置された複数のドット構造を有することを特徴とする請求項1又は2に記載の半導体装置。
- 前記終端領域は、前記リング領域の少なくとも一部と重なるP型層を更に備え、
前記P型層の表面濃度は前記P型リング層の表面濃度より小さく
前記P型層の深さは前記P型リング層の深さより深いことを特徴とする請求項1~4の何れか1項に記載の半導体装置。
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