JP7039937B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7039937B2 JP7039937B2 JP2017214981A JP2017214981A JP7039937B2 JP 7039937 B2 JP7039937 B2 JP 7039937B2 JP 2017214981 A JP2017214981 A JP 2017214981A JP 2017214981 A JP2017214981 A JP 2017214981A JP 7039937 B2 JP7039937 B2 JP 7039937B2
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- electric field
- field relaxation
- layer
- drift layer
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Description
本発明の第1実施形態に係る半導体装置は、図1に示すように、活性領域101と、活性領域101を囲んでその周辺に配置された耐圧構造領域102を備える。図1では、活性領域101に、第1導電型(n-型)のドリフト層2の上部に設けられたトレンチゲート構造のMISFETを活性素子として含む場合を例示している。
本発明の第1実施形態の変形例に係る半導体装置の耐圧構造領域を図10に示す。図10に示すように、本発明の第1実施形態の変形例に係る半導体装置の耐圧構造領域においては、ドリフト層2の上面に設けられたp型のベース領域6が段差部を有さず、耐圧構造領域の外側端部付近まで延伸して第3電界緩和層6として機能する。
本発明の第2実施形態に係る半導体装置は、図15に示すように、活性領域201と、活性領域201の周辺に配置された耐圧構造領域202を備える。図15では、活性領域201に、第1導電型(n-型)のドリフト層32の上部に設けられたプレーナゲート構造のMISFETを活性素子として含む場合を例示している。
本発明の第2実施形態の変形例に係る半導体装置の耐圧構造領域を図22に示す。図22に示すように、本発明の第2実施形態の変形例に係る半導体装置の耐圧構造領域において、ドリフト層32の上面に設けられたp型のベース領域34が段差部を有さず、耐圧構造領域の外側端部付近まで延伸して電界緩和層34として機能する。
上記のように、本発明は実施形態によって記載したが、この開示の一部をなす論述及び図面は本発明を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施形態、実施例及び運用技術が明らかとなろう。
2,2a,2b,32,70…ドリフト層
3…電流拡散層
4…第1ベース底部埋込領域(電界緩和層)
4a,5a,21a,33a,51a…本体部
4b,4c,4d,4e,5b,5c,5d,5e,6a,6b,6c,21b,21c,21d,21e,22a,22b,22c,22d,22e,22f,22g,22h,33b,33c,33d,33e,34a,34b,34c,51b,51c,51d,51e,52a,52b,52c,52d,52e,52f,52g,52h…空間変調部
4x,71…第1ベース底部埋込領域
4y…ゲート底部保護領域
5…第2ベース底部埋込領域(電界緩和層)
5x,72…第2ベース底部埋込領域
6…ベース領域(電界緩和層)
6x,34z…段差部
7a,7b,7c,35a,35b,74…ベースコンタクト領域
8,36a,36b…ソース領域
9,38…ゲート絶縁膜
10,39…ゲート電極
11,40…層間絶縁膜
12,42,43,44…保護膜
13…バリアメタル層
14,41…ソース電極
15…配線層
16…ゲート電極パッド
17,45…ドレイン電極
21,51,75…第1JTE領域
22,52,76…第2JTE領域
23,53,77…チャネルストッパ
24,24a,24b,24c,24d,54,54a,54b,54c,54d…n型領域
25…トレンチ
33…ベース底部埋込領域(電界緩和層)
33x…ベース底部埋込領域
34…ベース領域(電界緩和層)
34x,34y,73…ベース領域
37…JFET領域
101,201…活性領域
102,202…耐圧構造領域
Claims (7)
- 活性領域と、
前記活性領域の周囲に配置された、前記活性領域に含まれるドリフト層の上部に設けられ、前記ドリフト層とは反対導電型の電界緩和領域を有する耐圧構造領域
とを備え、
前記電界緩和領域の深さが外側に向かうにつれて浅くなり、前記電界緩和領域の外側端部に空間変調部が設けられ、
前記電界緩和領域の深さが深いほど、前記電界緩和領域の不純物密度が高いことを特徴とする半導体装置。 - 活性領域と、
前記活性領域の周囲に配置された、前記活性領域に含まれるドリフト層の上部に設けられ、前記ドリフト層とは反対導電型の電界緩和領域を有する耐圧構造領域
とを備え、
前記電界緩和領域の深さが外側に向かうにつれて浅くなり、前記電界緩和領域の外側端部に空間変調部が設けられ、
前記電界緩和領域の不純物密度が、外側に向かうにつれて低くなることを特徴とする半導体装置。 - 活性領域と、
前記活性領域の周囲に配置された、前記活性領域に含まれるドリフト層の上部に設けられ、前記ドリフト層とは反対導電型の電界緩和領域を有する耐圧構造領域
とを備え、
前記電界緩和領域の深さが外側に向かうにつれて浅くなり、前記電界緩和領域の外側端部に空間変調部が設けられ、
前記電界緩和領域が、
前記ドリフト層の内部に設けられ、外側端部に空間変調部を有する前記反対導電型の第1電界緩和層と、
前記第1電界緩和層の上面に接するように、前記ドリフト層の上部に前記第1電界緩和層よりも外側まで設けられ、外側端部に空間変調部を有する前記反対導電型の第2電界緩和層と、
前記第2電界緩和層の上面に接するように、前記第2電界緩和層よりも外側まで設けられ、外側端部に空間変調部を有し、前記第2電界緩和層よりも低不純物密度の前記反対導電型の接合終端構造部
とを備えることを特徴とする半導体装置。 - 前記接合終端構造部が、
外側端部に空間変調部を有する第1接合終端領域と、
前記第1接合終端領域と同じ深さで前記第1接合終端領域の外側に設けられ、外側端部に空間変調部を有する第2接合終端領域
とを備えることを特徴とする請求項3に記載の半導体装置。 - 活性領域と、
前記活性領域の周囲に配置された、前記活性領域に含まれるドリフト層の上部に設けられ、前記ドリフト層とは反対導電型の電界緩和領域を有する耐圧構造領域
とを備え、
前記電界緩和領域の深さが外側に向かうにつれて浅くなり、前記電界緩和領域の外側端部に空間変調部が設けられ、
前記電界緩和領域が、
前記ドリフト層の内部に設けられ、外側端部に空間変調部を有する前記反対導電型の第1電界緩和層と、
前記第1電界緩和層の上面に接するように、前記ドリフト層の上部に前記第1電界緩和層よりも外側まで設けられ、外側端部に空間変調部を有する前記反対導電型の第2電界緩和層と、
前記第2電界緩和層の上面に接するように、前記ドリフト層の上面に前記第2電界緩和層よりも外側まで設けられ、外側端部に空間変調部を有し、前記第2電界緩和層よりも低不純物密度の前記反対導電型の第3電界緩和層
とを備えることを特徴とする半導体装置。 - 活性領域と、
前記活性領域の周囲に配置された、前記活性領域に含まれるドリフト層の上部に設けられ、前記ドリフト層とは反対導電型の電界緩和領域を有する耐圧構造領域
とを備え、
前記電界緩和領域の深さが外側に向かうにつれて浅くなり、前記電界緩和領域の外側端部に空間変調部が設けられ、
前記電界緩和領域が、
前記ドリフト層の上部に設けられ、外側端部に空間変調部を有する前記反対導電型の電界緩和層と、
前記電界緩和層の上面に接するように、前記電界緩和層よりも外側まで設けられ、外側端部に空間変調部を有し、前記電界緩和層よりも低不純物密度の前記反対導電型の接合終端構造部
とを備えることを特徴とする半導体装置。 - 活性領域と、
前記活性領域の周囲に配置された、前記活性領域に含まれるドリフト層の上部に設けられ、前記ドリフト層とは反対導電型の電界緩和領域を有する耐圧構造領域
とを備え、
前記電界緩和領域の深さが外側に向かうにつれて浅くなり、前記電界緩和領域の外側端部に空間変調部が設けられ、
前記電界緩和領域が、
前記ドリフト層の上部に設けられ、外側端部に空間変調部を有する前記反対導電型の第1電界緩和層と、
前記第1電界緩和層の上面に接するように、前記ドリフト層の上面に前記第1電界緩和層よりも外側まで設けられ、外側端部に空間変調部を有し、前記第1電界緩和層よりも低不純物密度の前記反対導電型の第2電界緩和層
とを備えることを特徴とする半導体装置。
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