TW201719888A - 具有漸變濃度之邊緣終端結構的功率半導體裝置 - Google Patents

具有漸變濃度之邊緣終端結構的功率半導體裝置 Download PDF

Info

Publication number
TW201719888A
TW201719888A TW104138971A TW104138971A TW201719888A TW 201719888 A TW201719888 A TW 201719888A TW 104138971 A TW104138971 A TW 104138971A TW 104138971 A TW104138971 A TW 104138971A TW 201719888 A TW201719888 A TW 201719888A
Authority
TW
Taiwan
Prior art keywords
substrate
semiconductor
edge termination
concentration
top surface
Prior art date
Application number
TW104138971A
Other languages
English (en)
Other versions
TWI581425B (zh
Inventor
Chih-Fang Huang
Kung-Yen Lee
Chia-Hui Cheng
sheng-zhong Wang
Original Assignee
Macroblock Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=57389338&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=TW201719888(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Macroblock Inc filed Critical Macroblock Inc
Priority to TW104138971A priority Critical patent/TWI581425B/zh
Priority to CN201611033986.8A priority patent/CN106783940B/zh
Priority to US15/359,209 priority patent/US9865676B2/en
Priority to EP16200052.5A priority patent/EP3174104B1/en
Priority to JP2016226847A priority patent/JP6334655B2/ja
Application granted granted Critical
Publication of TWI581425B publication Critical patent/TWI581425B/zh
Publication of TW201719888A publication Critical patent/TW201719888A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827Vertical transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution

Landscapes

  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一種具有漸變濃度之邊緣終端結構的功率半導體裝置,包含一基板、一本體,及一電極單元。本體形成於基板上並包括主動部、環圍主動部的邊緣終端部,及絕緣氧化層,主動部具有多個相互並聯的電晶體,邊緣終端部具有呈第一型半導體特性的第一半導體區、呈第二型半導體特性的第二半導體區,及遠離基板的頂面,絕緣氧化層與基板相間隔地形成於邊緣終端部,第一半導體特性的濃度由頂面往基板方向遞減。電極單元包括與電晶體連接且部分形成於絕緣氧化層上的第一電極層,及與本體相間隔地形成於基板的第二電極層。

Description

具有漸變濃度之邊緣終端結構的功率半導體裝置
本發明是有關於一種功率半導體裝置,特別是指一種具有漸變濃度之邊緣終端結構的功率半導體裝置。
功率半導體裝置通常包含一主動部及一圍繞該主動部邊緣而用以將主動部累積的靜電荷或不必要的漏電流帶走的邊緣終端部。
一般來說,該主動部由多個電晶體並聯而成,形成多個彼此相互交替排列的n型半導體柱與p型半導體柱。然而,此種邊緣終端部結構的n型半導體柱與p型半導體柱彼此的間距與寬度需精準設計,若間距過大會無法發揮承受崩潰電壓的功效而提早於該主動部崩潰,若其彼此間距過小則n型半導體柱與p型半導體柱之間的空乏區無法有效延伸,而無法承受較高的崩潰電壓。
另一種邊緣終端部則是形成均勻的一n型半導體層與一p型半導體層而構成一二極體結構。然而,以此種方式形成邊緣終端部時,於降低n型半導體層與p型半導體層的載子濃度時,雖能 提升該邊緣終端部所構成的二極體的空乏區,但二極體的電場則會因低載子濃度而變小且具有不均勻的電力線,從而僅能承受較小的崩潰電壓;當提高n型半導體層與p型半導體層的載子濃度時,雖能提高二極體的電場,但其空乏區則會隨之變小,也僅能承受較小的崩潰電壓。
因此,本發明之目的,即在提供一種具有漸變濃度之邊緣終端結構的功率半導體裝置。
於是,本發明具有漸變濃度之邊緣終端結構的功率半導體裝置,包含一基板、一本體,及一電極單元。
該本體形成於該基板上,並包括一主動部、一環圍該主動部的邊緣終端部,及一絕緣氧化層,該主動部具有多個相互並聯的電晶體,該邊緣終端部具有一呈一第一型半導體特性的第一半導體區、一呈一第二型半導體特性的第二半導體區,及一遠離該基板的頂面,該絕緣氧化層與該基板相間隔地形成於該邊緣終端部上,該第一半導體特性的濃度由該頂面往該基板方向遞減。
該電極單元包括一與該等電晶體連接且部分形成於該絕緣氧化層上的第一電極層,及一與該本體相間隔地形成於該基板的第二電極層。
本發明之功效在於:藉由讓該第一半導體區的該第一型半導體特性的濃度由該絕緣氧化層往該基板方向遞減,當對該邊緣終端部施加電壓時,能延伸該第一半導體區與該第二半導體區之間的空乏區並具有均勻的電力線,從而能承受較高的崩潰電壓。
2‧‧‧基板
3‧‧‧本體
31‧‧‧主動部
311‧‧‧第一柱狀區
312‧‧‧第二柱狀區
313‧‧‧井區
314‧‧‧源極區
315‧‧‧閘極區
322‧‧‧第二半導體區
323‧‧‧表面
324‧‧‧表面
325‧‧‧絕緣氧化層
33‧‧‧空乏區
4‧‧‧電極單元
41‧‧‧第一電極層
42‧‧‧第二電極層
316‧‧‧電晶體
32‧‧‧邊緣終端部
320‧‧‧頂面
321‧‧‧第一半導體區
X‧‧‧第一方向
Y‧‧‧第二方向
R‧‧‧徑向
本發明之其他的特徵及功效,將於參照圖式的實施方式中清楚地呈現,其中:圖1是一示意圖,說明本發明具有漸變濃度之邊緣終端結構的功率半導體裝置之省略一絕緣氧化層與一電極單元的一第一實施例;圖2是一剖面側視示意圖,輔助說明圖1沿II-II直線之該第一實施例;圖3是一模擬示意圖,輔助說明圖2的一邊緣終端部;圖4是一模擬示意圖,輔助說明圖2的該邊緣終端部;圖5是一模擬示意圖,說明本發明具有漸變濃度之邊緣終端結構的功率半導體裝置的一第二實施例;及圖6是一示意圖,說明本發明具有漸變濃度之邊緣終端結構的功率半導體裝置的一第三實施例。
在本發明被詳細描述之前,應當注意在以下的說明內容中,類似的元件是以相同的編號來表示。
參閱圖1與圖2,本發明具有漸變濃度之邊緣終端結構的功率半導體裝置之一第一實施例,包含一由半導體材料所構成的基板2、一形成於該基板2上的本體3,及一形成於該本體3上的電極單元4。
具體地說,該本體3包括一主動部31、一環圍該主動部31的邊緣終端部32,及一絕緣氧化層325。該主動部31包括多個彼此交錯排列且分別呈第一型半導體特性與第二型半導體特性的第一柱狀區311及第二柱狀區312、該每一個第一柱狀區311具有一自該主動部31頂面往該基板2方向延伸的井區313、兩個形成於該井區313,彼此間隔且鄰近該主動部31頂面的源極區314,及多個分別形成於該等第二柱狀區312的頂面,並分別與相鄰的兩個源極區314連接的閘極區315,從而構成多個相互並聯且具有超級接面(super junction)的電晶體316。要說明的是,無論是具有超級接面電晶體或一般電晶體均可適用於構成該主動部31,由於該等電晶體316細部結構為本領域技術人員所周知,且非本發明之重點,因此,於此不加以贅述。
該邊緣終端部32具有一遠離該基板2的頂面320、一呈一第一型半導體特性且由該頂面320向該基板2方向延伸的第一半 導體區321,及一呈一第二型半導體特性且由該基板2沿該第一半導體區321的邊緣往遠離該基板2方向延伸至該頂面320的第二半導體區322,且該第一半導體區321與該第二半導體區322分別具有一表面323、324;其中,於本實施例中,該第一半導體區321的該表面323與該第二半導體區322的該表面324共同構成該邊緣終端部32的頂面320。該絕緣氧化層325與該基板2相間隔地形成於該邊緣終端部32的頂面320上。
該電極單元4包括一形成於該本體3而與該等電晶體316的源極區314連接,並部分形成於該絕緣氧化層325上而與該邊緣終端部32耦接的第一電極層41,及一與該本體3相間隔地形成於於基板2的第二電極層42。
詳細地說,該第一型半導體與該第二型半導體的摻雜原子並無特別限制,於本實施例中,該第一型半導體與該第二型半導體分別是以含有3價原子的p型半導體與含有5價原子的n型半導體為例作說明。該第一型半導體特性的濃度是由該第一半導體區321鄰近該主動部31與該頂面320處往邊緣終端部32與該基板2處以一徑向R的方向發散而呈梯度地降低。
更詳細地說,由於該邊緣終端部32的形成是先於該基板2上磊晶成長n型半導體層後,再對此n型半導體層進行摻雜,從而構成具有p型半導體特性的該第一半導體區321。換句話說,圖2 的該第一半導體區321中所顯示之陣列的方格P是用以示意摻雜過程,也就是說,此摻雜過程是局部進行摻雜,並由該頂面320至該基板2的垂直方向及該主動部31至該邊緣終端部32水平方向調整摻雜濃度,使p型半導體特性沿該該頂面320至該基板2的垂直方向及該主動部31至該邊緣終端部32水平方向呈梯度遞減。本實施例是以離子佈值方式配合一光罩孔洞及針對多次堆疊的磊晶層之不同層施打不同的離子濃度來實施作說明,然而,實際摻雜方式並無特別限制。詳細地說,本實施例是透過離子佈植製程,藉由先後執行以不同劑量來控制摻雜濃度來做垂直摻雜調變,再搭配光罩孔洞的開口率以於該邊緣終端部32的頂面320控制離子通過來做橫向摻雜調變,來達成具有斜向漸變濃度的第一半導體區321。
因此,以實際情況而言,圖2位於靠近該基板2及該邊緣終端部32尾端的方格P處雖然仍有進行p型半導體摻雜,但是因為具有最低的p型半導體特性濃度,因此,其整體半導體特性加總之後(即n型半導體特性與p型半導體特性的加總),其方格P的頂層與靠近該主動部31處,會幾乎屬於p型半導體特性;而方格P靠近該基板2的邊緣終端部32處會幾乎屬於n型半導體特性。
因此,當功率半導體裝置施加電壓產生的一空乏區33於實際情況會位於如圖2所示之處。
此處值得一提的是,於該第一實施例中,定義一平行該基板2並由該主動部31指向該邊緣終端部32為第一方向X,及一垂直該第一方向X並由該頂面320指向該基板2為第二方向Y,該第一半導體區321可視為是由沿該第一方向X具有N層不同濃度的半導體層(圖未示,N>1),及沿該第二方向Y具有M層半導體層(圖未示,M>1)所構成。較佳地,相鄰的半導體層的第一型半導體特性的濃度差異小於20%,且該等N層半導體層彼此相連,而該等M層半導體層則可彼此相連或彼此不相連。
配合地參閱圖3與圖4,圖3是使用半導體元件與製程模擬軟體(TACD)進行該第一實施例的模擬圖,而呈現該邊緣終端部32之該第一半導體區321所具有第一型半導體特性濃度漸變的特性。一般來說,與該主動部31耦接的該邊緣終端部32主要作用在於導引多餘電荷至外界,以防止該主動部31崩潰。當使用本發明具有漸變濃度之邊緣終端結構的功率半導體裝置時,外界分別提供該基板2(此處作為該電晶體316與邊緣終端部32的汲極區)與源極區314之間,及該閘極區315與該源極區314之間一正電壓時,該電晶體316成開啟狀態。由於本實施例該邊緣終端部32的第一半導體區321的第一型半導體特性具有漸變的濃度,由圖3可知此漸變濃度的特性能使該邊緣終端部32因在汲極區施加正電壓所產生的空乏區33能進行延伸。
進一步地,圖4顯示有該邊緣終端部32的電力線示意圖,由圖4可知由於第一半導體區321中的第一型半導體特性的濃度是斜下的漸變,因此,該主動部31至該邊緣終端部32及該頂面320至該基板2的p型摻雜濃度變化由高到低,從而使得電力線容易延伸,而此一特點能讓本發明功率半導體裝置相較於現有的功率半導體裝置,在製作承受同樣的崩潰電壓的該邊緣終端部32時,能製作成較小的體積。詳細地說,由於現有的功率半導體裝置的邊緣終端部是使用讓第一型半導體特性與第二型半導體特性呈單一濃度狀態的二極體,因此,若要承受與本發明相當的崩潰電壓時,必須讓邊緣終端部的整體體積增加,以提高阻值而能承受較高的崩潰電壓。由此可知,本發明該第一半導體區321所具有之濃度漸變的第一型半導體特性不僅能延伸該邊緣終端部32產生的空乏區33,還能縮小邊緣終端部32的體積而承受較高的崩潰電壓。
配合地參閱圖5,本發明具有漸變濃度之邊緣終端結構的功率半導體裝置之一第二實施例大致是相同於該第一實施例,其不同之處在於,該第一半導體區321的第一型半導體特性的濃度只有該頂面320垂直往該基板2漸變。詳細地說,圖5顯示有模擬該第二實施例的邊緣終端部32的模擬圖,於該第二實施例中,該第一型半導體特性的濃度只有沿該第二方向Y降低。據此,由圖5的TACD 模擬圖可推知,當第一型半導體特性的濃度若僅沿該第二方向Y降低時,亦能有效延伸於該3產生的空乏區33。
配合地參閱圖6,本發明具有漸變濃度之邊緣終端結構的功率半導體裝置之一第三實施例大致是相同於該第一實施例,其不同之處在於,該第三實施例是同時以兩種摻雜源,對該主動部31及該邊緣終端部32進行摻雜,以此方式進行能使該主動部31的效能更好。詳細地說,本實施例的摻雜方式主要是藉由建構該第二半導體區322與該第二柱狀區312時,以於該每一層磊晶層中同時摻雜3價原子與5價原子,且讓3價原子的摻雜量沿該頂面320往該基板2(即該第二方向Y)及由該主動部31往該邊緣終端部32方向(即該第一方向X)遞減,而讓5價原子的摻雜量沿該頂面320往該基板2(即該第二方向Y)及由該主動部31往該邊緣終端部32的方向(即該第一方向X)遞增。也就是說,總體來看,以此方式摻雜完成的該邊緣終端部32的p型半導體濃度,會由靠近該主動部31與該頂面320處沿該基板2與該邊緣終端部32方向逐漸遞減;而n型半導體濃度,則會由該頂面320往該基板2方向(即該第二方向Y)遞增及由該主動部31往該邊緣終端部32的方向(即該第一方向X)遞增,藉著對每一層磊晶層施打不同劑量的3價原子及5價原子,及讓通過3價原子的光罩的開口改變而造成與第一實施例相同的效果。
綜上所述,本發明具有漸變濃度之邊緣終端結構的功率半導體裝置,藉由讓該邊緣終端部32的該第一半導體區321的第一型半導體特性的濃度由該頂面320往該基板2及該主動部31往該邊緣終端部32方向呈梯度遞減,並讓相鄰濃度差異小於20%,使對該邊緣終端部32施加電壓時,能延伸該第一半導體區321與該第二半導體區322之間的空乏區33並具有均勻的電力線,從而使功率半導體裝置能承受較高的崩潰電壓,故確實能達成本發明之目的。
惟以上所述者,僅為本發明之實施例而已,當不能以此限定本發明實施之範圍,凡是依本發明申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾,皆仍屬本發明專利涵蓋之範圍內。
2‧‧‧基板
3‧‧‧本體
31‧‧‧主動部
311‧‧‧第一柱狀區
312‧‧‧第二柱狀區
313‧‧‧井區
314‧‧‧源極區
315‧‧‧閘極區
322‧‧‧第二半導體區
323‧‧‧表面
324‧‧‧表面
325‧‧‧絕緣氧化層
33‧‧‧空乏區
4‧‧‧電極單元
41‧‧‧第一電極層
42‧‧‧第二電極層
316‧‧‧電晶體
32‧‧‧邊緣終端部
320‧‧‧頂面
321‧‧‧第一半導體區
X‧‧‧第一方向
Y‧‧‧第二方向
R‧‧‧徑向

Claims (10)

  1. 一種具有漸變濃度之邊緣終端結構的功率半導體裝置,包含:一基板;一本體,形成於該基板上,並包括一主動部、一環圍該主動部的邊緣終端部,及一絕緣氧化層,該主動部具有多個相互並聯的電晶體,該邊緣終端部具有一呈一第一型半導體特性的第一半導體區、一呈一第二型半導體特性的第二半導體區,及一遠離該基板的頂面,該絕緣氧化層與該基板相間隔地形成於該邊緣終端部上,該第一半導體特性的濃度由該頂面往該基板方向遞減;及一電極單元,包括一與該等電晶體連接且部分形成於該絕緣氧化層上的第一電極層,及一與該本體相間隔地形成於該基板的第二電極層。
  2. 如請求項1所述的具有漸變濃度之邊緣終端結構的功率半導體裝置,其中,該第一半導體區由該頂面向該基板方向延伸,該第二半導體區由該基板沿該第一半導體區的邊緣往遠離該基板方向延伸至該頂面。
  3. 如請求項2所述的具有漸變濃度之邊緣終端結構的功率半導體裝置,其中,該第一型半導體特性的濃度由該第一半導體區之鄰近該主動部與該頂面處往該邊緣終端部與該基板處呈徑向發散地降低。
  4. 如請求項2所述的具有漸變濃度之邊緣終端結構的功率半導體裝置,其中,定義一平行該基板並從該主動部往該邊 緣終端部為第一方向,及一垂直該第一方向的並從該頂面至該基板為第二方向,該第一型半導體特性的濃度沿該第二方向降低。
  5. 如請求項2所述的具有漸變濃度之邊緣終端結構的功率半導體裝置,其中,定義一平行該基板並從該主動部往該邊緣終端部為第一方向,及一垂直該第一方向並從該頂面至該基板為第二方向,該第一型半導體特性的濃度沿該第一方向降低。
  6. 如請求項2所述的具有漸變濃度之邊緣終端結構的功率半導體裝置,其中,該第一半導體區沿該第一方向具有N層半導體層,N>1,相鄰的該半導體層的第一型半導體特性的濃度差異小於20%。
  7. 如請求項2所述的具有漸變濃度之邊緣終端結構的功率半導體裝置,其中,該第一半導體區沿該第二方向具有M層半導體層,M>1,相鄰的該半導體層的第一型半導體特性的濃度差異小於20%。
  8. 如請求項2所述的具有漸變濃度之邊緣終端結構的功率半導體裝置,其中,該第一半導體區沿該第一方向具有N層半導體層,N>1,該等N層半導體層彼此相連,該第一半導體區沿該第二方向具有M層半導體層,M>1,該等M層半導體層為彼此相連及彼此不相連其中一者。
  9. 如請求項2所述的具有漸變濃度之邊緣終端結構的功率半導體裝置,其中,定義一平行該基板並從該主動部往該邊緣終端部為第一方向,及一垂直該第一方向的並從該頂面 至該基板為第二方向,該第一型半導體特性的濃度由該第一半導體區之鄰近該主動部與該頂面處往該邊緣終端部與該基板處呈徑向發散地降低,該第二型半導體特性的濃度沿該第二方向的反方向降低。
  10. 如請求項2所述的具有漸變濃度之邊緣終端結構的功率半導體裝置,其中,定義一平行該基板並從該主動部往該邊緣終端部為第一方向,及一垂直該第一方向的並從該頂面至該基板為第二方向,該第一型半導體特性的濃度由該第一半導體區之鄰近該主動部與該頂面處往該邊緣終端部與該基板處呈徑向發散地降低,該第二型半導體特性的濃度沿該第一方向的反方向降低。
TW104138971A 2015-11-24 2015-11-24 And a power semiconductor device having an edge terminal structure having a gradation concentration TWI581425B (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
TW104138971A TWI581425B (zh) 2015-11-24 2015-11-24 And a power semiconductor device having an edge terminal structure having a gradation concentration
CN201611033986.8A CN106783940B (zh) 2015-11-24 2016-11-22 具有渐变浓度的边缘终端结构的功率半导体装置
US15/359,209 US9865676B2 (en) 2015-11-24 2016-11-22 Power semiconductor device
EP16200052.5A EP3174104B1 (en) 2015-11-24 2016-11-22 Power semiconductor device
JP2016226847A JP6334655B2 (ja) 2015-11-24 2016-11-22 パワー半導体デバイス

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW104138971A TWI581425B (zh) 2015-11-24 2015-11-24 And a power semiconductor device having an edge terminal structure having a gradation concentration

Publications (2)

Publication Number Publication Date
TWI581425B TWI581425B (zh) 2017-05-01
TW201719888A true TW201719888A (zh) 2017-06-01

Family

ID=57389338

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104138971A TWI581425B (zh) 2015-11-24 2015-11-24 And a power semiconductor device having an edge terminal structure having a gradation concentration

Country Status (5)

Country Link
US (1) US9865676B2 (zh)
EP (1) EP3174104B1 (zh)
JP (1) JP6334655B2 (zh)
CN (1) CN106783940B (zh)
TW (1) TWI581425B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016118012A1 (de) * 2016-09-23 2018-03-29 Infineon Technologies Ag Halbleiterbauelement und Verfahren zum Bilden eines Halbleiterbauelements
CN110212014A (zh) * 2019-04-30 2019-09-06 上海功成半导体科技有限公司 超结器件终端结构及其制备方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002170955A (ja) * 2000-09-25 2002-06-14 Toshiba Corp 半導体装置およびその製造方法
JP3908572B2 (ja) 2002-03-18 2007-04-25 株式会社東芝 半導体素子
JP3873798B2 (ja) * 2002-04-11 2007-01-24 富士電機デバイステクノロジー株式会社 炭化けい素半導体素子およびその製造方法
JP3634830B2 (ja) * 2002-09-25 2005-03-30 株式会社東芝 電力用半導体素子
JP4945055B2 (ja) 2003-08-04 2012-06-06 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5261640B2 (ja) * 2005-12-09 2013-08-14 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置の製造方法
JP2007173418A (ja) * 2005-12-20 2007-07-05 Toshiba Corp 半導体装置
JP2008103529A (ja) * 2006-10-19 2008-05-01 Toyota Central R&D Labs Inc 半導体装置
EP2118933A1 (en) * 2007-01-10 2009-11-18 Freescale Semiconductor, Inc. Semiconductor device and method of forming a semiconductor device
JP2008187125A (ja) * 2007-01-31 2008-08-14 Toshiba Corp 半導体装置
JP2011049393A (ja) * 2009-08-27 2011-03-10 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP6009731B2 (ja) * 2010-10-21 2016-10-19 富士電機株式会社 半導体装置
JP5664142B2 (ja) * 2010-11-09 2015-02-04 富士電機株式会社 半導体装置
JP5287893B2 (ja) * 2011-02-08 2013-09-11 株式会社デンソー 半導体装置およびその製造方法
DE102012200056A1 (de) 2011-01-12 2012-07-12 Denso Corporation Halbleitervorrichtung und Verfahren zur Herstellung hiervon
JP2013093560A (ja) * 2011-10-06 2013-05-16 Denso Corp 縦型半導体素子を備えた半導体装置
US8841718B2 (en) 2012-01-16 2014-09-23 Microsemi Corporation Pseudo self aligned radhard MOSFET and process of manufacture
WO2013132568A1 (ja) * 2012-03-05 2013-09-12 三菱電機株式会社 半導体装置
JP5559232B2 (ja) * 2012-04-06 2014-07-23 株式会社東芝 電力用半導体素子
JP6197294B2 (ja) * 2013-01-16 2017-09-20 富士電機株式会社 半導体素子
US9349854B2 (en) * 2013-10-04 2016-05-24 Infineon Technologies Ag Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
JP2017098550A (ja) 2017-06-01
TWI581425B (zh) 2017-05-01
US9865676B2 (en) 2018-01-09
CN106783940A (zh) 2017-05-31
US20170148870A1 (en) 2017-05-25
CN106783940B (zh) 2020-08-04
EP3174104B1 (en) 2021-08-11
EP3174104A1 (en) 2017-05-31
JP6334655B2 (ja) 2018-05-30

Similar Documents

Publication Publication Date Title
JP5991383B2 (ja) 半導体装置の製造方法
JP2010135791A (ja) 半導体素子及びその製造方法
CN106463503A (zh) 半导体装置
US10032904B2 (en) Semiconductor device with non-isolated power transistor with integrated diode protection
JP2019521529A (ja) パワーデバイス及びその製造方法
TWI524390B (zh) A wafer structure, and a power element to which it is applied
JP6104743B2 (ja) ショットキーダイオードを内蔵するfet
JP6237064B2 (ja) 半導体装置
JP2017084998A (ja) スーパージャンクション型mosfetデバイスおよび半導体チップ
US11631763B2 (en) Termination for trench field plate power MOSFET
JP6770177B2 (ja) デプレッションモード接合電界効果トランジスタと統合されたデバイスおよび該デバイスを製造するための方法
US10090408B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP6381067B2 (ja) 半導体装置および半導体装置の製造方法
JP6391136B2 (ja) 高電圧ダイオード
JP4998524B2 (ja) 半導体装置
TWI591792B (zh) 靜電放電裝置及其製造方法
TWI581425B (zh) And a power semiconductor device having an edge terminal structure having a gradation concentration
CN104347614A (zh) 功率半导体器件及其制造方法
CN105977308B (zh) 超级势垒整流器器件及其制备方法
CN110323138B (zh) 一种ldmos器件的制造方法
KR20160032654A (ko) 반도체 장치 및 그 제조 방법
US20130093013A1 (en) High voltage transistor and manufacturing method therefor
TWI798254B (zh) 用於具有快速切換能力的電荷平衡半導體功率裝置之系統和方法
CN104124276B (zh) 一种超级结器件及其制作方法
KR101887910B1 (ko) SiC MOSFET 전력 반도체 소자 및 그 제조방법