JP6391136B2 - 高電圧ダイオード - Google Patents
高電圧ダイオードInfo
- Publication number
- JP6391136B2 JP6391136B2 JP2013199779A JP2013199779A JP6391136B2 JP 6391136 B2 JP6391136 B2 JP 6391136B2 JP 2013199779 A JP2013199779 A JP 2013199779A JP 2013199779 A JP2013199779 A JP 2013199779A JP 6391136 B2 JP6391136 B2 JP 6391136B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- terminal
- terminal contact
- conductivity type
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 claims description 135
- 239000004065 semiconductor Substances 0.000 claims description 107
- 238000002955 isolation Methods 0.000 claims description 69
- 230000002093 peripheral effect Effects 0.000 claims description 50
- 238000000034 method Methods 0.000 claims description 35
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 21
- 239000012212 insulator Substances 0.000 claims description 17
- 238000000926 separation method Methods 0.000 claims description 3
- 239000007943 implant Substances 0.000 description 67
- 239000010410 layer Substances 0.000 description 64
- 238000002513 implantation Methods 0.000 description 42
- 239000012535 impurity Substances 0.000 description 21
- 239000002019 doping agent Substances 0.000 description 16
- 230000015556 catabolic process Effects 0.000 description 15
- 230000008901 benefit Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 5
- 230000000670 limiting effect Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000005465 channeling Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
- H01L29/66204—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
説明を簡潔かつ明瞭にするために、図面に示す要素は必ずしも原寸に比例して描かれてはいないことは諒解されよう。たとえば、明瞭性および理解を促進および向上する目的で、いくつかの要素の寸法は、他の要素に対して誇張されている。さらに、適切であると考えられる場合、対応するまたは類似の要素を表すために参照符号が複数の図面の間で反復されている。
Claims (13)
- 半導体ダイオードデバイスであって、
第1の導電型の半導体基板領域と、
前記半導体基板領域を電気的に分離するための分離構造と、
前記半導体基板領域内に形成される第1の導電型の第1の高濃度ドープ・端子コンタクト領域と、
前記第1の高濃度ドープ・端子コンタクト領域から離間されるように前記半導体基板領域内に位置する第2の導電型の第2の高濃度ドープ・端子コンタクト領域と、
前記半導体基板領域内で前記第1の高濃度ドープ・端子コンタクト領域の第1の部分の下に位置する前記第1の導電型の第1の端子ウェル領域と、
前記第2の高濃度ドープ・端子コンタクト領域の周りに位置する深い部分、および該深い部分から前記第1の端子ウェル領域まで拡張した浅い部分を含む前記半導体基板領域内に位置する前記第2の導電型の第2の端子ウェル領域とを備え、
前記浅い部分の周縁部は、前記第1の高濃度ドープ・端子コンタクト領域の第2の部分の下に位置し、
前記第1の端子ウェル領域、および前記第2の端子ウェル領域の浅い部分は、
前記第1の高濃度ドープ・端子コンタクト領域の下に位置する接合部を形成する、半導体ダイオードデバイス。 - 前記第1の導電型はp型であり、前記第2の導電型はn型である、請求項1に記載の半導体ダイオードデバイス。
- 前記第2の端子ウェル領域の前記周縁部、および前記第1の高濃度ドープ・端子コンタクト領域は、
前記第1の高濃度ドープ・端子コンタクト領域によって遮蔽された垂直p−n接合部を形成する、請求項1に記載の半導体ダイオードデバイス。 - 前記半導体基板領域の表面上に位置するシャロートレンチ分離領域が、前記第1の高濃度ドープ・端子コンタクト領域と前記第2の高濃度ドープ・端子コンタクト領域との間の唯一の分離である、請求項1に記載の半導体ダイオードデバイス。
- 前記第1の高濃度ドープ・端子コンタクト領域、前記第1の端子ウェル領域、および下層の半導体基板領域は、前記第2の端子ウェル領域の底部および側部を取り囲む、請求項1に記載の半導体ダイオードデバイス。
- 前記分離構造は、
前記半導体基板領域を包囲するように形成されるディープトレンチ分離領域と、
前記半導体基板領域の底部に形成される埋め込み絶縁体層と、
前記半導体基板領域の表面上に形成される少なくとも第1のシャロートレンチ分離領域とを備える、請求項1に記載の半導体ダイオードデバイス。 - 半導体デバイスを製造する方法であって、任意の順序で、
分離構造内に第1の導電型の半導体基板領域を提供することであって、前記分離構造は、前記半導体基板領域を包囲するように形成されるディープトレンチ分離領域と、前記半導体基板領域の底部に形成される埋め込み絶縁体層と、前記半導体基板領域の表面上に形成される少なくとも第1のシャロートレンチ分離領域とを含む、前記第1の導電型の半導体基板領域を提供すること、
前記半導体基板領域の第1の端子コンタクト領域内に前記第1の導電型の第1の高濃度ドープ・端子コンタクト領域を形成すること、
前記半導体基板領域の第2の端子コンタクト領域内に、前記第1の端子コンタクト領域から離間されるように、第2の導電型の第2の高濃度ドープ・端子コンタクト領域を形成すること、
前記半導体基板領域内で、少なくとも前記第1の端子コンタクト領域の下に、最終的に形成されるときに前記第1の端子コンタクト領域と抵抗接触しているように、前記第1の導電型の第1の端子ウェル領域を形成すること、
前記半導体基板領域内で、少なくとも前記第2の端子コンタクト領域の下に、最終的に形成されるときに前記第2の端子コンタクト領域と抵抗接触しているように、前記第2の導電型の第2の端子ウェル領域を形成することを備え、
前記第2の端子ウェル領域は、前記半導体基板領域の前記第1の端子コンタクト領域の下に位置し、最終的に形成されるときに前記第1の端子ウェル領域に隣接している周縁端部まで側方に拡張し、
前記第1の端子ウェル領域と前記第2の端子ウェル領域との間に形成されるカソード−アノード接合部は、前記第1の高濃度ドープ・端子コンタクト領域によって遮蔽されて帯電耐性を増強し、
前記第2の端子ウェル領域を形成することは、
前記半導体基板領域内で前記第2の高濃度ドープ・端子コンタクト領域の周りに前記第2の導電型のディープ端子ウェル領域を形成すること、
前記半導体基板領域内に、前記ディープ端子ウェル領域から前記半導体基板領域の前記第1の端子コンタクト領域の下に位置する周縁端部まで側方に拡張するように、前記第2の導電型のシャロー端子ウェル領域を形成することを含む、方法。 - 前記第1の端子ウェル領域、前記第1の高濃度ドープ・端子コンタクト領域、および下層の半導体基板領域は、前記第2の端子ウェル領域の底部および側部を完全に取り囲む、請求項7に記載の方法。
- シャロートレンチ分離領域のみが前記第1の端子コンタクト領域と前記第2の端子コンタクト領域を離隔する、請求項7に記載の方法。
- 前記第1の導電型の材料を用いて形成される領域はp型領域として形成され、
前記第2の導電型の材料を用いて形成される領域はn型領域として形成される、請求項9に記載の方法。 - 高電圧ダイオードデバイスを形成する方法であって、
埋め込み絶縁体の上に形成され、ディープトレンチ分離領域によって包囲される半導体の第2導電型の基板層を含むセミコンダクタ・オン・インシュレータ基板を提供すること、
前記基板層上にシャロートレンチ分離領域を形成して、第2の端子コンタクトの開口から第1のシャロートレンチ分離領域によって離隔している第1の端子コンタクトの開口を画定することを備え、その後、任意の順序で、
前記基板層内で前記第1の端子コンタクトの開口において、第1の導電型の第1の高濃度ドープ・端子コンタクト領域を選択的に注入すること、
前記第1の導電型の第1のディープ端子ウェル領域を、前記基板層内で前記第1の高濃度ドープ・端子コンタクト領域の周りに選択的に注入すること、
前記第1の導電型の第1のシャロー端子ウェル領域を、前記基板層内で前記第2の端子コンタクトの開口の下に位置する周縁端部まで側方に拡張するように選択的に注入すること、
第2の導電型の第2の周縁端子ウェル領域を、最終的に形成されるときに前記第1のシャロー端子ウェル領域の前記周縁端部に隣接して位置付けられるように、前記基板層内で前記第2の端子コンタクトの開口の下に選択的に注入することを備え、その後、
前記第2の導電型の第2の高濃度ドープ・端子コンタクト領域を、前記第1のシャロートレンチ分離領域によって前記第1の高濃度ドープ・端子コンタクト領域から離間され、離隔されるように、前記基板層内で前記第2の端子コンタクトの開口内に選択的に注入することを備え、
前記第2の周縁端子ウェル領域および前記第2の高濃度ドープ・端子コンタクト領域を選択的に注入することは、
前記基板層内で、前記第2の高濃度ドープ・端子コンタクト領域によって遮蔽されて帯電耐性を増強する、前記第2の端子コンタクトの開口の下にカソード−アノード接合部を形成することを含む、方法。 - 前記第2の周縁端子ウェル領域および前記第2の高濃度ドープ・端子コンタクト領域は、
前記基板層内に前記第1のシャロー端子ウェル領域に隣接してRESURF層を形成する、請求項11に記載の方法。 - 前記第2の導電型はp型であり、前記第1の導電型はn型である、請求項11に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/656,122 | 2012-10-19 | ||
US13/656,122 US9040384B2 (en) | 2012-10-19 | 2012-10-19 | High voltage diode |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014086723A JP2014086723A (ja) | 2014-05-12 |
JP6391136B2 true JP6391136B2 (ja) | 2018-09-19 |
Family
ID=50484605
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013199779A Active JP6391136B2 (ja) | 2012-10-19 | 2013-09-26 | 高電圧ダイオード |
Country Status (3)
Country | Link |
---|---|
US (2) | US9040384B2 (ja) |
JP (1) | JP6391136B2 (ja) |
CN (1) | CN103779429B (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9093567B2 (en) * | 2013-11-05 | 2015-07-28 | Freescale Semiconductor, Inc. | Diodes with multiple junctions and fabrication methods therefor |
US9646964B2 (en) * | 2015-07-23 | 2017-05-09 | Vanguard International Semiconductor Corporation | Semiconductor device |
CN107919385B (zh) * | 2017-11-06 | 2020-08-11 | 上海华虹宏力半导体制造有限公司 | 高压隔离环及其制造方法 |
US10930747B2 (en) | 2019-06-04 | 2021-02-23 | Nxp B.V. | Semiconductor device with an encircled electrode |
CN110211957B (zh) * | 2019-06-24 | 2024-06-11 | 南京华瑞微集成电路有限公司 | 一种双管芯器件及其制作方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2896141B2 (ja) * | 1987-02-26 | 1999-05-31 | 株式会社東芝 | 高耐圧半導体素子 |
US5241210A (en) | 1987-02-26 | 1993-08-31 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device |
US5294825A (en) | 1987-02-26 | 1994-03-15 | Kabushiki Kaisha Toshiba | High breakdown voltage semiconductor device |
US5386136A (en) * | 1991-05-06 | 1995-01-31 | Siliconix Incorporated | Lightly-doped drain MOSFET with improved breakdown characteristics |
US6242787B1 (en) * | 1995-11-15 | 2001-06-05 | Denso Corporation | Semiconductor device and manufacturing method thereof |
US5877044A (en) * | 1997-03-11 | 1999-03-02 | Harris Corporation | Method of making MOS-gated semiconductor devices |
JPH11354631A (ja) | 1998-06-11 | 1999-12-24 | Nec Kansai Ltd | 半導体装置 |
JP2003249644A (ja) * | 2002-02-26 | 2003-09-05 | Nec Kansai Ltd | 横型パワーmos−fet |
JP4974474B2 (ja) * | 2004-06-22 | 2012-07-11 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US7466006B2 (en) | 2005-05-19 | 2008-12-16 | Freescale Semiconductor, Inc. | Structure and method for RESURF diodes with a current diverter |
US7936023B1 (en) | 2006-09-26 | 2011-05-03 | Cypress Semiconductor Corporation | High voltage diode |
US7842968B2 (en) * | 2008-01-09 | 2010-11-30 | Fairchild Semiconductor Corporation | Integrated low leakage diode |
JP5409247B2 (ja) | 2009-10-13 | 2014-02-05 | 三菱電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP5460279B2 (ja) | 2009-12-11 | 2014-04-02 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
JP5488256B2 (ja) * | 2010-06-25 | 2014-05-14 | 三菱電機株式会社 | 電力用半導体装置 |
-
2012
- 2012-10-19 US US13/656,122 patent/US9040384B2/en active Active
-
2013
- 2013-09-26 JP JP2013199779A patent/JP6391136B2/ja active Active
- 2013-10-10 CN CN201310470104.4A patent/CN103779429B/zh active Active
-
2015
- 2015-04-27 US US14/697,195 patent/US9466665B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20140110815A1 (en) | 2014-04-24 |
CN103779429B (zh) | 2018-06-22 |
US20150228713A1 (en) | 2015-08-13 |
CN103779429A (zh) | 2014-05-07 |
US9466665B2 (en) | 2016-10-11 |
JP2014086723A (ja) | 2014-05-12 |
US9040384B2 (en) | 2015-05-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8278710B2 (en) | Guard ring integrated LDMOS | |
US8772871B2 (en) | Partially depleted dielectric resurf LDMOS | |
CN104979344B (zh) | 用于创建具有横向集电极的高电压互补bjt的方法 | |
US10529849B2 (en) | High-voltage semiconductor device including a super-junction doped structure | |
US9496333B2 (en) | Resurf high voltage diode | |
US6924531B2 (en) | LDMOS device with isolation guard rings | |
US9209277B2 (en) | Manufacturing methods for laterally diffused metal oxide semiconductor devices | |
US20150179764A1 (en) | Semiconductor device and method for manufacturing same | |
KR100731141B1 (ko) | 반도체소자 및 그의 제조방법 | |
US10504921B2 (en) | Integrated circuit with resurf region biasing under buried insulator layers | |
JP2008004643A (ja) | 半導体装置 | |
KR101955055B1 (ko) | 전력용 반도체 소자 및 그 소자의 제조 방법 | |
KR102246570B1 (ko) | 전력 반도체 장치 | |
JP6391136B2 (ja) | 高電圧ダイオード | |
KR20070026690A (ko) | 쇼트키 소자와 형성 방법 | |
JP6381067B2 (ja) | 半導体装置および半導体装置の製造方法 | |
US10217828B1 (en) | Transistors with field plates on fully depleted silicon-on-insulator platform and method of making the same | |
KR101960077B1 (ko) | 플로팅 쉴드를 갖는 실리콘카바이드 트렌치 게이트 트랜지스터 및 그 제조 방법 | |
US20160056234A1 (en) | Deep trench isolation structures and systems and methods including the same | |
KR20110078621A (ko) | 반도체 소자 및 그 제조 방법 | |
JPWO2006082618A1 (ja) | 半導体装置およびその製造方法 | |
US9231120B2 (en) | Schottky diode with leakage current control structures | |
US7488638B2 (en) | Method for fabricating a voltage-stable PMOSFET semiconductor structure | |
JP2012195394A (ja) | 半導体装置の製造方法 | |
KR100916892B1 (ko) | 반도체 소자 및 반도체 소자의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20160921 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20171030 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20171205 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180219 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20180724 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20180820 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6391136 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |