CN110323138B - 一种ldmos器件的制造方法 - Google Patents
一种ldmos器件的制造方法 Download PDFInfo
- Publication number
- CN110323138B CN110323138B CN201910536451.XA CN201910536451A CN110323138B CN 110323138 B CN110323138 B CN 110323138B CN 201910536451 A CN201910536451 A CN 201910536451A CN 110323138 B CN110323138 B CN 110323138B
- Authority
- CN
- China
- Prior art keywords
- type
- forming
- well
- region
- trap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 43
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 32
- 239000010703 silicon Substances 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims description 22
- 238000005468 ion implantation Methods 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 4
- 239000007924 injection Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 7
- ALKWEXBKAHPJAQ-NAKRPEOUSA-N Asn-Leu-Asp-Asp Chemical compound NC(=O)C[C@H](N)C(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CC(O)=O)C(=O)N[C@@H](CC(O)=O)C(O)=O ALKWEXBKAHPJAQ-NAKRPEOUSA-N 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 23
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
Abstract
本发明提供一种LDMOS器件的制造方法,在P型衬底中形成N型埋层和P型外延层;在硅表面形成场氧区,之后形成N阱和P阱,场氧区位于N阱中表面区域;在N阱和P阱间的硅表面上形成栅极,栅极与P阱纵向部分交叠,栅极与N阱纵向间留有间隙;在间隙形成位于P型衬底表面处的N型LDD区域;在P阱和N阱的表面区域形成N型重掺杂区,并在P阱表面区域形成P型重掺杂区;在栅极和场氧区上形成接触孔,将接触孔连接于金属线。本发明不需要额外增加掩膜,利用现有工艺流程,击穿电压BV能达到20V以上;场氧区STI与多晶硅poly间留一定距离,使NLDD能自对准注入;漂移区由NW和NLDD构成;STI上打接触孔起到场板效果,简化了工艺流程,提高了产能。
Description
技术领域
本发明涉及一种半导体制造领域,特别是涉及一种LDMOS器件的制造方法。
背景技术
高压功率集成电路中常采用高压LDMOS满足耐高压、实现功率控制等方面的要求。LDMOS器件由于很容易于CMOS工艺兼容而被广泛采用。通常击穿电压BV要求小于14V的LDMOS,漂移区可以共用N阱NW;但由于N阱NW的注入剂量较浓难以耗尽,BV要求大于14V的器件需要额外增加一层掩模单独作为LDMOS的漂移区。
图1为现有技术中的一种LDMOS结构,多晶硅poly场板跨在浅沟道隔离区STI上,漂移区用单独掩膜mask定义。其中,1-NBL为n型埋层,2-P epi为P型外延层,3-STI为场氧区,4-Ndrift为N型漂移区,5-PW为P阱,6-Gate Oxide为栅氧化层,7-Poly为栅极多晶硅,8-N+为N型重掺杂区,9-P+为P型重掺杂区。该结构中由于漂移区需要单独用掩膜定义导致工艺繁琐复杂,降低了产能。
因此,需要提出一种新的方法来解决上述问题。
发明内容
鉴于以上所述现有技术的缺点,本发明的目的在于提供一种LDMOS器件的制造方法,用于解决现有技术中击穿电压要求大于14V的器件额外增加一层掩模单独作为LDMOS的漂移区导致工艺繁琐复杂的问题。
为实现上述目的及其他相关目的,本发明提供一种LDMOS器件的制造方法,该方法至少包括以下步骤:步骤一、在P型衬底中自下而上依次形成N型埋层和P型外延层;步骤二、在P型衬底的硅表面形成场氧区;步骤三、所述P型衬底上分别形成N阱和P阱,所述场氧区位于所述N阱中的表面区域;步骤四、在所述N阱和P阱之间的所述硅表面上形成栅极,所述栅极与所述P阱纵向部分交叠,所述栅极与所述N阱纵向之间留有间隙;步骤五、在所述栅极与所述N阱之间的间隙形成位于所述P型衬底表面处的N型LDD区域;步骤六、在所述P阱和N阱的表面区域形成N型重掺杂区,并且在所述P阱表面区域形成P型重掺杂区;步骤七、在所述栅极和所述场氧区上形成接触孔,将所述接触孔连接于金属线。
优选地,步骤一中在所述P型衬底中采用离子注入的方法形成N型埋层。
优选地,步骤一中所述P型外延层生长于所述P型衬底上。
优选地,步骤二中在所述P型衬底的硅表面形成场氧区的方法为:先在所述硅表面淀积氧化层,之后刻蚀该氧化层形成所述场氧区。
优选地,步骤三在所述P型衬底上分别形成N阱和P阱的方法为:采用光刻分别打开注入区域,分别注入N型杂质离子和P型杂质离子。
优选地,步骤四中在所述N阱和P阱之间的所述硅表面上形成栅极的方法为:先在所述N阱和P阱之间的所述硅表面上淀积一层栅氧化层以及位于所述栅氧化层上的多晶硅层,之后刻蚀该多晶硅层和栅氧化层,形成所述栅极。
优选地,步骤五中在所述栅极与所述N阱之间的间隙形成位于所述P型衬底表面处的N型LDD区域的方法为:采用选择性的进行常规的斜角LDD离子注入。
优选地,步骤六中形成所述N型重掺杂区的方法为:采用选择性的进行常规的源漏离子注入。
优选地,步骤六中形成所述P型重掺杂区的方法为:采用选择性的进行常规的源漏离子注入。
如上所述,本发明的LDMOS器件的制造方法,具有以下有益效果:本发明不需要额外增加掩膜,利用现有工艺流程,击穿电压BV能达到20V以上;场氧区STI与多晶硅poly间留一定距离,使NLDD能自对准注入;漂移区由NW和NLDD构成;STI上打接触孔起到场板效果,简化了工艺流程,提高了产能。
附图说明
图1显示为现有技术中的一种LDMOS结构示意图;
图2显示为本发明的LDMOS器件的制造方法流程示意图;
图3显示为执行本发明步骤一形成的结构示意图;
图4显示为执行本发明步骤二形成的结构示意图;
图5显示为执行本发明步骤三形成的结构示意图;
图6显示为执行本发明步骤四形成的结构示意图;
图7显示为执行本发明步骤五形成的结构示意图;
图8显示为执行本发明步骤六形成的结构示意图;
图9显示为执行本发明步骤七形成的结构示意图;
图10显示为本发明击穿电压提高至20V的BV图。
元件标号说明
1-NBL N型埋层
2-P epi P型外延层
3-STI 场氧区
4A-NW N阱
4B-NLDD N型LDD区域
5-PW P阱
6-Gate Oxide 栅氧化层
7-Poly 栅极多晶硅
8-N+ N型重掺杂区
9-P+ P型重掺杂区
10-Contact 接触孔
11-Metal 金属线
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
请参阅图2至图9。需要说明的是,本实施例中所提供的图示仅以示意方式说明本发明的基本构想,遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制,其实际实施时各组件的型态、数量及比例可为一种随意的改变,且其组件布局型态也可能更为复杂。
如图2所示,图2显示为本发明的LDMOS器件的制造方法流程示意图。本发明提供一种LDMOS器件的制造方法,该方法包括以下步骤:
步骤一、在P型衬底中自下而上依次形成N型埋层和P型外延层;本实施例的步骤一中在所述P型衬底中采用离子注入的方法形成N型埋层。并且本实施例的步骤一中所述P型外延层生长于所述P型衬底上。如图3所示,图3显示为执行本发明步骤一形成的结构示意图;先在所述P型衬底中形成N型埋层(1-NBL),在所述N型埋层上方形成所述P型外延层(2-Pepi),所述N型埋层(1-NBL)采用离子注入的方法形成,所述P型外延层(2-P epi)采用离子注入的方法形成。
步骤二、在P型衬底的硅表面形成场氧区;本实施例的步骤二中在所述P型衬底的硅表面形成场氧区的方法为:先在所述硅表面淀积氧化层,之后刻蚀该氧化层形成所述场氧区。如图4所示,图4显示为执行本发明步骤二形成的结构示意图;该步骤中,先在P型衬底的硅表面淀积一层氧化层,之后利用光刻和刻蚀的步骤刻蚀所述氧化层,形成如图4所示的场氧区(3-STI)结构,该3-STI结构用于隔离有源区。
步骤三、所述P型衬底上分别形成N阱和P阱,所述场氧区位于所述N阱中的表面区域;本实施例的步骤三在所述P型衬底上分别形成N阱和P阱的方法为:采用光刻分别打开注入区域,分别注入N型杂质离子和P型杂质离子。如图5所示,图5显示为执行本发明步骤三形成的结构示意图;该步骤中,利用光刻工艺定义出P行衬底上的N阱(4A-NW)和P阱(5-PW)的区域,之后在所定义出的N阱(4A-NW)和P阱(5-PW)的区域分别N型杂质离子和P型杂质离子,注入N型杂质离子的区域形成所述N阱,注入P型杂质离子的区域形成所述P阱。
步骤四、在所述N阱和P阱之间的所述硅表面上形成栅极,所述栅极与所述P阱(5-PW)纵向部分交叠,所述栅极与所述N阱(4A-NW)纵向之间留有间隙;本实施例的步骤四中在所述N阱(4A-NW)和P阱(5-PW)之间的所述硅表面上形成栅极的方法为:先在所述N阱(4A-NW)和P阱(5-PW)之间的所述硅表面上淀积一层栅氧化层以及位于所述栅氧化层上的多晶硅层,之后刻蚀该多晶硅层和栅氧化层,形成所述栅极。如图6所示,图6显示为执行本发明步骤四形成的结构示意图;也就是说,先在所述硅表面上淀积栅氧化层,之后再淀积一层多晶硅层,采用光刻工艺定义出栅极的形状,利用刻蚀工艺对所述多晶硅层和所述栅氧化层一起刻蚀,形成如图6所示的栅极结构。其中6-Gate Oxide为刻蚀后形成的栅极中的栅氧化层,7-Poly为刻蚀后形成的栅极中的栅极多晶硅。
步骤五、在所述栅极与所述N阱之间的间隙形成位于所述P型衬底表面处的N型LDD区域;本实施例的步骤五中在所述栅极与所述N阱之间的间隙形成位于所述P型衬底表面处的N型LDD区域的方法为:采用选择性的进行常规的斜角LDD离子注入。
如图7所示,图7显示为执行本发明步骤五形成的结构示意图;由于所述栅极的一部分位于所述P阱的上方,并且所述P阱的一部分位于所述栅极的下方,也就是说,所述栅极与所述P阱在纵向上呈现一定区域的交叠,如图7所示,而所述栅极与所述N阱之间在纵向上并没有形成交叠,并且,所述栅极与所述N阱在纵向具有一定距离的间隔,亦即间隙,因此,在所述栅极与所述N阱之间间隙的硅表面区域形成了所述N型LDD区域(4B-NLDD)。因此,由所述N阱(4A-NW)和所述N型LDD区域(4B-NLDD)共同构成了该LDMOS器件的漂移区。
步骤六、在所述P阱和N阱的表面区域形成N型重掺杂区,并且在所述P阱表面区域形成P型重掺杂区;如图8所示,图8显示为执行本发明步骤六形成的结构示意图;该步骤中,在所述P阱(5-PW)中掺杂N型离子和P型离子,在所述N阱(4A-NW)中只掺杂N型离子,形成如图8所示的结构,在所述P阱(5-PW)中形成的N型重掺杂区(8-N+)位于所述P型重掺杂区(9-P+)与所述栅极之间,在所述N阱中形成的所述N型重掺杂区(8-N+)位于所述场氧区远离所述栅极一侧。
步骤七、在所述栅极和所述场氧区上形成接触孔,将所述接触孔连接于金属线。如图9所示,图9显示为执行本发明步骤七形成的结构示意图;所述接触孔10-Contact中填充有金属,用于将所述栅极、所述场氧区连接至所述金属线(11-Metal)。
本发明还提供另一实施例
如图2所示,图2显示为本发明的LDMOS器件的制造方法流程示意图。本发明提供一种LDMOS器件的制造方法,该方法包括以下步骤:
步骤一、在P型衬底中自下而上依次形成N型埋层和P型外延层;本实施例的步骤一中在所述P型衬底中采用离子注入的方法形成N型埋层。并且本实施例的步骤一中所述P型外延层生长于所述P型衬底上。如图3所示,图3显示为执行本发明步骤一形成的结构示意图;先在所述P型衬底中形成N型埋层(1-NBL),在所述N型埋层上方形成所述P型外延层(2-Pepi),所述N型埋层(1-NBL)采用离子注入的方法形成,所述P型外延层(2-P epi)采用离子注入的方法形成。
步骤二、在P型衬底的硅表面形成场氧区;本实施例的步骤二中在所述P型衬底的硅表面形成场氧区的方法为:先在所述硅表面淀积氧化层,之后刻蚀该氧化层形成所述场氧区。如图4所示,图4显示为执行本发明步骤二形成的结构示意图;该步骤中,先在P型衬底的硅表面淀积一层氧化层,之后利用光刻和刻蚀的步骤刻蚀所述氧化层,形成如图4所示的场氧区(3-STI)结构,该3-STI结构用于隔离有源区。
步骤三、所述P型衬底上分别形成N阱和P阱,所述场氧区位于所述N阱中的表面区域;本实施例的步骤三在所述P型衬底上分别形成N阱和P阱的方法为:采用光刻分别打开注入区域,分别注入N型杂质离子和P型杂质离子。如图5所示,图5显示为执行本发明步骤三形成的结构示意图;该步骤中,利用光刻工艺定义出P行衬底上的N阱(4A-NW)和P阱(5-PW)的区域,之后在所定义出的N阱(4A-NW)和P阱(5-PW)的区域分别N型杂质离子和P型杂质离子,注入N型杂质离子的区域形成所述N阱,注入P型杂质离子的区域形成所述P阱。
步骤四、在所述N阱和P阱之间的所述硅表面上形成栅极,所述栅极与所述P阱(5-PW)纵向部分交叠,所述栅极与所述N阱(4A-NW)纵向之间留有间隙;本实施例的步骤四中在所述N阱(4A-NW)和P阱(5-PW)之间的所述硅表面上形成栅极的方法为:先在所述N阱(4A-NW)和P阱(5-PW)之间的所述硅表面上淀积一层栅氧化层以及位于所述栅氧化层上的多晶硅层,之后刻蚀该多晶硅层和栅氧化层,形成所述栅极。如图6所示,图6显示为执行本发明步骤四形成的结构示意图;也就是说,先在所述硅表面上淀积栅氧化层,之后再淀积一层多晶硅层,采用光刻工艺定义出栅极的形状,利用刻蚀工艺对所述多晶硅层和所述栅氧化层一起刻蚀,形成如图6所示的栅极结构。其中6-Gate Oxide为刻蚀后形成的栅极中的栅氧化层,7-Poly为刻蚀后形成的栅极中的栅极多晶硅。
步骤五、在所述栅极与所述N阱之间的间隙形成位于所述P型衬底表面处的N型LDD区域;本实施例的步骤五中在所述栅极与所述N阱之间的间隙形成位于所述P型衬底表面处的N型LDD区域的方法为:采用选择性的进行常规的斜角LDD离子注入。
如图7所示,图7显示为执行本发明步骤五形成的结构示意图;由于所述栅极的一部分位于所述P阱的上方,并且所述P阱的一部分位于所述栅极的下方,也就是说,所述栅极与所述P阱在纵向上呈现一定区域的交叠,如图7所示,而所述栅极与所述N阱之间在纵向上并没有形成交叠,并且,所述栅极与所述N阱在纵向具有一定距离的间隔,亦即间隙,因此,在所述栅极与所述N阱之间间隙的硅表面区域形成了所述N型LDD区域(4B-NLDD)。因此,由所述N阱(4A-NW)和所述N型LDD区域(4B-NLDD)共同构成了该LDMOS器件的漂移区。
步骤六、在所述P阱和N阱的表面区域形成N型重掺杂区,并且在所述P阱表面区域形成P型重掺杂区;如图8所示,图8显示为执行本发明步骤六形成的结构示意图;该步骤中,在所述P阱(5-PW)中掺杂N型离子和P型离子,在所述N阱(4A-NW)中只掺杂N型离子,形成如图8所示的结构,在所述P阱(5-PW)中形成的N型重掺杂区(8-N+)位于所述P型重掺杂区(9-P+)与所述栅极之间,在所述N阱中形成的所述N型重掺杂区(8-N+)位于所述场氧区远离所述栅极一侧。
本实施例的步骤六中形成所述N型重掺杂区的方法为:采用选择性的进行常规的源漏离子注入。
步骤七、在所述栅极和所述场氧区上形成接触孔,将所述接触孔连接于金属线。如图9所示,图9显示为执行本发明步骤七形成的结构示意图;所述接触孔10-Contact中填充有金属,用于将所述栅极、所述场氧区连接至所述金属线(11-Metal)。
本实施例的步骤七中形成所述N型重掺杂区的方法为:采用选择性的进行常规的源漏离子注入。如图10所示,图10显示为本发明击穿电压提高至20V的BV图。
综上所述,本发明不需要额外增加掩膜,利用现有工艺流程,击穿电压BV能达到20V以上;场氧区STI与多晶硅poly间留一定距离,使NLDD能自对准注入;漂移区由NW和NLDD构成;STI上打接触孔起到场板效果,简化了工艺流程,提高了产能。所以,本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。
Claims (8)
1.一种LDMOS器件的制造方法,其特征在于,该方法至少包括以下步骤:
步骤一、在P型衬底中自下而上依次形成N型埋层和P型外延层;
步骤二、在P型衬底的硅表面形成场氧区;
步骤三、所述P型衬底上分别形成N阱和P阱,所述场氧区位于所述N阱中的表面区域;
步骤四、在所述N阱和P阱之间的所述硅表面上形成栅极,所述栅极与所述P阱纵向部分交叠,所述栅极与所述N阱纵向之间留有间隙;
步骤五、采用选择性的常规斜角LDD离子注入在所述栅极与所述N阱之间的间隙形成位于所述P型衬底表面处的N型LDD区域;
步骤六、在所述P阱和N阱的表面区域形成N型重掺杂区,并且在所述P阱表面区域形成P型重掺杂区;
步骤七、在所述栅极和所述场氧区上形成接触孔,将所述接触孔连接于金属线。
2.根据权利要求1所述的LDMOS器件的制造方法,其特征在于:步骤一中在所述P型衬底中采用离子注入的方法形成N型埋层。
3.根据权利要求1所述的LDMOS器件的制造方法,其特征在于:步骤一中所述P型外延层生长于所述P型衬底上。
4.根据权利要求1所述的LDMOS器件的制造方法,其特征在于:步骤二中在所述P型衬底的硅表面形成场氧区的方法为:先在所述硅表面淀积氧化层,之后刻蚀该氧化层形成所述场氧区。
5.根据权利要求1所述的LDMOS器件的制造方法,其特征在于:步骤三在所述P型衬底上分别形成N阱和P阱的方法为:采用光刻分别打开注入区域,分别注入N型杂质离子和P型杂质离子。
6.根据权利要求1所述的LDMOS器件的制造方法,其特征在于:步骤四中在所述N阱和P阱之间的所述硅表面上形成栅极的方法为:先在所述N阱和P阱之间的所述硅表面上淀积一层栅氧化层以及位于所述栅氧化层上的多晶硅层,之后刻蚀该多晶硅层和栅氧化层,形成所述栅极。
7.根据权利要求1所述的LDMOS器件的制造方法,其特征在于:步骤六中形成所述N型重掺杂区的方法为:采用选择性的进行常规的源漏离子注入。
8.根据权利要求1所述的LDMOS器件的制造方法,其特征在于:步骤六中形成所述P型重掺杂区的方法为:采用选择性的进行常规的源漏离子注入。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910536451.XA CN110323138B (zh) | 2019-06-20 | 2019-06-20 | 一种ldmos器件的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910536451.XA CN110323138B (zh) | 2019-06-20 | 2019-06-20 | 一种ldmos器件的制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110323138A CN110323138A (zh) | 2019-10-11 |
CN110323138B true CN110323138B (zh) | 2021-04-06 |
Family
ID=68119918
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910536451.XA Active CN110323138B (zh) | 2019-06-20 | 2019-06-20 | 一种ldmos器件的制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN110323138B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111223917A (zh) * | 2020-01-17 | 2020-06-02 | 和舰芯片制造(苏州)股份有限公司 | 用于ldmos的屏蔽接触结构及其制备方法 |
DE102022102333A1 (de) | 2022-02-01 | 2023-08-03 | Infineon Technologies Ag | Feldeffekttransistor mit dielektrikumsstruktur |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102569381A (zh) * | 2010-12-07 | 2012-07-11 | 上海华虹Nec电子有限公司 | 具有屏蔽栅的ldmos结构及其制备方法 |
CN106571393A (zh) * | 2015-10-07 | 2017-04-19 | 爱思开海力士有限公司 | 具有沟槽绝缘场板和金属场板的横向高压集成器件 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100611111B1 (ko) * | 2004-07-15 | 2006-08-10 | 삼성전자주식회사 | 고주파용 모오스 트랜지스터, 이의 형성 방법 및 반도체장치의 제조 방법 |
-
2019
- 2019-06-20 CN CN201910536451.XA patent/CN110323138B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102569381A (zh) * | 2010-12-07 | 2012-07-11 | 上海华虹Nec电子有限公司 | 具有屏蔽栅的ldmos结构及其制备方法 |
CN106571393A (zh) * | 2015-10-07 | 2017-04-19 | 爱思开海力士有限公司 | 具有沟槽绝缘场板和金属场板的横向高压集成器件 |
Also Published As
Publication number | Publication date |
---|---|
CN110323138A (zh) | 2019-10-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6713453B2 (ja) | カスケードされたリサーフ注入及び二重バッファを備えるldmosデバイスのための方法及び装置 | |
US10529849B2 (en) | High-voltage semiconductor device including a super-junction doped structure | |
US7125777B2 (en) | Asymmetric hetero-doped high-voltage MOSFET (AH2MOS) | |
US10468402B1 (en) | Trench diode and method of forming the same | |
US7981783B2 (en) | Semiconductor device and method for fabricating the same | |
US8399921B2 (en) | Metal oxide semiconductor (MOS) structure and manufacturing method thereof | |
US6677210B1 (en) | High voltage transistors with graded extension | |
JP2019521529A (ja) | パワーデバイス及びその製造方法 | |
CN110323138B (zh) | 一种ldmos器件的制造方法 | |
US20070152245A1 (en) | Semiconductor device and method for manufacturing the same | |
CN107452789B (zh) | 用于器件制造的改进布局 | |
KR102648999B1 (ko) | Ldmos 반도체 소자 및 제조방법 | |
US10629734B2 (en) | Fabricating method of fin structure with tensile stress and complementary FinFET structure | |
US7247532B2 (en) | High voltage transistor and method for fabricating the same | |
CN103681850B (zh) | 功率mosfet及其形成方法 | |
KR20110078621A (ko) | 반도체 소자 및 그 제조 방법 | |
JP5543253B2 (ja) | 半導体装置及びその製造方法 | |
US9087708B2 (en) | IC with floating buried layer ring for isolation of embedded islands | |
CN111223931A (zh) | 沟槽mosfet及其制造方法 | |
CN113611733A (zh) | 隔离型nldmos器件及其制造方法 | |
KR20110079021A (ko) | 반도체 소자 및 그의 제조방법 | |
CN103715129A (zh) | 注入隔离器件及其形成方法 | |
CN111987164B (zh) | Ldmos器件及其制造方法 | |
KR20110037031A (ko) | 반도체 소자 및 그 제조 방법 | |
KR20230144201A (ko) | 아이솔레이션 항복 전압 향상을 위한 반도체 소자 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |