JP6713453B2 - カスケードされたリサーフ注入及び二重バッファを備えるldmosデバイスのための方法及び装置 - Google Patents
カスケードされたリサーフ注入及び二重バッファを備えるldmosデバイスのための方法及び装置 Download PDFInfo
- Publication number
- JP6713453B2 JP6713453B2 JP2017506834A JP2017506834A JP6713453B2 JP 6713453 B2 JP6713453 B2 JP 6713453B2 JP 2017506834 A JP2017506834 A JP 2017506834A JP 2017506834 A JP2017506834 A JP 2017506834A JP 6713453 B2 JP6713453 B2 JP 6713453B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- diffusion
- well
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 86
- 239000000872 buffer Substances 0.000 title claims description 40
- 238000002347 injection Methods 0.000 title description 6
- 239000007924 injection Substances 0.000 title description 6
- 239000007943 implant Substances 0.000 claims description 90
- 238000009792 diffusion process Methods 0.000 claims description 80
- 239000000758 substrate Substances 0.000 claims description 78
- 239000004065 semiconductor Substances 0.000 claims description 69
- 238000002955 isolation Methods 0.000 claims description 45
- 238000005468 ion implantation Methods 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 29
- 239000004020 conductor Substances 0.000 claims description 11
- 238000002513 implantation Methods 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 description 25
- 239000002019 doping agent Substances 0.000 description 16
- 238000013459 approach Methods 0.000 description 14
- 229910052796 boron Inorganic materials 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 8
- 210000000746 body region Anatomy 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 7
- 239000003989 dielectric material Substances 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 108091006149 Electron carriers Proteins 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005755 formation reaction Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- -1 pattern Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0856—Source regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
Claims (19)
- LDMOSデバイスであって、
少なくとも1つのドリフト領域であって、半導体基板の一部に配置され、第1の導電型にドープされる、前記少なくとも1つのドリフト領域と、
前記半導体基板の表面における少なくとも1つの隔離構造であって、前記少なくとも1つのドリフト領域の一部の中に位置する、前記少なくとも1つの隔離構造と、
前記半導体基板の別の一部におけるDウェル領域であって、第2の導電型にドープされ、前記少なくとも1つのドリフト領域の一部に近接して位置し、前記ドリフト領域と前記Dウェル領域との交差部が、前記第1及び第2の導電型の間の接合を形成する、前記Dウェル領域と、
前記半導体基板の表面上に配置され、チャネル領域と前記隔離構造の一部とに重なるゲート構造であって、前記ゲート構造が、前記チャネル領域の上にあるゲート誘電体層と、前記ゲート誘電体層に重なるゲート導体材料とを含む、前記ゲート構造と、
前記Dウェル領域の前記表面上において、前記チャネル領域の1つの側部に近接して配置されるソースコンタクト領域であって、前記第1の導電型にドープされる、前記ソースコンタクト領域と、
ドレインコンタクト領域であって、前記ドレインコンタクト領域が、前記ドリフト領域の前記表面上の拡散ウェルにおいて、前記隔離構造に近接し、前記チャネル領域から前記隔離構造によって離間されて配置され、前記ドレインコンタクト領域と前記拡散ウェルとが前記第1の導電型にドープされる、前記ドレインコンタクト領域と、
二重バッファ領域であって、前記Dウェル領域と前記ドリフト領域との下にあり、前記第2の導電型にドープされる第1の埋め込み層と、前記第1の埋め込み層の下にあり、前記第1の導電型にドープされる高電圧拡散層とを含む、前記二重バッファ領域と、
ディープダウンボディ拡散を形成する前記第1の埋め込み層に近接する前記Dウェル領域における第1のp型拡散領域と、
アップボディ拡散を形成する前記ドリフト領域との前記接合に近接する前記Dウェル領域における第2のp型拡散領域と、
を含む、LDMOSデバイス。 - 請求項1に記載のLDMOSデバイスであって、
前記第1の導電型がn型であり、前記第2の導電型がp型である、LDMOSデバイス。 - 請求項1に記載のLDMOSデバイスであって、
前記ドリフト領域における第1のn型リサーフ拡散領域と、前記ドリフト領域における第2のn型JFEリサーフ拡散領域とを更に含み、前記第2のn型JFEリサーフ拡散領域が、前記Dウェル領域との前記接合に近接し、前記第1のn型リサーフ拡散領域より上にある、LDMOSデバイス。 - 請求項3に記載のLDMOSデバイスであって、
前記チャネル領域の近くの第3のn型拡散を更に含む、LDMOSデバイス。 - 請求項1に記載のLDMOSデバイスであって、
前記ソースコンタクト領域とチャネル領域とにおいて第3のp型拡散領域を更に含む、LDMOSデバイス。 - 請求項1に記載のLDMOSデバイスであって、
前記半導体基板が前記第2の導電型のエピタキシャル層を更に含む、LDMOSデバイス。 - 請求項6に記載のLDMOSデバイスであって、
前記高電圧拡散層の下にあり、前記第1の導電型のインプラント領域として、前記半導体基板の前記エピタキシャル層において形成される、第2の埋め込み層を更に含む、LDMOSデバイス。 - 請求項7に記載のLDMOSデバイスであって、
前記Dウェル領域から離間され、前記半導体基板の前記表面から、前記第1の埋め込み層と前記高電圧拡散層と前記エピタキシャル層とを介して延在し、前記半導体基板に接する、隔離構造を更に含む、LDMOSデバイス。 - 請求項7に記載のLDMOSデバイスであって、
前記Dウェル領域から離間され、前記半導体基板の前記表面から、前記第1の埋め込み層と前記高電圧拡散層とを介して前記第2の埋め込み層内へ延在する、トレンチ隔離構造を更に含む、LDMOSデバイス。 - 請求項9に記載のLDMOSデバイスであって、
前記トレンチ隔離構造が、前記第2の埋め込み層と物理的に接する前記第1の導電型の材料を含む、LDMOSデバイス。 - LDMOSデバイスを形成するための方法であって、
第1の導電型を有する半導体基板を提供することと、
前記半導体基板の上に前記第1の導電型を有するエピタキシャル層を形成することと、
前記半導体基板の上の前記エピタキシャル層に不純物を注入することによって第2の導電型の第1の埋め込み層を形成することと、
前記第1の埋め込み層の上に前記第1の導電型のインラインエピタキシャル層を形成することと、
高電圧ディープウェルバッファ領域を形成するために、第1のチェーン注入において前記第2の導電型の第1のイオン注入を行うことと、
第2の埋め込み層を形成するために、前記第1の導電型のイオン注入を行うことであって、前記第2の埋め込み層が前記高電圧ディープウェルバッファ領域とドリフト領域との間に配置され、前記高電圧ディープウェルバッファ領域と前記第2の埋め込み層とが二重バッファ領域を形成する、前記第1の導電型のイオン注入を行うことと、
前記第1の導電型の前記ドリフト領域において、前記半導体基板の表面における隔離領域を形成することと、
前記半導体基板の上にゲート誘電体を堆積し、前記ゲート誘電体の上にゲート導体を堆積し、その後、チャネル領域に重なるゲート構造を形成するように、前記ゲート導体と前記ゲート誘電体とをエッチングすることと、
前記チャネル領域によって前記ゲート構造から離間されたソース領域を形成し、前記ドリフト領域において、前記隔離領域によって前記ゲート構造から離間される、ドレイン領域を形成するように、不純物を注入することと、
を含む、方法。 - 請求項11に記載の方法であって、
前記第1の導電型がp型であり、前記第2の導電型がn型である、方法。 - 請求項12に記載の方法であって、
前記第1のチェーン注入が、ウェル領域においてドリフトリサーフ拡散を形成するように前記第2の導電型の第2のイオン注入を行うことと、前記ウェル領域において前記ドリフトリサーフ拡散の上に、JFEリサーフ拡散を形成するように前記第2の導電型の第3のイオン注入を行うこととを更に含む、方法。 - 請求項12に記載の方法であって、
前記隔離領域を形成した後に前記第1の導電型の第2のチェーンイオン注入を行うことを更に含み、
前記第2のチェーンイオン注入を行うことが、
第1のDウェル領域ダウン拡散を形成するように前記第1の導電型の不純物を注入することを含む、前記第2のチェーンイオン注入の第1の注入を行うことと、
前記第1のDウェル領域ダウン拡散の上に第2のDウェルアップ拡散領域を形成するように前記第1の導電型の不純物を注入することを含む、前記第2のチェーンイオン注入の第2の注入を行うことと、
によって行われる、方法。 - 請求項14に記載の方法であって、
前記チャネル領域においてシャローリサーフ拡散領域を形成するように、前記第1及び第2の両方の導電型のイオンを共注入するために付加的なチェーン注入を行うことを更に含む、方法。 - 請求項12に記載の方法であって、
前記第2の埋め込み層を形成した後に、前記半導体基板に物理的に接するように、前記半導体基板の前記表面から前記第2の埋め込み層を介して、及び前記第1の埋め込み層を介して延在するディープトレンチ隔離構造を形成することを更に含む、方法。 - 集積回路であって、
LDMOSデバイスと少なくとも1つのMOSデバイスとを含み、
前記LDMOSデバイスが、
半導体基板の一部において配置され、第1の導電型にドープされる、少なくとも1つのドリフト領域と、
前記半導体基板の表面にあり、前記少なくとも1つのドリフト領域の一部の中に位置する、少なくとも1つの隔離構造と、
前記半導体基板の別の一部にあり、第2の導電型にドープされ、前記少なくとも1つのドリフト領域の一部に近接して位置するDウェル領域であって、前記ドリフト領域と前記Dウェル領域との交差部が前記第1及び第2の導電型の間の接合を形成する、前記Dウェル領域と、
前記半導体基板の表面上に配置され、チャネル領域と前記隔離構造の一部とに重なるゲート構造であって、前記チャネル領域の上にあるゲート誘電体層と、前記ゲート誘電体層に重なるゲート導体材料とを含む、前記ゲート構造と、
前記Dウェル領域の前記表面上において、前記チャネル領域の1つの側部に近接して配置されるソースコンタクト領域であって、前記第1の導電型にドープされる、前記ソースコンタクト領域と、
ドレインコンタクト領域であって、前記ドリフト領域の前記表面上のシャロー拡散ウェルにおいて、前記隔離構造に近接して配置され、前記隔離構造によって前記チャネル領域から離間され、前記ドレインコンタクト領域と前記シャロー拡散ウェルとが前記第1の導電型にドープされ、前記シャロー拡散ウェルが前記ドリフト領域よりも浅い、前記ドレインコンタクト領域と、
二重バッファ領域であって、前記Dウェル領域と前記ドリフト領域との下にあって前記第2の導電型にドープされる第1の埋め込み層と、前記第1の埋め込み層の下にあって前記第1の導電型にドープされる第2の高電圧ディープ拡散層とを含む、前記二重バッファ領域と、
を含み、
前記少なくとも1つのMOSデバイスが、前記半導体基板において、前記LDMOSデバイスから離間されて形成される、集積回路。 - 請求項17に記載の集積回路であって、
前記少なくとも1つのMOSデバイスがPMOSトランジスタを含む、集積回路。 - 請求項17に記載の集積回路であって、
前記第1の導電型がn型であり、前記第2の導電型がp型である、集積回路。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201462034378P | 2014-08-07 | 2014-08-07 | |
US62/034,378 | 2014-08-07 | ||
US14/808,991 US9660074B2 (en) | 2014-08-07 | 2015-07-24 | Methods and apparatus for LDMOS devices with cascaded RESURF implants and double buffers |
US14/808,991 | 2015-07-24 | ||
PCT/US2015/044317 WO2016022975A1 (en) | 2014-08-07 | 2015-08-07 | Methods and apparatus for ldmos devices with cascaded resurf implants and double buffers |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2017527110A JP2017527110A (ja) | 2017-09-14 |
JP2017527110A5 JP2017527110A5 (ja) | 2018-09-13 |
JP6713453B2 true JP6713453B2 (ja) | 2020-06-24 |
Family
ID=55264668
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017506834A Active JP6713453B2 (ja) | 2014-08-07 | 2015-08-07 | カスケードされたリサーフ注入及び二重バッファを備えるldmosデバイスのための方法及び装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9660074B2 (ja) |
EP (1) | EP3178116A4 (ja) |
JP (1) | JP6713453B2 (ja) |
CN (1) | CN106663699B (ja) |
WO (1) | WO2016022975A1 (ja) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9437470B2 (en) | 2013-10-08 | 2016-09-06 | Cypress Semiconductor Corporation | Self-aligned trench isolation in integrated circuits |
CN105575812B (zh) * | 2014-10-16 | 2018-12-21 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件及其制造方法和电子装置 |
US10217860B2 (en) * | 2015-09-11 | 2019-02-26 | Nxp Usa, Inc. | Partially biased isolation in semiconductor devices |
US10297676B2 (en) | 2015-09-11 | 2019-05-21 | Nxp Usa, Inc. | Partially biased isolation in semiconductor device |
US9728600B2 (en) | 2015-09-11 | 2017-08-08 | Nxp Usa, Inc. | Partially biased isolation in semiconductor devices |
JP6476317B2 (ja) * | 2015-12-01 | 2019-02-27 | シャープ株式会社 | アバランシェフォトダイオード |
CN107564816B (zh) * | 2016-06-30 | 2020-05-08 | 中芯国际集成电路制造(上海)有限公司 | Ldmos晶体管及其形成方法 |
KR102513081B1 (ko) | 2016-07-08 | 2023-03-24 | 삼성전자주식회사 | 반도체 장치 |
US10347656B2 (en) * | 2016-07-18 | 2019-07-09 | Semiconductor Components Industries, Llc | Semiconductor device and monolithic semiconductor device including a power semiconductor device and a control circuit |
US9786665B1 (en) * | 2016-08-16 | 2017-10-10 | Texas Instruments Incorporated | Dual deep trenches for high voltage isolation |
US9761707B1 (en) | 2016-08-19 | 2017-09-12 | Nxp Usa, Inc. | Laterally diffused MOSFET with isolation region |
US10243047B2 (en) * | 2016-12-08 | 2019-03-26 | Globalfoundries Inc. | Active and passive components with deep trench isolation structures |
US9842896B1 (en) * | 2017-02-17 | 2017-12-12 | Vanguard International Semiconductor Corporation | Ultra-high voltage devices and method for fabricating the same |
US9929283B1 (en) | 2017-03-06 | 2018-03-27 | Vanguard International Semiconductor Corporation | Junction field effect transistor (JFET) with first and second top layer of opposite conductivity type for high driving current and low pinch-off voltage |
TWI624058B (zh) * | 2017-04-26 | 2018-05-11 | 世界先進積體電路股份有限公司 | 半導體裝置及其製造方法 |
TWI614891B (zh) * | 2017-07-03 | 2018-02-11 | 世界先進積體電路股份有限公司 | 高壓半導體裝置 |
US10529804B2 (en) * | 2017-08-21 | 2020-01-07 | Texas Instruments Incorporated | Integrated circuit, LDMOS with trapezoid JFET, bottom gate and ballast drift and fabrication method |
US10262997B2 (en) * | 2017-09-14 | 2019-04-16 | Vanguard International Semiconductor Corporation | High-voltage LDMOSFET devices having polysilicon trench-type guard rings |
US10424647B2 (en) * | 2017-10-19 | 2019-09-24 | Texas Instruments Incorporated | Transistors having gates with a lift-up region |
US10580890B2 (en) | 2017-12-04 | 2020-03-03 | Texas Instruments Incorporated | Drain extended NMOS transistor |
TWI673869B (zh) | 2018-07-31 | 2019-10-01 | 新唐科技股份有限公司 | 高壓半導體裝置及其製造方法 |
US11121224B2 (en) | 2019-02-08 | 2021-09-14 | Texas Instruments Incorporated | Transistor with field plate over tapered trench isolation |
JP7299769B2 (ja) * | 2019-06-24 | 2023-06-28 | ローム株式会社 | 半導体装置 |
US11049957B1 (en) * | 2020-04-16 | 2021-06-29 | Monolithic Power Systems, Inc. | LDMOS device with sinker link |
CN111584366B (zh) * | 2020-05-13 | 2023-08-18 | 上海华虹宏力半导体制造有限公司 | 半导体器件的制造方法及半导体器件结构 |
CN113964035B (zh) * | 2020-07-20 | 2023-05-02 | 无锡华润上华科技有限公司 | 一种半导体器件的制造方法、半导体器件 |
CN114464663B (zh) * | 2020-11-09 | 2023-12-26 | 苏州华太电子技术股份有限公司 | 应用于射频放大的多层阱区ldmos器件及其制法 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0562271B1 (en) | 1992-03-26 | 1998-01-14 | Texas Instruments Incorporated | High voltage structure with oxide isolated source and resurf drift region in bulk silicon |
US5640034A (en) | 1992-05-18 | 1997-06-17 | Texas Instruments Incorporated | Top-drain trench based resurf DMOS transistor structure |
EP0610599A1 (en) | 1993-01-04 | 1994-08-17 | Texas Instruments Incorporated | High voltage transistor with drift region |
US6531355B2 (en) | 1999-01-25 | 2003-03-11 | Texas Instruments Incorporated | LDMOS device with self-aligned RESURF region and method of fabrication |
US6509220B2 (en) * | 2000-11-27 | 2003-01-21 | Power Integrations, Inc. | Method of fabricating a high-voltage transistor |
JP2002237591A (ja) * | 2000-12-31 | 2002-08-23 | Texas Instruments Inc | Dmosトランジスタ・ソース構造とその製法 |
US20080197408A1 (en) * | 2002-08-14 | 2008-08-21 | Advanced Analogic Technologies, Inc. | Isolated quasi-vertical DMOS transistor |
US6900101B2 (en) | 2003-06-13 | 2005-05-31 | Texas Instruments Incorporated | LDMOS transistors and methods for making the same |
US7230302B2 (en) * | 2004-01-29 | 2007-06-12 | Enpirion, Inc. | Laterally diffused metal oxide semiconductor device and method of forming the same |
US20080164537A1 (en) * | 2007-01-04 | 2008-07-10 | Jun Cai | Integrated complementary low voltage rf-ldmos |
JP4907920B2 (ja) * | 2005-08-18 | 2012-04-04 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7785974B2 (en) | 2006-06-26 | 2010-08-31 | Texas Instruments Incorporated | Methods of employing a thin oxide mask for high dose implants |
DE102006038874B4 (de) * | 2006-08-18 | 2011-02-10 | Infineon Technologies Austria Ag | Halbleitervorrichtung mit gemeinsamen Bezugspotential über Deep-Trench-Isolation und Messanordnung |
JP2008140817A (ja) * | 2006-11-30 | 2008-06-19 | Toshiba Corp | 半導体装置 |
JP2009059949A (ja) * | 2007-08-31 | 2009-03-19 | Sharp Corp | 半導体装置、および、半導体装置の製造方法 |
US7960222B1 (en) * | 2007-11-21 | 2011-06-14 | National Semiconductor Corporation | System and method for manufacturing double EPI N-type lateral diffusion metal oxide semiconductor transistors |
US9484454B2 (en) * | 2008-10-29 | 2016-11-01 | Tower Semiconductor Ltd. | Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate “bump” structure |
US8399924B2 (en) | 2010-06-17 | 2013-03-19 | Texas Instruments Incorporated | High voltage transistor using diluted drain |
CN201732791U (zh) * | 2010-08-12 | 2011-02-02 | 四川和芯微电子股份有限公司 | 横向扩散金属氧化物半导体结构 |
CN102376762B (zh) * | 2010-08-26 | 2013-09-11 | 上海华虹Nec电子有限公司 | 超级结ldmos器件及制造方法 |
US9059306B2 (en) * | 2011-10-11 | 2015-06-16 | Maxim Integrated Products, Inc. | Semiconductor device having DMOS integration |
JP5898473B2 (ja) * | 2011-11-28 | 2016-04-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2013247188A (ja) * | 2012-05-24 | 2013-12-09 | Toshiba Corp | 半導体装置 |
US9024380B2 (en) * | 2012-06-21 | 2015-05-05 | Freescale Semiconductor, Inc. | Semiconductor device with floating RESURF region |
KR101988425B1 (ko) * | 2012-11-05 | 2019-06-12 | 삼성전자주식회사 | 반도체 소자 및 그의 제조 방법 |
US9460926B2 (en) * | 2014-06-30 | 2016-10-04 | Alpha And Omega Semiconductor Incorporated | Forming JFET and LDMOS transistor in monolithic power integrated circuit using deep diffusion regions |
-
2015
- 2015-07-24 US US14/808,991 patent/US9660074B2/en active Active
- 2015-08-07 JP JP2017506834A patent/JP6713453B2/ja active Active
- 2015-08-07 CN CN201580042187.4A patent/CN106663699B/zh active Active
- 2015-08-07 EP EP15830577.1A patent/EP3178116A4/en not_active Ceased
- 2015-08-07 WO PCT/US2015/044317 patent/WO2016022975A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
EP3178116A1 (en) | 2017-06-14 |
WO2016022975A1 (en) | 2016-02-11 |
US9660074B2 (en) | 2017-05-23 |
JP2017527110A (ja) | 2017-09-14 |
CN106663699B (zh) | 2020-06-05 |
EP3178116A4 (en) | 2018-08-15 |
US20160043217A1 (en) | 2016-02-11 |
CN106663699A (zh) | 2017-05-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6713453B2 (ja) | カスケードされたリサーフ注入及び二重バッファを備えるldmosデバイスのための方法及び装置 | |
US8652930B2 (en) | Semiconductor device with self-biased isolation | |
US7125777B2 (en) | Asymmetric hetero-doped high-voltage MOSFET (AH2MOS) | |
TWI590457B (zh) | 半導體裝置及其製造方法 | |
US7928508B2 (en) | Disconnected DPW structures for improving on-state performance of MOS devices | |
US20150097238A1 (en) | Mergeable Semiconductor Device with Improved Reliability | |
US6677210B1 (en) | High voltage transistors with graded extension | |
US8674442B2 (en) | Semiconductor device and manufacturing method thereof | |
JP5098026B2 (ja) | 高圧nmosトランジスタの製造方法 | |
KR102068842B1 (ko) | 반도체 전력소자 | |
US10069006B2 (en) | Semiconductor device with vertical field floating rings and methods of fabrication thereof | |
US9735244B2 (en) | Quasi-vertical structure having a sidewall implantation for high voltage MOS device and method of forming the same | |
KR20110078621A (ko) | 반도체 소자 및 그 제조 방법 | |
US10312368B2 (en) | High voltage semiconductor devices and methods for their fabrication | |
KR20110079021A (ko) | 반도체 소자 및 그의 제조방법 | |
CN102694020A (zh) | 一种半导体装置 | |
CN110783334A (zh) | 具有漏极有源区域的半导体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20170207 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180801 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180801 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20190820 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20191120 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20191122 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200305 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20200310 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20200512 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20200603 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6713453 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |