JP5898473B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5898473B2 JP5898473B2 JP2011258570A JP2011258570A JP5898473B2 JP 5898473 B2 JP5898473 B2 JP 5898473B2 JP 2011258570 A JP2011258570 A JP 2011258570A JP 2011258570 A JP2011258570 A JP 2011258570A JP 5898473 B2 JP5898473 B2 JP 5898473B2
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- 239000012535 impurity Substances 0.000 claims description 49
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Description
本発明は、上記の課題に鑑みてなされたものであり、その目的は、ハイサイド素子として用いても誤動作が少なく、かつオン耐圧およびオフ耐圧の双方を高く維持することのできる半導体装置を提供することである。
(実施の形態1)
まず図1を用いて本実施の形態の半導体装置の構成について説明する。
図5を参照して、まずエピタキシャル成長により、半導体基板SUBにp-エピタキシャル領域EP1が形成される。
まず図30(A)、(B)を用いて本実施の形態の半導体装置の構成について説明する。
アナログ・デジタル混載技術においては、実施の形態1のようなLDMOSトランジスタが、CMOS(Complementary MOS)、バイポーラトランジスタ、ダイオード、メモリー素子などと同一プロセスで1チップ上に形成される場合がある。そのようなチップ上で実施の形態1のトランジスタをレイアウトする場合、そのトランジスタを他の素子と電気的に分離する必要がある。本実施の形態においては、その電気的分離のための構造について図34および図35を用いて説明する。
図36および図37を参照して、本実施の形態においては、LDMOSトランジスタのアレー配置領域ARAを他の素子と電気的に分離するためのトレンチ分離が形成されている。このトレンチ分離は、分離用溝TRSと、充填絶縁層BISとを有している。
本実施の形態では、アレー配置領域ARAを他の素子から電気的に分離するためにトレンチ分離が用いられているため、実施の形態3のn型拡散領域DNWを設けた場合のようなn型不純物の拡散によるトランジスタへの影響を考慮する必要がない。たとえば、n型拡散領域DNWがトレンチ分離の外側へ向かおうと主表面に沿う方向に広がっても、その拡散がトレンチ分離によって抑えられることにより、図36に示すようにトレンチ分離の外側にはn型拡散領域DNWが配置されない態様となる。
図38および図39を参照して、本実施の形態においては、実施の形態4のn型拡散領域DNWが、平面視における領域ARAの周囲のうち一方向(図の右側)のみに形成されており、他の点については実施の形態4と同様の構成である。
図40を参照して、上記実施の形態2〜5においてアレー配置領域ARAと電気的に分離する他の素子として、たとえば図40の左側に示すLDMOSトランジスタが考えられる。図40の左側に示すLDMOSトランジスタは図18の第3の比較例の構造を有しているが、たとえば図12の第1の比較例、図15の第2の比較例の構造であってもよい。さらに図40の左側に示すLDMOSトランジスタは一例であり、他にもダイオード、IGBT(Insulated Gate Bipolar Transistor)などが形成されてもよい。図40の右側には図3の本発明の実施の形態1の第2例の構造が示されるが、他の実施の形態の任意の構造が用いられてもよい。図40の左側に示すLDMOSトランジスタは、図40の右側に示す図3の構造のLDMOSトランジスタと同一の層として形成されている。
Claims (5)
- 主表面を有する半導体基板と、
前記半導体基板内に形成された第1導電型の第1領域と、
前記半導体基板内であって前記第1領域の前記主表面側に形成された第1導電型の第2領域と、
前記半導体基板内であって前記第2領域の前記主表面側に形成され、かつ前記第2領域との間でpn接合を構成する第2導電型の第3領域と、
前記第2領域の前記主表面側において前記第2領域と接するとともに前記第3領域と隣り合うように前記半導体基板内に形成され、かつ前記第2領域よりも高い第1導電型の不純物濃度を有する第1導電型の第4領域と、
前記第1領域と前記第2領域とを電気的に分離するように前記第1領域と前記第2領域との間の前記半導体基板内に形成された第2導電型の第5領域と、
前記第5領域と前記第2領域との間の前記半導体基板内に形成され、かつ前記第2領域よりも高い第1導電型の不純物濃度を有する第1導電型の第6領域と、
前記第3領域と接するように前記主表面に形成され、かつ前記第3領域よりも高い第2導電型の不純物濃度を有するドレイン領域と、
前記第4領域とpn接合を構成するように前記半導体基板の前記主表面に形成されたソース領域とを備え、
前記第6領域は、前記第3領域と前記第4領域との接合部の少なくとも直下に位置し、かつ前記ドレイン領域の直下を避けて配置されており、
前記ドレイン領域の真下において前記第2領域と前記第5領域とが互いに接するように配置されている、半導体装置。 - 前記主表面から前記第5領域に達するように前記半導体基板内に形成された第2導電型の第7領域をさらに備え、
前記ドレイン領域に印加される電位と同じ電位が前記第5および第7領域に印加されるように構成されており、
前記第6領域と前記第7領域との間に前記第2領域が挟まれており、前記第6領域は前記第7領域と直接接していない、請求項1に記載の半導体装置。 - 前記第2、第3および第4領域を含む横型素子が構成され、
前記第7領域は、前記横型素子の周囲を前記主表面において取り囲むように形成される、請求項2に記載の半導体装置。 - 前記半導体基板は前記主表面に分離用溝を有し、
前記分離用溝は、前記横型素子の形成領域の周囲を、前記第7領域の外側において前記第7領域と接するように前記主表面において取り囲むとともに、前記主表面から前記第5領域を少なくとも貫通するように形成されている、請求項3に記載の半導体装置。 - 前記横型素子は横型の絶縁ゲート型電界効果トランジスタである、請求項3または4に記載の半導体装置。
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US13/686,900 US8890243B2 (en) | 2011-11-28 | 2012-11-27 | Semiconductor device |
CN201210495284.7A CN103137703B (zh) | 2011-11-28 | 2012-11-28 | 半导体器件 |
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JP5898473B2 (ja) * | 2011-11-28 | 2016-04-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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CN104347420B (zh) * | 2013-08-07 | 2018-06-01 | 中芯国际集成电路制造(北京)有限公司 | Ldmos器件及其形成方法 |
CN104600111A (zh) * | 2013-10-31 | 2015-05-06 | 上海华虹宏力半导体制造有限公司 | Ldmos器件 |
CN104766885B (zh) * | 2014-01-08 | 2018-04-13 | 无锡华润上华科技有限公司 | 一种对称隔离ldmos器件及其制造方法 |
US9660074B2 (en) * | 2014-08-07 | 2017-05-23 | Texas Instruments Incorporated | Methods and apparatus for LDMOS devices with cascaded RESURF implants and double buffers |
JP6509665B2 (ja) | 2015-07-23 | 2019-05-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9911845B2 (en) * | 2015-12-10 | 2018-03-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage LDMOS transistor and methods for manufacturing the same |
JP6591312B2 (ja) * | 2016-02-25 | 2019-10-16 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN107146814B (zh) * | 2016-03-01 | 2020-09-11 | 世界先进积体电路股份有限公司 | 高压半导体装置及其制造方法 |
CN107437563B (zh) * | 2016-05-27 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Ldmos晶体管及其形成方法、以及esd器件及其形成方法 |
CN109863581B (zh) * | 2016-10-18 | 2022-04-26 | 株式会社电装 | 半导体装置及其制造方法 |
JP6677672B2 (ja) | 2017-03-24 | 2020-04-08 | 株式会社東芝 | 半導体装置 |
CN109216453B (zh) * | 2017-07-04 | 2022-02-15 | 世界先进积体电路股份有限公司 | 高压半导体装置及其制造方法 |
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JP7195167B2 (ja) * | 2019-02-08 | 2022-12-23 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
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JP5898473B2 (ja) * | 2011-11-28 | 2016-04-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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US20130134510A1 (en) | 2013-05-30 |
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CN103137703B (zh) | 2017-06-09 |
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