CN104766885B - 一种对称隔离ldmos器件及其制造方法 - Google Patents

一种对称隔离ldmos器件及其制造方法 Download PDF

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CN104766885B
CN104766885B CN201410007467.9A CN201410007467A CN104766885B CN 104766885 B CN104766885 B CN 104766885B CN 201410007467 A CN201410007467 A CN 201410007467A CN 104766885 B CN104766885 B CN 104766885B
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马栋
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CSMC Technologies Corp
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Abstract

本发明提供一种对称隔离LDMOS器件及其制造方法,LDMOS器件包括:埋层隔离层;P型阱区;侧面隔离区;栅极;源区,设置在所述栅极的一侧;漏区,与所述源区相对于所述栅极对称地设置在另一侧,源区和漏区分别包括设于所述P型阱区内的N型掺杂区,邻接所述N型掺杂区的N型漂移区,设于所述N型漂移区上的场氧化层以及与设于所述N型掺杂区之上的重掺杂N型区;其特征在于:在所述P型阱区内,在N型掺杂区与所述埋层隔离层之间,通过P型注入形成有P型注入区,所述P型注入的杂质注入面密度为1013~1014cm‑2量级。因此P型阱(P well)不会被耗尽,能有效改善LDMOS器件容易被击穿的问题。

Description

一种对称隔离LDMOS器件及其制造方法
技术领域
本发明涉及一种LDMOS器件及其制造方法,尤其是改善对称隔离LDMOS管击穿的方法,及对应的LDMOS器件。
背景技术
LDMOS(横向扩散金属氧化物半导体),与晶体管相比,在关键的器件特性方面,如增益、线性度、开关性能、散热性能以及减少级数等发面优势很明显;并且LDMOS由于更容易与CMOS工艺兼容而被广泛采用,而对称隔离LDMOS管,因为Source(源)和Drain(漏)是完全对称的,所以工作时这两端也可以互换使用,这样实际应用更加方便,所以对称隔离LDMOS管更加受到用户的青睐。
如图1所示为现有技术中的一种对称隔离LDMOS管,采用0.25μmBCD工艺平台下,隔离对称LDMOS1’包括:埋层隔离层2’(BN),设置在底部;P型阱区3’,设置于埋层隔离层2’之上;侧面隔离区4’、5’,为N型阱区,设置于P型阱区3’外侧,源区(Source)7’和漏区(Drain)8’完全对称设置在栅极6’两侧,并且源区7’和漏区8’分别包括N型掺杂区(NG)74’a和84’a,N型漂移区(N-drift)72’a和82’a,场氧化层(FOX)73’a和83’a,重掺杂N型区71’a和81’a。但是现有的制造方法存在一个问题:因为在工作时漏区8’和埋层隔离层2’,一起被施加高电压,而源区7’接地。这样埋层隔离层2’和源区7’之间形成就形成了一个很高的压差,当源区7’的N型掺杂区74’a和埋层隔离层2’之间距离很小时,它们之间的P型阱区3’很容易被耗尽,这样源区7’的N型掺杂区74’a和埋层隔离层2’容易被击穿,这样对称隔离LDMOS管就耐不了高压;并且现有技术中源区7’的N型掺杂区74’a和埋层隔离层2’之间仅可以承受10V的压差,超过10V就会穿通,而这种对称隔离LDMOS管的击穿电压(BV,breakdown voltage)要求通常在30V以上。
为了解决LDMOS管的击穿电压(BV,breakdownvoltage)不够高的技术问题,对于本领域技术人员很容易想到的技术方案是:通过增加EPI的厚度(即增加NG和BN的距离),这样虽然可以改善以上问题,但是对其他器件影响较大,而且制造成本也很高。
发明内容
为了解决上述技术问题,本发明提供一种对称隔离LDMOS管及其制造方法,能够保证对称隔离LDMOS管的击穿电压满足需求的情况下,制造工艺简单,而且成本低。本发明采用的技术方案为:
提供一种对称隔离LDMOS器件,包括:
埋层隔离层,设置在底部;
P型阱区,设置于埋层隔离层之上;
侧面隔离区,设置于所述P型阱区外侧;
栅极,设置于所述P型阱区之上;
源区,设置在所述栅极的一侧,包括设于所述P型阱区内的第一N型掺杂区,邻接所述第一N型掺杂区的第一N型漂移区,设于所述第一N型漂移区上的场氧化层以及设于所述第一N型掺杂区之上的第一重掺杂N型区;
漏区,与所述源区相对于所述栅极对称地设置在另一侧,所述漏区包括设于所述P型阱区内的第二N型掺杂区,邻接所述第二N型掺杂区的第二N型漂移区,设于所述第二N型漂移区上的场氧化层以及设于所述第二N型掺杂区之上的第二重掺杂N型区;
其特征在于:
在所述P型阱区内,在第一N型掺杂区与所述埋层隔离层之间,通过P型注入形成有P型注入区,所述P型注入的杂质注入面密度为1013~1014cm-2量级。
作为一种优选方案,上述P型注入的杂质注入能量为100Kev到500Kev。
作为一种优选方案,上述P型注入区位于所述第一N型掺杂区的正下方。
作为一种优选方案,上述P型注入区与埋层隔离层的距离较其与所述第一N型掺杂区的距离更短。
作为一种优选方案,上述P型注入的杂质为硼离子。
另一方面,本发明提供一种对称隔离LDMOS器件的制造方法,包括:
首先提供一种器件,包括埋层隔离层,设置在底部;P型阱区,设置于埋层隔离层之上;侧面隔离区,设置于所述P型阱区外侧;栅极,设置于所述P型阱区之上;源区,设置在所述栅极的一侧,包括设于所述P型阱区内的第一N型掺杂区,邻接所述第一N型掺杂区的第一N型漂移区,设于所述第一N型漂移区上的场氧化层以及设于所述第一N型掺杂区之上的第一重掺杂N型区;漏区,与所述源区相对于所述栅极对称地设置在另一侧,所述漏区包括设于所述P型阱区内的第二N型掺杂区,邻接所述第二N型掺杂区的第二N型漂移区,设于所述第二N型漂移区上的场氧化层以及设于所述第二N型掺杂区之上的第二重掺杂N型区;
然后在第一N型掺杂区与所述埋层隔离层之间,通过增加一次P型注入形成P型注入区。
作为一种优选方案,上述增加的P型注入的杂质注入面密度为1013~1014cm-2量级。
作为一种优选方案,上述P型注入的杂质注入能量为100Kev到500Kev。
作为一种优选方案,通过N型注入形成第一N型掺杂区,并从与所述N型注入相同的注入区域进行所述增加的P型注入,以使所述P型注入区位于所述第一N型掺杂区的正下方。
作为一种优选方案,上述增加的P型注入的杂质为硼离子。
附图说明
图1所示为现有技术中对称隔离LDMOS器件的截面示意图;
图2所示为本发明一实施例的对称隔离LDMOS器件的截面示意图。
具体实施方式
下面结合附图对本发明的具体实施方式做详细的说明,需要说明的是,这些具体的说明只是让本领域普通技术人员更加容易、清晰理解本发明,而非对本发明的限定性解释。
如图2所示,作为本发明一优选实施例,首先提供一种对称隔离LDMOS器件1,包括:埋层隔离层(Bury N Well)2,设置在底部;P型阱区(Pwell)3,设置于埋层隔离层2之上;侧面隔离区4、5,侧面隔离区4、5为N型阱区(N well),设置于所述P型阱区外侧;栅极(GT)6,设置于所述P型阱区之上,通常栅极包括栅电极和位于栅电极下方的栅介质层,本发明对于栅极的具体材质结构没有限制;源区(Source)7,设置在所述栅极6的一侧,包括设于所述P型阱区3内的第一N型掺杂区(NG)74a,邻接所述第一N型掺杂区74a的第一N型漂移区(N—Drift)72a、72b,设于所述第一N型漂移区72a、72b上的场氧化层(FOX)73a、73b,以及设于所述第一N型掺杂区74a之上的第一重掺杂N型区71a,所述第一重掺杂N型区71a作为引出端,引出源电极;漏区8,与所述源区7相对于所述栅极6对称地设置在另一侧,所述漏区8包括设于所述P型阱区内的第二N型掺杂区(NG)84a,邻接所述第二N型掺杂区84a的第二N型漂移区(N—Drift)82a、82b,设于所述第二N型漂移区82a、82b上的场氧化层(FOX)83a、83b以及设于所述第二N型掺杂区84a之上的第二重掺杂N型区81a,所述第二重掺杂N型区81a作为引出端,引出漏电极。其中,本发明对第一、第二N型漂移区的数量没有限制,同样地,对相应覆盖在第一、第二N型漂移区上方的场氧化层的数量也没有限制;
在该实施例中,源区及漏区的外侧还分别设有重掺杂P型区73c、83c,所述重掺杂P型区73c、83c直接与下方的P型阱区(Pwell)3连接用于作为引出端引出衬底电极;最外侧的侧面隔离区4、5中还可设有第三重掺杂N型区71b、81b,作为引出端,用于引出隔离电极。此处,引出衬底电极和引出隔离电极也可以是其他的结构形式,本发明对此没有限制。
为了满足对称隔离LDMOS管的击穿电压需求,在所述P型阱区3内,在第一N型掺杂区74a与所述埋层隔离层2之间,通过P型注入形成有P型注入区9,所述P型注入的杂质注入面密度为1013~1014cm-2量级。这样即使源区7的第一N型掺杂区74a和埋层隔离层2承受较高电压时,P型阱区3也不会被完全耗尽。本实施例中,考虑到器件的对称性,优选地,在漏区8和埋层隔离层2之间同样设置了一个通过P型注入形成的P型注入区10。
优选地,P型注入的杂质注入能量为100Kev到500Kev。
优选地,P型注入区9与埋层隔离层2的距离较其与所述第一N型掺杂区74a的距离更短。
优选地,P型注入区9位于所述第一N型掺杂区74a的正下方。
优选地,P型注入的的P型杂质为硼离子。
上述优选地方案中,P型注入的杂质注入能量较大,P型注入区9与第一N型掺杂区74a的距离更近,可进一步改善源区7的第一N型掺杂区74a和埋层隔离层2容易被击穿的可能性。进行P型注入的区域与第一N型掺杂区74a的注入区域一致,使P型注入区9位于第一N型掺杂区74a的正下方,这样从工艺上分析,不会对BCD工艺下其他器件造成影响,成本花费小。
另一方面,本实施例还提供一种对称隔离LDMOS器件的制造方法,包括:
1、在P型半导体的衬底上注入N型离子,然后高温退火,形成一个埋层隔离层(BuryN Well)2;
2、在埋层隔离层(Bury N Well)2上生长4.5μm的外延层(EPI),在外延层上注入N型杂质经高温退火形成侧面隔离区4、5,侧面隔离区4、5为N型阱区(N well);
3、在EPI上注入P型杂质经高温退火形成P型阱区(P well)3;
4、形成源区(Source)7、漏区(Drain)8:在特定位置注入N型杂质,然后再经过生长场氧化层(FOX)73a、73b、83a、83b,在场氧化层下面就形成了第一N型漂移区(N—Drift)72a、72b和第二N型漂移区(N—Drift)82a、82b,在生长场氧化层后,在特定位置注入N型杂质形成第一N型掺杂区(NG)74a、第二N型掺杂区(NG)84a;
5、在源区(Source)7、漏区(Drain)8对称中心处的P型阱区(Pwell)3上形成栅极(GT)6,然后分别在第一N型掺杂区(NG)74a、第二N型掺杂区(NG)84a、侧面隔离区4、5、P型阱区(Pwell)3中注入N+/P+作为源区(Source)7、漏区(Drain)8、侧面隔离区4、5及衬底电极的引出端,即形成第一重掺杂N型区71a、第二重掺杂N型区81a、第三重掺杂N型区71b、81b以及重掺杂P型区73c、83c。
其中,源区、漏区、栅极和各部分电极引出端的制作是本领域技术人员的常用技术,除本实施例所述方法外也可以是其他方法步骤,本发明对此没有限制。
通过上述方法就形成了一种器件,包括:埋层隔离层(Bury N Well)2,设置在底部;P型阱区(P well)3,设置于埋层隔离层2之上;侧面隔离区4、5,侧面隔离层4、5为N型阱区(N well),设置于所述P型阱区外侧;栅极(GT)6,设置于所述P型阱区之上;源区(Source)7,设置在所述栅极6的一侧,包括设于所述P型阱区3内的第一N型掺杂区(NG)74a,邻接所述第一N型掺杂区74a的第一N型漂移区(N—Drift)72a、72b,设于所述第一N型漂移区72a、72b上的场氧化层(FOX)73a、73b,以及设于所述第一N型掺杂区74a之上的第一重掺杂N型区71a;漏区8,与所述源区7相对于所述栅极6对称地设置在另一侧,所述漏区8包括设于所述P型阱区内的第二N型掺杂区(NG)84a,邻接所述第二N型掺杂区84a的第二N型漂移区(N—Drift)82a、82b,设于所述第二N型漂移区82a、82b上的场氧化层(FOX)83a、83b以及设于所述第二N型掺杂区84a之上的第二重掺杂N型区81a。
然后在所述P型阱区3内,在第一N型掺杂区74a与所述埋层隔离层2之间,通过增加一次P型注入形成P型注入区9,本实施例中,考虑到器件的对称性,优选地,同时在漏区8和埋层隔离层2之间注入形成P型注入区10。所述P型注入的杂质注入面密度为1013~1014cm-2量级。这样即使源区7的第一N型掺杂区74a和埋层隔离层2承受较高电压时,P型阱区3也不会被完全耗尽。
优选地,P型注入的杂质注入能量为100Kev到500Kev。
优选地,P型注入区9与埋层隔离层2的距离较其与所述第一N型掺杂区74a的距离更短。
优选地,P型注入区9位于所述第一N型掺杂区74a的正下方。
上述优选地方案中,P型注入的杂质注入能量较大,P型注入区9与第一N型掺杂区74a的距离更近,可进一步改善源区7的第一N型掺杂区74a和埋层隔离层2容易被击穿的可能性。进行P型注入的区域与第一N型掺杂区74a、第二N型掺杂区84a的注入区域一致,同时形成P型注入区9、10,并使P型注入区9、10分别位于第一N型掺杂区74a、第二N型掺杂区84a的正下方,这样从工艺上分析,不会对BCD工艺下其他器件造成影响,成本花费小。
最后需要说明的是,上述说明仅是本发明的最佳实施例而已,并非对本发明做任何形式上的限制。任何熟悉本领域的技术人员,在不脱离本发明技术方案范围内,都可利用上述揭示的做法和技术内容对本发明技术方案做出许多可能的变动和简单的替换等,这些都属于本发明技术方案保护的范围。

Claims (9)

1.一种对称隔离LDMOS器件,包括:
埋层隔离层,设置在底部;
P型阱区,设置于埋层隔离层之上;
侧面隔离区,设置于所述P型阱区外侧;
栅极,设置于所述P型阱区之上;
源区,设置在所述栅极的一侧,包括设于所述P型阱区内的第一N型掺杂区,邻接所述第一N型掺杂区的第一N型漂移区,设于所述第一N型漂移区上的场氧化层以及设于所述第一N型掺杂区之上的第一重掺杂N型区;
漏区,与所述源区相对于所述栅极对称地设置在另一侧,所述漏区包括设于所述P型阱区内的第二N型掺杂区,邻接所述第二N型掺杂区的第二N型漂移区,设于所述第二N型漂移区上的场氧化层以及设于所述第二N型掺杂区之上的第二重掺杂N型区;
其特征在于:
在所述P型阱区内,在第一N型掺杂区与所述埋层隔离层之间,通过P型注入形成有P型注入区,所述P型注入的杂质注入面密度为1013~1014cm-2量级,所述P型注入区与埋层隔离层的距离较其与所述第一N型掺杂区和第二N型掺杂区的距离更短。
2.如权利要求1所述的对称隔离LDMOS器件,其特征在于,所述P型注入的杂质注入能量为100Kev到500Kev。
3.如权利要求1或2所述的对称隔离LDMOS器件,其特征在于,所述P型注入区位于所述第一N型掺杂区的正下方。
4.如权利要求3所述的对称隔离LDMOS器件,其特征在于,所述P型注入的杂质为硼离子。
5.一种对称隔离LDMOS器件的制造方法,包括:
首先提供一种器件,包括埋层隔离层,设置在底部;P型阱区,设置于埋层隔离层之上;侧面隔离区,设置于所述P型阱区外侧;栅极,设置于所述P型阱区之上;源区,设置在所述栅极的一侧,包括设于所述P型阱区内的第一N型掺杂区,邻接所述第一N型掺杂区的第一N型漂移区,设于所述第一N型漂移区上的场氧化层以及设于所述第一N型掺杂区之上的第一重掺杂N型区;漏区,与所述源区相对于所述栅极对称地设置在另一侧,所述漏区包括设于所述P型阱区内的第二N型掺杂区,邻接所述第二N型掺杂区的第二N型漂移区,设于所述第二N型漂移区上的场氧化层以及设于所述第二N型掺杂区之上的第二重掺杂N型区;
然后在第一N型掺杂区与所述埋层隔离层之间,通过增加一次P型注入形成P型注入区,所述P型注入区与埋层隔离层的距离较其与所述第一N型掺杂区和第二N型掺杂区的距离更短。
6.如权利要求5所述的对称隔离LDMOS器件的制造方法,其特征在于,增加的P型注入的杂质注入面密度为1013~1014cm-2量级。
7.如权利要求5或6所述的对称隔离LDMOS器件的制造方法,其特征在于,所述P型注入的杂质注入能量为100Kev到500Kev。
8.如权利要求7所述的对称隔离LDMOS器件的制造方法,其特征在于,通过N型注入形成第一N型掺杂区,并从与所述N型注入相同的注入区域进行所述增加的P型注入,以使所述P型注入区位于所述第一N型掺杂区的正下方。
9.如权利要求8所述的对称隔离LDMOS器件的制造方法,其特征在于,增加的P型注入的杂质为硼离子。
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