CN106663699A - 用于具有经级联resurf植入部及双缓冲器的ldmos装置的方法及设备 - Google Patents

用于具有经级联resurf植入部及双缓冲器的ldmos装置的方法及设备 Download PDF

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CN106663699A
CN106663699A CN201580042187.4A CN201580042187A CN106663699A CN 106663699 A CN106663699 A CN 106663699A CN 201580042187 A CN201580042187 A CN 201580042187A CN 106663699 A CN106663699 A CN 106663699A
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conductivity
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diffusion
semiconductor substrate
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CN106663699B (zh
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蔡军
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

在所描述实例中，一种LDMOS装置(1200)包含：至少一个漂移区域(1222)，其安置于半导体衬底(1210)的一部分中；至少一个隔离结构(1252)，其位于所述半导体衬底(1210)的表面处；D阱区域，其邻近所述至少一个漂移区域(1222)的一部分而定位，且所述漂移区域(1222)与所述D阱区域的相交点形成第一导电性类型与第二导电性类型之间的结(1226)；栅极结构(1282)，其安置于所述半导体衬底(1210)上方；源极触点区域(S)，其安置于所述D阱区域的表面上；漏极触点区域(D)，其邻近所述隔离结构(1252)而安置；及双缓冲器区域，其包含：第一隐埋式层(1228)，其位于所述D阱区域及所述漂移区域(1222)下面且被掺杂成所述第二导电性类型；及第二高电压深扩散层(1218)，其位于所述第一隐埋式层(1228)下面且被掺杂成所述第一导电性类型。

Description

用于具有经级联RESURF植入部及双缓冲器的LDMOS装置的方 法及设备
技术领域
此涉及集成电路(IC)的领域，且更具体来说涉及横向双扩散金属氧化物半导体(LDMOS)装置的制作。
背景技术
对可提供半导体集成电路上的高功率驱动能力的晶体管的需要引起横向双扩散金属氧化物半导体(LDMOS)装置的发展。对于LDMOS装置来说尤其有意义的应用包含用于输出缓冲器及射频(RF)电路的高侧驱动器及低侧驱动器。双扩散MOS装置(DMOS)用于其中需要高电压容量及低电阻的应用。LDMOS晶体管展现出高击穿电压BVdss及低导通电阻RDSon，且因此非常适合于高功率应用。
在以DMOS工艺形成的晶体管中，源极及背栅扩散是通过到衬底中的同步或同时执行的离子植入及后续驱动退火而形成。漏极扩散部与下伏栅极电极的沟道区域间隔开漂移区域，所述漂移区域可下伏隔离区域形成。半导体衬底的表面处的所得扩散部之间的间隔确定LDMOS晶体管的沟道长度。
图1在横截面图中描绘常规LDMOS装置100。在图1中，提供p型半导体衬底110。在图1中展示形成于所述衬底上方的p型外延层114。N型隐埋式层(标记为“NBL”且编号为120)展示于LDMOS结构的底部处。NBL 120通过光掩模图案化及离子植入步骤形成。同样，展示P型隐埋式区域(标记为“PBL”且编号为116)。这些区域是借助第二单独掩模图案化及单独离子植入步骤形成。LDMOS装置100包含位于形成于扩散部DWL 136中的源极区域的任一侧上的两个对称部分，每一侧具有栅极及漏极布置。通常，这些区域耦合在一起以形成大晶体管，但可替代地形成具有共同源极及背栅部分的两个晶体管。类似形成且布置的许多区域可共同耦合以形成较大晶体管。
在图1中，在EPI区域114的任一侧上展示编号为118的深N阱区域。在区域118中的每一者中，展示形成漏极扩散的浅N阱(标记为“SNW”且编号为121)。在深N阱区域118外部，展示浅P阱(标记为“SPW”且编号为122)。在处理P-EPI 114及PBL 116的同时，此也形成集成式LDMOS装置100与其它附近装置结之间的隔离。在区域118中的每一者中，P隐埋式层区域(编号为116)位于NBL 120的顶部上，如在图1中所展示，从而形成PBL区域到DNW区域之间的电荷平衡而实现LDMOS装置的减小表面场效应(“RESURF”)。在实例性布置中，深N阱118可由n型掺杂区形成，而浅N阱区域(标记为“SNW”、编号为121)可由用于MOS装置的半导体工艺中的低电压CMOS N型扩散阱形成。这些SNW区域112用于形成LDMOS漏极触点到DNW 118的电连接。此外，形成于上覆于衬底上的导体中的漏极端子D可与漏极接触区128耦合且由CMOS源极/漏极n+掺杂扩散部形成。
在图1中，展示上覆于衬底表面上的两个栅极电极(编号为132)。在操作中，栅极端子上的电位将使晶体管导通且在衬底中形成其中载流子可从源极行进到漏极的沟道区域。N+源极区域(编号为134)形成于p型D阱扩散部(标记为DWL且编号为136)内。与N+源极134邻接的额外P+D阱接触区域135用于D阱连接。隔离氧化物区域130(其可通过浅沟槽隔离形成)在图1中展示为上覆于漂移区域上且标记为“STI”。DNW通过离子植入提供以形成位于STI下方的漂移区域(标记为“RESURF”138)，所述漂移区域提供用于LDMOS晶体管的减小表面场效应(“RESURF”)。RESURF LDMOS晶体管具有增加的击穿电压BVdss以用于处置由功率装置经受的高电压。
在操作中，电子载流子从源极区域跃迁过形成于栅极下面的沟道区域且接着跃迁过漂移区域到达漏极端子。在实例中，源极端子S耦合到接地电位，而高电压(例如35伏特、50伏特或更高伏特)耦合到漏极端子。栅极端子132处的电位可接着用于使装置导通，且高功率电流接着流动通过所述装置(从漏极到源极，与电子载流子方向相反)。
在关于功率装置的已知方法中，LDMOS晶体管的使用提供具有高击穿电压特性(其能够处置非常高电压(例如源极或漏极端子处的50伏特))且具有相对低电阻Rdson的装置。然而，图1中所描绘的现有LDMOS装置100仍经受各种问题及性能问题。还需要要求较少硅面积的装置以增加集成并减小包含LDMOS晶体管的集成电路的面积。在LDMOS装置的目标高电压处，漂移区域中的单个RESURF可不足以处置在半导体工艺持续缩减时发生的经减小漂移长度下装置漏极到源极之间的高电压。此外，在较小漂移长度下，区域“X”(JFET区，在图1中标记为“X”)中的电场变得较强，此容易地诱发较低装置漏极到源极击穿电压且还致使电流涌入所标记“X”区域中，且此可导致沟道热载流子(“CHC”)效应。举例来说，在CHC中，一些载流子(电子或空穴)可隧穿到栅极电介质中且被陷获，从而使栅极电介质材料降级且降低晶体管装置性能及可靠性。同样，隐埋式层“NBL”及“PBL”的使用通过需要额外及特定光掩模、图案及植入步骤而给标准CMOS半导体制造工艺添加复杂性，从而增加生产成本。
发明内容
在所描述实例中，一种LDMOS装置包含：至少一个漂移区域，其安置于半导体衬底的一部分中；至少一个隔离结构，其位于所述半导体衬底的表面处；D阱区域，其邻近所述至少一个漂移区域的一部分而定位，且所述漂移区域与所述D阱区域的相交点形成第一导电性类型与第二导电性类型之间的结；栅极结构，其安置于所述半导体衬底上方；源极触点区域，其安置于所述D阱区域的表面上；漏极触点区域，其邻近所述隔离结构而安置；及双缓冲器区域，其包含：第一隐埋式层，其位于所述D阱区域及所述漂移区域下面且被掺杂成所述第二导电性类型；及第二高电压深扩散层，其位于所述第一隐埋式层下面且被掺杂成所述第一导电性类型。
附图说明
图1在经简化横截面图中描绘现有方法的实例性LDMOS装置。
图2到12在一系列横截面图中图解说明用以使用本申请案的半导体工艺布置来制造LDMOS装置的连续处理步骤。
图13在横截面图中图解说明在衬底上彼此邻近构造的LDMOS晶体管及PMOS晶体管的布置。
图14在流程图中描绘用以在本申请案的半导体工艺布置中形成LDMOS装置的第一系列处理步骤。
图15在另一流程图中描绘用以在半导体工艺中形成LDMOS装置的额外处理步骤。
具体实施方式
各图未必按比例绘制。
存在对具有经改进减小表面场效应性能的LDMOS晶体管装置的持续需要。需要在与现有方法相比时具有经减少过程步骤及经减少成本的可与标准CMOS装置一起制造的LDMOS晶体管。存在对具有非常高击穿电压BVdss、经减小导通电阻、经改进CHC性能且以更低成本需要低于现有LDMOS装置所需要的硅面积的硅面积的LDMOS装置的需要。
形成本申请案的各种方面的布置提供形成于半导体工艺中的LDMOS装置，所述LDMOS装置具有双缓冲器布置且进一步使用链式离子植入步骤而形成以在漂移区域及D阱区域两者中包含级联resurf扩散部以实现高性能。还揭示对应方法布置。
在实例性布置中，一种LDMOS装置包含：至少一个漂移区域，其安置于半导体衬底的一部分中且被掺杂成第一导电性类型；至少一个隔离结构，其位于所述半导体衬底的表面处且定位于所述至少一个漂移区域的一部分内；D阱区域，其位于所述半导体衬底的另一部分中，被掺杂成第二导电性类型且邻近所述至少一个漂移区域的一部分而定位，且所述漂移区域与所述D阱区域的相交点形成所述第一导电性类型与所述第二导电性类型之间的结；栅极结构，其安置于所述半导体衬底的表面上且上覆于沟道区域及所述隔离结构的一部分上，所述栅极结构包含位于所述沟道区域上方的栅极电介质层及上覆于所述栅极电介质上的栅极导体材料；源极触点区域，其安置于所述D阱区域的表面上且在邻近所述沟道区域的一侧处，所述源极触点区域开始被掺杂成所述第一导电性类型；漏极触点区域，其安置于所述漂移区域的表面上的浅扩散阱中并邻近所述隔离结构且通过所述隔离结构与所述沟道区域间隔开，所述漏极触点及所述浅扩散阱被掺杂成所述第一导电性类型；及双缓冲器区域，其包含：第一隐埋式层，其位于所述D阱区域及所述漂移区域下面且被掺杂成所述第二导电性类型；及第二高电压深扩散层，其位于所述第一隐埋式层下面且被掺杂成所述第一导电性类型。
在另一布置中，一种用于形成LDMOS装置的方法包含：提供半导体衬底；在所述半导体衬底上方形成外延层；通过在所述半导体衬底上方的所述外延层中植入杂质而形成第一导电性类型的第一隐埋式层，所述外延层及所述半导体衬底被掺杂成第二导电性类型；在所述隐埋式层上方形成所述第二导电性类型的直列式外延层；执行第一链式植入中的所述第一导电性类型的第一离子植入以形成高电压深阱缓冲器区域；执行所述第二导电性类型的离子植入以形成安置于高电压阱区域与漂移区域之间的第二隐埋式层，高电压深阱区域及所述第二隐埋式层形成双缓冲器区域；在所述半导体衬底的表面处形成位于所述第一导电性类型的所述阱中的隔离区域；在所述衬底上方沉积栅极电介质，在所述栅极电介质上方沉积栅极导体，且接着蚀刻所述栅极导体及所述栅极电介质以形成上覆于沟道区域上的栅极结构；及植入杂质以形成通过所述沟道区域与所述栅极结构间隔开的源极区域且形成位于所述漂移区域中且通过所述隔离区域与所述栅极结构间隔开的漏极区域。
在再一布置中，一种集成电路包含：LDMOS装置，其进一步包含：至少一个漂移区域，其安置于半导体衬底的一部分中且被掺杂成第一导电性类型；至少一个隔离结构，其位于所述半导体衬底的表面处且定位于所述至少一个漂移区域的一部分内；D阱区域，其位于所述半导体衬底的另一部分中，被掺杂成第二导电性类型且邻近所述至少一个漂移区域的一部分而定位，且所述漂移区域与所述D阱区域的相交点形成所述第一导电性类型与所述第二导电性类型之间的结；栅极结构，其安置于所述半导体衬底的表面上且上覆于沟道区域及所述隔离结构的一部分上，所述栅极结构包含位于所述沟道区域上方的栅极电介质层及上覆于所述栅极电介质上的栅极导体材料；源极触点区域，其安置于所述D阱区域的表面上且在邻近所述沟道区域的一侧处，所述源极触点区域开始被掺杂成所述第一导电性类型；漏极触点区域，其安置于所述漂移区域的表面上的浅扩散阱中并邻近所述隔离结构且通过所述隔离结构与所述沟道区域间隔开，所述漏极触点及所述浅扩散阱被掺杂成所述第一导电性类型；及双缓冲器区域，其包含：第一隐埋式层，其位于所述D阱区域及所述漂移区域下面且被掺杂成所述第二导电性类型；及第二高电压深扩散层，其位于所述第一隐埋式层下面且被掺杂成所述第一导电性类型；及至少一个CMOS装置，其形成于所述半导体衬底中且与所述LDMOS装置间隔开。
本申请案中认识到，具有形成于n型隐埋式层上方的由p型隐埋式层上覆于高电压深N阱层上而形成的双缓冲器的LDMOS晶体管的布置提供高性能LDMOS晶体管。在额外布置中，在漂移区域及主体区域两者中形成链式resurf扩散植入部以进一步减小表面场效应、解决沟道热载流子问题且减少掩模层级以减少成本。应用包含功率晶体管装置(例如低侧及高侧驱动器)、汽车应用、RF电路及高频率装置。
本申请案包含若干布置，所述布置描述在CMOS兼容半导体工艺中使用各种植入来形成经扩散区域以形成LDMOS装置。针对MOS晶体管装置，名称“源极”及“漏极”指代这些区域的电连接，且在MOS装置的物理结构的横截面图中，“源极”及“漏极”通常为形成于晶体管栅极的相对侧上的相同且对称经掺杂扩散区域。在许多情形中可通过反转“源极”及“漏极”区域而形成额外替代布置。
由于在形成具有布置的LDMOS RESURF装置时使用的各种离子植入步骤类似于已在MOS制作工艺中使用的离子植入步骤，因此以相对低成本实现用以产生LDMOS RESURF装置的工艺。同样，所述工艺可同时用于产生与LDMOS RESURF装置相同的集成电路中的NMOS及/或PMOS晶体管。以此方式，可使用与LDMOS装置一起产生的CMOS装置形成控制电路、计算电路及输入/输出电路，从而形成具有所有所需电路的单个集成电路以将LDMOS装置用于可在现有半导体工艺中容易制造的系统中。在也设想为形成本申请案的额外方面的替代方法中，LDMOS RESURF晶体管装置可在不需要额外NMOS及PMOS装置的情况下形成于排列式集成电路装置上。
图2描绘图解说明在构造LDMOS经级联RESURF装置200时执行的连续步骤的一系列横截面中的第一者。LDMOS经级联RESURF装置200可在一些布置中以对现有CMOS半导体工艺的稍微修改而形成。相关领域的技术人员将认识到，存在据以实现LDMOS经级联RESURF装置的构造的替代方法及步骤次序，且此非限制性制作实例仅为针对此配置的那些方法中的一者。托管LDMOS经级联RESURF装置(且在形成本申请案的若干方面的一些布置中，还托管其它MOS晶体管装置)的半导体衬底210可在一个实例性布置中为P型单晶硅衬底。在CMOS工艺中支持制作集成电路的任何衬底(其包含但不限于绝缘体上硅(SOI)或混合定向技术(HOT)衬底)中或在与CMOS半导体制作兼容的任何外延层上形成LDMOS经级联RESURF装置也在本申请案的范围内。在图2中，展示初始外延层212，P型层上覆于所述初始外延层上。可在一些替代布置中省略此外延层。衬底210及外延层212在一个实例性布置中提供为用于半导体工艺的起始材料。在其它布置中，省略外延层212。
图3在横截面图中描绘在图解说明N型隐埋式层或“NBL”(编号为314)的制作的下一步骤之后的LDMOS经级联RESURF装置300。为形成如在图3中所展示的此层，在衬底310上方执行n型掺杂剂种类的毯覆植入351以形成NBL 314。在下文所描述的稍后步骤中，可形成深沟槽或具有n+材料的深沟槽且所述深沟槽可耦合到NBL以形成N型槽。此槽可用于将LDMOS经级联RESURF装置300与衬底310上的其它区及其它装置进行电隔离。如在图3中所展示，隐埋式层314可形成为到衬底310上方的P-epi 312的毯覆植入。此与现有方法形成鲜明对比，且毯覆植入不需要掩模、光致抗蚀剂、图案化及光致抗蚀剂剥除工艺，替代地可在不需要光掩模的情况下执行NBL 314的离子植入。可通过将n型掺杂剂(例如磷或砷)植入到非常高浓度而形成NBL 314。举例来说，可使用5×l015原子/cm2的植入剂量。在替代布置中，可在执行植入步骤之前使用掩模层来形成NBL 314。在此布置中，可在LDMOS装置周围形成n型槽结构。
图4在横截面图中描绘在构造LDMOS装置400时执行的接下来的步骤。在图4中，执行直列式外延工艺以在n型隐埋式层NBL 414上方形成P型外延层416。还展示初始层p外延层412及衬底410，其如上文所描述而布置。
图5在横截面图中描绘在额外连续制作步骤之后的LDMOS装置500。在图5中，使用掩模及图案化工艺来执行n型掺杂剂的一连串离子植入步骤以形成抗蚀剂图案537。在p外延层516的一部分中形成数个离子植入区。举例来说，在第一离子植入步骤中，通过在2MeV到3MeV的能量下且在1×1012原子/cm2到3×1012原子/cm2的植入剂量下进行磷的离子植入而形成高电压深N阱缓冲器518。
在深N阱缓冲器离子植入531之后，(例如)在600KeV到2MeV的植入能量及～2×l012原子/cm2到～5×l012原子/cm2的植入剂量下使用磷作为掺杂剂原子而执行链式植入中的第二n型离子植入(编号为533)。此在漂移区域522中形成n型掺杂区域。
仍参考图5，执行n型离子植入步骤链中的第三植入以在“JFET”区域(编号为524)中形成植入部。执行离子植入535以形成JFET区域，在一个布置中，此植入可在l00Kev到350KeV的植入能量下且在～1×l012原子/cm2到9×l012原子/cm2的植入剂量下使用砷掺杂剂原子。以此方式，连续执行n型离子植入链且不需要介入步骤或过程。由在这些植入步骤期间使用的掩模537形成n型阱，使得沿着线526形成p-n结。在执行n型离子植入链之后，执行被称为驱动步骤的热步骤以使扩散区域完整。
图6在另一横截面图中图解说明形成LDMOS装置600的额外连续过程步骤。在图6中，展示编号为651的离子植入步骤且所述离子植入步骤经执行以形成p型隐埋式层PBL628。在一个布置中，此植入步骤是使用毯覆植入执行，使得不需要掩模、图案化及蚀刻步骤，且所使用的掺杂剂可为硼。可在从～3×1012原子/cm2到8×1012原子/cm2的植入剂量下使用800KeV到2.5MeV的植入能量。包含在图6中所展示的HV深N阱缓冲器(编号为618)及p隐埋式层PBL(编号为628)的布置形成用于LDMOS装置的双缓冲器特征。LDMOS装置漂移区域电阻可通过本申请案的专用PBL缓冲器628到N阱漂移622区域电荷平衡RESURF设计而显著减小。在本申请案的布置中，由于深结深度处的较高HV深N阱掺杂浓度而实现针对装置导通状态的非常低漂移区域电阻。漂移区域622(其将安置于如下文在稍后步骤中描述的隔离区域STI下方)可由PBL缓冲器628到HV深N阱618的漂移区域622之间的p-n结的耗尽区域隔离开，从而实现较高漏极到源极关断状态击穿电压。需要相对高PBL缓冲器掺杂浓度以使高掺杂N阱漂移区域622电荷平衡，且现有方法的LDMOS装置中的NBL到高掺杂PBL低雪崩击穿的问题通过所插入HV深N阱N型缓冲器层618而改进。同样，深沟槽隔离结构(图6中不可见，但在下文进一步描述)可耦合到NBL 614且可针对LDMOS装置而形成具有N型底部及侧的经隔离槽，从而进一步改进隔离。p-n结626如之前一样布置。据称，图6的p型植入步骤可将p型隐埋式层或PBL 628插入到n型链式植入部中。
在工艺中的此阶段处，可在LDMOS装置附近形成额外深沟槽隔离结构。在一个布置中，深沟槽或“DT”区域可由氧化物或内衬于沟槽的其它电介质形成，其中P+材料形成于电介质区域内侧且延伸到p外延层。在第二布置中，DT结构可进一步包含内衬于沟槽且向下延伸到N隐埋式层的N+材料，且另外，N+材料可形成为通过电介质材料与P+材料隔离，且延伸到NBL层以从N型槽结构。DT结构的使用为LDMOS装置提供优异的电隔离。可形成顶部侧触点以允许槽电耦合到电位以用于进一步隔离及噪声控制。
图7在横截面图中描绘可与布置一起使用的深沟槽结构700的一部分。深沟槽结构700是在图6中的PBL植入完成之后形成。举例来说，深沟槽结构可为其中电介质内衬于各侧且P+材料758形成于中心部分中并延伸到p外延层712的沟槽。在图7的布置中，深沟槽结构进一步包含N+材料754。电介质部分756将N+部分与P+材料758隔离。N+材料754延伸穿过STI752、N阱材料722/724、PBL 728、深N阱718且接触N隐埋式层NBL 714。P+材料758延伸穿过所有这些层且延伸到P-epi层712中或穿过P-epi层712以接触P衬底710。深沟槽700以横截面展示但可围绕在上文的各图中所展示的LDMOS装置延伸以便形成槽形沟槽，且具有N+材料754的N隐埋式层714可形成N型隔离槽。
在图7中所形成的STI层752也用作LDMOS装置的部分。在图8中，展示在来自图6的连续步骤(其包含在漂移区域上方形成STI绝缘体852)之后的LDMOS装置800。在图8中，LDMOS装置800包含STI层852、JFET扩散部824、漂移扩散部822(其为N型扩散部)、P-epi材料816以及由PBL 828及HV深N阱缓冲器818(其形成于n型隐埋式层NBL 814上方)形成的双缓冲器、P型外延层812及P型衬底810及结826，其全部如上文所描述而布置。在替代布置中，可代替STI层852而使用LOCOS隔离部。
图9描绘LDMOS装置900且图解说明用以形成装置的额外过程步骤。在图9中，执行第一p型掺杂剂的链式植入以修整LDMOS装置的D阱深上部/下部主体结构中的掺杂剂水平。使用光掩模、抗蚀剂及图案工艺形成抗蚀剂层947。一连串p型植入以编号为971的植入开始，例如在从～3×1012原子/cm2到～8×1012原子/cm2的植入剂量下使用硼作为掺杂剂且使用～1MeV到2MeV的植入能量。此植入在p-epi层916中形成扩散区域954且形成深上部(扩散部956)/下部(扩散部954)主体区域的一部分。在编号为971的植入之后，执行第二植入973。在此离子植入步骤中，在先前扩散区域上面形成扩散区域956。在一个布置中，此第二植入是使用硼植入执行，其中植入能量介于400KeV到～800KeV之间，其中植入剂量介于8×1012原子/cm2到～5×1013原子/cm2之间。向下深入主体扩散部954用于将D阱与PBL连结，且向上深入主体扩散部956用于对靠近于STI 952底部隅角区的N阱JFET区域924构建分布式电荷平衡区域以实现横向JFET RESURF。在图9中，衬底910、p外延层912、NBL 914、深N阱缓冲器918及PBL 928、N阱漂移区域922全部如上文所描述而布置。
图10在用于形成LDMOS装置1000的下一连续步骤中进行图解说明。在图10中展示额外链式离子共植入。此共植入与图9中的深上部/下部主体植入共享相同抗蚀剂图案及光掩模以形成额外扩散区域1058以实现浅主体及有效沟道区域。此额外扩散区域1058控制靠近于衬底表面的场效应且此CHANNEL RESURF来自靠近装置漏极侧上的沟道区域的子表面电荷平衡，所述子表面电荷平衡通过D阱浅主体(来自共植入扩散部1058的p型离子)到靠近STI 1052的侧壁的HV深N阱的顶部部分进行调整。本申请案的布置的沟道resurf及JFETresurf扩散概念的使用解决沟道热载流子问题，从而允许使用短沟道装置而不形成现有方法的沟道热载流子。同样，JFET区域电阻由于此区域中的较均匀电流流动而减小。图10中的离子植入步骤1075及1076是使用共植入到扩散区域1058中的p型及n型植入离子而执行，在扩散区域1058中n型区用作装置n型源的部分且共植入p型区域形成装置D阱浅主体。两个植入均可经调整以控制LDMOS装置有效沟道区域。在实例性共植入步骤1075中，展示为1075的p型植入可使用1×l013原子/cm2到～3×1014原子/cm2的植入剂量在60Kev到260KeV的植入能量下使用硼作为掺杂剂原子而执行。针对n型共植入1076，砷可在～2×l013原子/cm2到～1×l015原子/cm2的植入剂量下以～20KeV到～220KeV的植入能量植入。这些共植入步骤形成装置的浅主体扩散区域1058，从而针对所形成的LDMOS装置1000减小沟道区域的表面处的电场。
漂移resurf、JFET resurf及沟道resurf植入步骤级联在一起以改进从装置漏极到漂移区域且到JFET及沟道区域的装置电场分布以用于提供高性能LDMOS装置。
图10中所图解说明的其余元件STI 1052、JFET扩散部1024、N阱中的漂移扩散部1022、p隐埋式层1028、HV深N阱缓冲器1018、n隐埋式层NBL 1014、p外延层1012、衬底1010且如之前一样布置。主体扩散部1054、1056及1058在p外延层1016的主体区域中提供额外性能，所述主体区域形成LDMOS装置的D阱。如下文所描述，LDMOS装置的源极触点及主体触点将形成于此D阱区域上方。结1026形成于p-epi材料1016中的D阱区域与N阱区域之间。
图11在又一横截面图中描绘用以形成LDMOS装置1100的栅极及栅极电介质的连续步骤。栅极电介质层1180(其通常为二氧化硅、氧化铪或其它绝缘材料且具有介于～1nm与～45nm之间的厚度)通过已知方法形成于衬底1110的顶部上。通过LDMOS装置所要的栅极电压额定(例如栅极电压1.5V、3.3V、5V及12V)而确定栅极电介质材料及厚度的选择。在形成本申请案的方面的一个布置中，衬底1110的其它部分中的额外NMOS栅极及PMOS栅极电介质层或栅极绝缘体(图11中未展示)可用类似材料及类似厚度制作，且可在时间上与LDMOS栅极电介质1180同时形成。替代地，PMOS及NMOS栅极电介质可独立于具有不同材料及/或厚度的LDMOS栅极电介质而形成。
仍参考图11，栅极1182形成于栅极电介质1180的顶部上。栅极1182通常由多晶硅(被称为polysilicon)形成。多晶硅沉积于栅极电介质层上方且也可沉积于NMOS及PMOS栅极电介质层(未展示)上方以在衬底1110上的其它地方形成NMOS及PMOS栅极结构。
图11中所图解说明的其余元件STI 1152、JFET扩散部1124、N阱中的漂移扩散部1122、p隐埋式层1128、HV深N阱缓冲器1118、n隐埋式层NBL 1114、p外延层1112、衬底110及1126处的结如之前一样布置。D阱或主体扩散部1154、1156及共植入区域1158在p外延层1116的主体区域中提供额外性能，所述主体区域形成LDMOS装置的D阱。如下文所描述，LDMOS装置的源极触点及主体触点将形成于此D阱区域上方。结1126形成于p-epi材料1016中的D阱区域与N阱区域之间。
图12在另一横截面图中描绘额外处理步骤之后的LDMOS装置1200。栅极光致抗蚀剂图案(为简便起见未图解说明)经施加于栅极1282上方且针对蚀刻工艺而图案化。通过已知蚀刻方法移除任何非所要栅极多晶硅及下伏栅极电介质的非所要部分。接着还移除栅极光致抗蚀剂。安置于半导体衬底1210的位于衬底1210中的其它地方且在图12中不可见的部分中的任何NMOS及/或PMOS晶体管的栅极结构可在LDMOS栅极多晶硅1282形成时同步图案化。在形成本申请案的额外方面的一些布置中，替换栅极(例如金属栅极)可在稍后处理步骤处替换多晶硅栅极1282。如在图12中所展示，栅极侧壁间隔件1288于是由绝缘体形成，例如氧化物层、氮氧化物层或氮化物层。栅极间隔件1288可通过氧化物沉积或通过其它已知技术形成。栅极间隔件接着通过各向异性蚀刻步骤形成。关于本文中所描述的其它步骤，可同步形成在图12中不可见的衬底1210的其它部分中同时制作的NMOS及/或PMOS装置的栅极结构。
仍参考图12，通过使用低电压PMOS N阱植入而形成浅N阱1290，浅N阱1290通常在栅极氧化物及栅极多晶硅工艺步骤之前形成。在实例性布置中，针对LDMOS漏极区域的此阱1290也与针对制作于衬底1210上的其它地方的CMOS装置而形成的N阱区域同时形成。
进一步仍参考图12，在额外处理步骤中形成P+主体触点(标记为B)、N+源极触点(标记为S)及漏极触点(标记为D)。在布置中，触点植入步骤还经执行以形成针对位于衬底上的其它地方的CMOS装置的源极触点及漏极触点。还形成到栅极的触点G。
图12中所展示的横截面图解说明基本上完整LDMOS装置1200。LDMOS装置1200包含主体触点B、源极触点S、栅极触点G及漏极触点D，由HV深N阱缓冲器1218及p型隐埋式层PBL1228形成的双缓冲器，形成漂移及JFET resurf扩散部的漂移区域resurf植入部1222、1224，D阱区域中的上/下主体扩散部1256、1254，及通过共植入工艺形成的沟道resurf扩散部1258。NBL 1214、p外延层1212及衬底1210全部如之前一样布置。
在操作中，沟道区域1285形成于介于标记为“S”的源极N+区域与介于p型D阱区域与n型漂移区域之间的p-n结1226之间的栅极区域下面。当大于阈值的电位施加到栅极端子G时，反转区域形成且载流子可从标记为S的N+源极区域跨越沟道行进且行进到漂移区域中，且接着漂移到STI绝缘体1252下面的N+漏极区域D。由上文所描述的链式离子植入步骤形成的在沟道、主体区域及漂移区域中的各种经掺杂扩散部的使用减小表面场效应以提供“resurf”装置、增加击穿电压BVdss且提供合理低的漏极到源极导通电阻Rdson以实现高性能LDMOS晶体管。
图13在另一横截面图中描绘完成的LDMOS装置1300，LDMOS装置1300是与在CMOS半导体制作工艺内形成的MOS晶体管同时构建。图13图解说明同时在衬底上形成CMOS装置及LDMOS装置两者的能力。LDMOS装置1300包含主体触点B、源极触点S、栅极触点G及漏极触点D，由HV深N阱缓冲器1318及p型隐埋式层PBL 1328形成的双缓冲器，形成漂移及JFETresurf扩散部的漂移区域resurf植入部1322、1324，D阱区域中的上/下主体扩散部1356、1354，及通过共植入工艺形成的沟道resurf扩散部1358。p-n结1326形成于p-epi区域1316中的D阱区域与N阱区域之间。深沟槽隔离结构1301通过延伸到且接触NBL 1314的n型材料1362及延伸到衬底1310的p型材料1364形成，且包含电介质区域1364以将两种材料彼此隔离。在低电压CMOS区域1302中，PMOS晶体管展示为形成有位于浅N阱1372中的标记为S1的源极触点、标记为G1的栅极及标记为D1的漏极触点，具有单独的N+N阱触点(图13中未展示)。如上文所描述，在链式植入之后用以形成LDMOS装置的一些工艺步骤可在形成用于LDMOS装置及CMOS装置两者的结构时使用，从而实现在衬底1310中进行两种类型的装置的同时制作。举例来说，针对两种类型的装置同时形成多晶硅栅极材料G、G1。以此方式，高度集成电路装置(例如，LDMOS高侧驱动器及用于控制所述驱动器的相关联高电压CMOS控制电路)可形成于硅衬底上的单个集成电路中。
图14在流程图中图解说明用于形成实例性布置中的LDMOS装置的方法的步骤。在图14中，方法在步骤1401处以P衬底上方的p外延层开始。在步骤1403处，通过离子植入执行N型隐埋式层的毯覆形成。在实例中，离子植入使用非常高浓度，使用高达5×1015原子/cm2n型掺杂剂的植入剂量。在一种方法中，在不需要掩模的情况下形成毯覆n型隐埋式层。在替代方法中，使用掩模层且完成选择性植入。在此方法中，稍后形成接触NBL材料的深N结构以在LDMOS装置周围完成n型槽。
在图14中的步骤1405处，形成P材料的直列式外延层以提供用于LDMOS装置(深N阱区域及主体区域)且用于可同时形成于衬底上的CMOS装置的基础材料。
在步骤1407处，执行链式n型离子植入。所述链中的第一植入以从1×1012原子/cm2到3×1012原子/cm2的剂量在2MeV到3MeV的植入能量下使用磷作为掺杂剂原子。此植入形成高电压深N阱缓冲器层，如上文所描述。接着再次使用n型掺杂剂(例如磷)而以从2×l012原子/cm2到～5×l012原子/cm2的植入剂量在从600KeV到～2MeV的能级下执行n型链中的第二植入。此植入形成漂移区域中的用于装置漂移resurf控制的扩散部。接下来，例如使用砷以从l×l012原子/cm2到～9×l012原子/cm2的剂量在从～100KeV到～350KeV的能级下执行n型链中的第三n型植入以形成JFET区域中的扩散部，如上文所描述。在双缓冲器上方使用这些植入区域改进经级联resurf LDMOS装置的性能。
在步骤1409处，形成插入到由n型链式植入形成的n型扩散部中的p隐埋式层。此p型隐埋式层或PBL是通过硼的离子植入而形成，例如在从～800KeV到～2.5MeV的植入能量下，从～3×l012原子/cm2到～8×l012原子/cm2。PBL层上覆于HV深N阱N型缓冲器区域上以形成针对LDMOS晶体管的双缓冲器结构及漂移区域resurf设计，如上文所描述。
在图14中的步骤1411处，形成隔离结构。如果已在毯覆步骤中形成在步骤1403处形成的n型隐埋式层NBL，那么可使用例如在图7或图13中所展示的深沟槽隔离结构。在替代方法中，如果在形成步骤1403处的NBL时使用掩模，那么隔离结构可为深n型触点以与n型隐埋式层一起在LDMOS装置的区周围形成槽。
如在图14中所展示，方法接着过渡到图15中的步骤1501。
在图15中，流程图继续。图15展示用于形成LDMOS晶体管的方法的其余步骤。在步骤1501处，形成用于LDMOS晶体管的浅沟槽隔离或STI区域。同时，可在衬底的其它区域中形成用于CMOS晶体管的额外STI区域，如上文所描述。在步骤1503处，执行第一串p型植入以完成D阱的第一部分或LDMOS装置的深上部/下部主体区域。下部主体部分用于将D阱与PBL连接，且上部主体部分用于靠近LDMOS装置的STI隅角区域的底部支持JFET resurf。以3×1012原子/cm2到～8×l012原子/cm2之间的植入剂量在1MeV到2MeV的植入能量下(例如)使用硼作为掺杂剂原子而执行第一植入；接着以从～8×l012原子/cm2到～5×l013原子/cm2的植入剂量以～400KeV到～800KeV的植入能量而使用硼执行第二p型植入。
在步骤1503之后，使用相同D阱植入掩模层连续执行第二共植入链1505，例如使用硼作为p型掺杂剂且使用砷作为n型掺杂剂。以从～60KeV到～260KeV的植入能量且以从～l×l013原子/cm2到～3×l014原子/cm2的植入剂量执行p型植入；以从～20KeV到～220KeV的植入能量及从～2×1013原子/cm2到～1×1015原子/cm2的植入剂量执行n型植入。如上文所描述，共植入形成具有用于LDMOS装置的沟道resurf设计的浅主体及有效沟道区域。
在本申请案的布置中，漂移resurf、JFET resurf及沟道resurf离子植入级联在一起以改进从装置漏极漂移区到JFET及沟道区域的装置电场分布以实现LDMOS装置的高性能。
在图15中的步骤1507处，方法继续。在此步骤处，用于形成LDMOS装置的其余结构(例如栅极电介质、栅极导体、源极、主体区域及漏极区域)的同时工艺步骤可与用于在衬底上的其它地方制作CMOS装置(例如PMOS及NMOS晶体管)的类似步骤同时执行。以此方式，高度集成电路装置可制成并入有各布置的LDMOS装置。在图15中的步骤1509处，所图解说明方法结束。在执行图14及15中所展示的方法之后，半导体制作工艺继续使用常规步骤(包含硅化物形成、层间电介质、导通体及触点形成、金属沉积及图案化等等)而将结构连接到金属化图案，以使用上部导电层(例如金属导体)将LDMOS装置的源极、主体、漏极及栅极端子及CMOS装置(如果有的话)的源极、漏极及栅极端子耦合到各种信号。
使用图14及15中所展示的方法，可使用仅具有两个额外掩模层级(一个用于n型漂移区域且一个用于D阱或主体区域)的标准CMOS半导体工艺获得具有优越性能的LDMOS装置。使用单个掩模在连续步骤中执行链式植入。用于布置中的双缓冲器的n型隐埋式层及p型隐埋式层可在不使用掩模的情况下在毯覆离子植入中形成，如上文所描述，借此减少制造成本。
使用双缓冲器及经级联resurf扩散布置形成的实例性LDMOS装置已获得性能计量，如上文所描述。所述装置在与使用现有方法获得的装置(例如图1中所展示的装置)相比时展现出优越的击穿电压及经减小电阻。
使用上文所描述的布置及结构获得的LDMOS装置展示了与现有方法相较特定导通电阻32.6％的平均减小，且在10年DC的最大Id转变方面满足汽车工业指南。
从制造成本及复杂性的观点来看，用于形成具有双缓冲器及经级联resurf扩散部的LDMOS装置的方法提供较低掩模计数LDMOS工艺。此外，使用本申请案的布置获得的装置导通电阻Rdson低于已知现有方法。
可在所描述实施例中作出修改，且其它实施例在权利要求书的范围内为可能的。举例来说，也可在步骤的次序方面及在步骤的数目方面作出修改。

Claims (20)

1.一种LDMOS装置，其包括：
至少一个漂移区域，其安置于半导体衬底的一部分中且被掺杂成第一导电性类型；
至少一个隔离结构，其位于所述半导体衬底的表面处且定位于所述至少一个漂移区域的一部分内；
D阱区域，其位于所述半导体衬底的另一部分中，被掺杂成第二导电性类型且邻近所述至少一个漂移区域的一部分而定位，且所述漂移区域与所述D阱区域的相交点形成所述第一导电性类型与所述第二导电性类型之间的结；
栅极结构，其安置于所述半导体衬底的表面上且上覆于沟道区域及所述隔离结构的一部分上，所述栅极结构包含位于所述沟道区域上方的栅极电介质层及上覆于所述栅极电介质上的栅极导体材料；
源极触点区域，其安置于所述D阱区域的表面上且邻近所述沟道区域的一侧，所述源极触点区域被掺杂成所述第一导电性类型；
漏极触点区域，其安置于所述漂移区域的表面上的浅扩散阱中并邻近所述隔离结构且通过所述隔离结构与所述沟道区域间隔开，所述漏极触点及所述浅扩散阱被掺杂成所述第一导电性类型；及
双缓冲器区域，其包含：第一隐埋式层，其位于所述D阱区域及所述漂移区域下面且被掺杂成所述第二导电性类型；及第二高电压深扩散层，其位于所述第一隐埋式层下面且被掺杂成所述第一导电性类型。
2.根据权利要求1所述的LDMOS装置，其中所述第一导电性类型为n型且所述第二导电性类型为p型。
3.根据权利要求1所述的LDMOS装置，其进一步包括：
第一n型resurf扩散区域，其位于所述漂移区域中；及第二n型JFET resurf扩散区域，其位于所述漂移区域中，邻近与所述D阱区域的所述结且在所述第一n型resurf扩散区域上面。
4.根据权利要求3所述的LDMOS装置，其进一步包括靠近所述沟道区域的第三n型扩散部。
5.根据权利要求1所述的LDMOS装置，其进一步包括：第一p型扩散区域，其位于所述D阱区域中邻近所述第一隐埋式层，形成深下部主体扩散部；及第二p型扩散区域，其位于所述D阱区域中邻近与所述漂移区域的所述结，形成上部主体扩散部。
6.根据权利要求5所述的LDMOS装置，其进一步包括位于所述源极触点区域及所述沟道区域中的第三p型扩散区域。
7.根据权利要求1所述的LDMOS装置，其中所述半导体衬底进一步包含所述第二导电性类型的外延层。
8.根据权利要求7所述的LDMOS装置，其中所述LDMOS装置进一步包含第二隐埋式层，所述第二隐埋式层在高电压深阱下面且作为所述第一导电性类型的植入区域而形成于所述半导体衬底中的所述外延层中。
9.根据权利要求8所述的LDMOS装置，其进一步包括深隔离结构，所述深隔离结构与所述D阱区域间隔开且从所述衬底的所述表面穿过所述第一隐埋式层、所述高电压深扩散层且穿过所述外延层而延伸且与所述半导体衬底接触。
10.根据权利要求8所述的LDMOS装置，其进一步包括深沟槽隔离结构，所述深沟槽隔离结构与所述D阱区域间隔开且从所述衬底的所述表面延伸穿过所述第一隐埋式层及所述高电压深阱且延伸到所述第二隐埋式层中。
11.根据权利要求10所述的LDMOS装置，其中所述深沟槽隔离结构进一步包含与所述第二隐埋式层物理接触的所述第一导电性类型的材料。
12.一种用于形成LDMOS装置的方法，所述方法包括：
提供半导体衬底；
在所述半导体衬底上方形成外延层；
通过在所述半导体衬底上方的所述外延层中植入杂质而形成第一导电性类型的第一隐埋式层，所述外延层及所述半导体衬底被掺杂成第二导电性类型；
在所述隐埋式层上方形成所述第二导电性类型的直列式外延层；
执行第一链式植入中的所述第一导电性类型的第一离子植入以形成高电压深阱缓冲器区域；
执行所述第二导电性类型的离子植入以形成安置于所述高电压深阱缓冲器区域与漂移区域之间的第二隐埋式层，所述高电压深阱缓冲器区域及所述第二隐埋式层形成双缓冲器区域；
在所述半导体衬底的表面处形成位于所述第一导电性类型的所述阱中的隔离区域；
在所述衬底上方沉积栅极电介质，在所述栅极电介质上方沉积栅极导体，且接着蚀刻所述栅极导体及所述栅极电介质以形成上覆于沟道区域上的栅极结构；及
植入杂质以形成通过所述沟道区域与所述栅极结构间隔开的源极区域且形成位于所述漂移区域中且通过所述隔离区域与所述栅极结构间隔开的漏极区域。
13.根据权利要求12所述的方法，其中所述第一导电性类型为n型且所述第二导电性类型为p型。
14.根据权利要求13所述的方法，其中执行所述第一链式植入进一步包含：执行所述第一导电性类型的第二离子植入以形成位于阱区域中的漂移resurf扩散部，及执行所述第一导电性类型的第三离子植入以形成位于所述阱区域中且在所述漂移resurf扩散部上面的JFET resurf扩散部。
15.根据权利要求13所述的方法，进一步包括：在形成所述隔离区域之后，通过以下操作执行所述第二导电性类型的第二链式离子植入：执行所述第二链式离子植入的第一植入，包含植入所述第二导电性类型的杂质以形成第一D阱区域下部扩散部；及执行所述第二链式离子植入的第二植入，包含植入所述第二导电性类型的杂质以形成在所述第一D阱区域下部扩散部上面的第二D阱上部扩散区域。
16.根据权利要求15所述的方法，其进一步包括执行额外链式植入以共植入所述第一导电性类型及所述第二导电性类型两者的离子以在所述沟道区域中形成浅resurf扩散区域。
17.根据权利要求13所述的方法，其进一步包括：在形成所述第二隐埋式层之后，形成深沟槽隔离结构，所述深沟槽隔离结构从所述衬底的所述表面延伸穿过所述第二隐埋式层且穿过所述第一隐埋式层以物理地接触所述半导体衬底。
18.一种集成电路，其包括：
LDMOS装置，其包含：
至少一个漂移区域，其安置于半导体衬底的一部分中且被掺杂成第一导电性类型；
至少一个隔离结构，其位于所述半导体衬底的表面处且定位于所述至少一个漂移区域的一部分内；
D阱区域，其位于所述半导体衬底的另一部分中，被掺杂成第二导电性类型且邻近所述至少一个漂移区域的一部分而定位，且所述漂移区域与所述D阱区域的相交点形成所述第一导电性类型与所述第二导电性类型之间的结；
栅极结构，其安置于所述半导体衬底的表面上且上覆于沟道区域及所述隔离结构的一部分上，所述栅极结构包含位于所述沟道区域上方的栅极电介质层及上覆于所述栅极电介质上的栅极导体材料；
源极触点区域，其安置于所述D阱区域的表面上且在邻近所述沟道区域的一侧处，所述源极触点区域开始掺杂成所述第一导电性类型；
漏极触点区域，其安置于所述漂移区域的表面上的浅扩散阱中并邻近所述隔离结构且通过所述隔离结构与所述沟道区域间隔开，所述漏极触点及所述浅扩散阱被掺杂成所述第一导电性类型；及
双缓冲器区域，其包含：第一隐埋式层，其位于所述D阱区域及所述漂移区域下面且被掺杂成所述第二导电性类型；及第二高电压深扩散层，其位于所述第一隐埋式层下面且被掺杂成所述第一导电性类型；及
至少一个MOS装置，其形成于所述半导体衬底中且与所述LDMOS装置间隔开。
19.根据权利要求18所述的集成电路，其中所述至少一个MOS装置进一步包含PMOS晶体管。
20.根据权利要求18所述的集成电路，其中所述第一导电性类型为n型且所述第二导电性类型为p型。
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