CN111223917A - 用于ldmos的屏蔽接触结构及其制备方法 - Google Patents
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Abstract
本发明公开了一种用于LDMOS的屏蔽接触结构,包含设置于多晶硅栅上的第一接触点、设置于STI区内的第二接触点和连接第一接触点和第二接触点的导电金属,第二接触点设置于STI区内的多晶硅上。该屏蔽接触结构能够确保接触点在STI内具有稳定的深度,提高了屏蔽接触结构以及LDMOS的可靠性。本发明同时提供一种包含该屏蔽接触结构的LDMOS器件以及一种用于LDMOS的屏蔽接触结构的制备方法。
Description
技术领域
本发明涉及半导体技术领域,特别涉及一种用于LDMOS的屏蔽接触结构、具有该屏蔽接触结构的LDMOS器件以及该屏蔽接触结构的制备方法。
背景技术
LDMOS(横向扩散金属氧化物半导体)因其具有耐高压、高增益、低失真等优点而被广泛应用于功率集成电路中,而其本身的性能的优劣及其工作的可靠性直接决定了整个功率集成电路性能的优劣。LDMOS的可靠性由高的BVD(击穿电压)和较低的Ron-sp(比导通电阻)来决定。如图1-2所示,现有技术采用屏蔽接触结构来提高LDMOS的可靠性,即在多晶硅(Poly)110栅上设置导电的第一接触点(contact)111,并通过导电金属130与设置在STI(浅槽隔离)区120内的导电的第二接触点121连接,构成屏蔽接触结构(shielding contactstructure)100。现有STI区120内通常填充有氧化物,而以传统的蚀刻方式在填充有氧化物的STI区120内设置第二接触点无法准确限定接触点的深度,极易导致屏蔽接触结构100甚至半导体器件不稳定,直接影响整个功率集成电路的性能。因此,如何能够确保屏蔽接触结构的稳定性成为半导体领域内亟待解决的问题。
发明内容
为了解决现有的技术问题,本发明提出了一种能够确保接触点在STI内具有稳定的深度屏蔽接触结构、具有该屏蔽接触结构的LDMOS器件以及该屏蔽接触结构的制备方法。
依据本发明,提供一种用于LDMOS的屏蔽接触结构,包含设置于多晶硅栅上的第一接触点、设置于STI区内的第二接触点和连接第一接触点和第二接触点的导电金属,第二接触点设置于STI区内的多晶硅上。
依据本发明的一个实施例,STI区内填充有氧化物,多晶硅沉积于氧化物上。
依据本发明的一个实施例,第一接触点包含蚀刻于多晶硅栅上的第一接触孔和填充于第一接触孔内的导电材料。
依据本发明的一个实施例,第二接触点包含蚀刻于多晶硅上的第二接触孔和填充于第二接触孔内的导电材料。
依据本发明,提供一种LDMOS器件,包含上述屏蔽接触结构。
依据本发明,提供一种用于LDMOS的屏蔽接触结构的制备方法,包含以下步骤:
步骤1:在多晶硅栅上设置第一接触点;
步骤2:在STI区内沉积多晶硅,并在多晶硅上设置第二接触点;
步骤3:使用导电金属将第一接触点和第二接触点电连接。
依据本发明的一个实施例,步骤2包含在STI区内填充有氧化物,并将多晶硅沉积于氧化物上。
依据本发明的一个实施例,步骤1包含在多晶硅栅上蚀刻出第一接触孔以及在第一接触孔内填充导电材料。
依据本发明的一个实施例,步骤2包含在多晶硅上蚀刻出第二接触孔以及在第二接触孔内填充导电材料。
由于采用以上技术方案,本发明与现有技术相比具有如下优点:通过在STI内填充一层氧化物后再沉积一层多晶硅,并将接触点设置于多晶硅上,确保接触点在STI内具有稳定的深度,提高了屏蔽接触结构以及LDMOS的可靠性。
附图说明
图1示出了现有技术中包含屏蔽接触结构的LDMOS的示意图;
图2示出了图1所示LDMOS的屏蔽结构的局部放大图;
图3示出了包含依据本发明的屏蔽接触结构的LDMOS的示意图;
图4示出了图3所示LDMOS的屏蔽结构的局部放大图;
图5示出了依据本发明的屏蔽接触结构的制备方法的流程图。
图中:
100现有屏蔽接触结构,200本发明的屏蔽结构,110、210多晶硅栅,111、211第一接触点,120、220STI区,130、230导电金属,240多晶硅,121、241第二接触点。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白,下面结合实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅用以解释本发明,并不用于限定本发明。
参见图3-4,依据本发明的屏蔽结构200总体包含多晶硅栅210、STI区220以及电连接多晶硅栅210和STI区220的导电金属230。其中多晶硅栅210上设置有用于连接导电金属230一端的第一接触点211,STI区220内包含多晶硅240,并在该多晶硅240设置有用于连接导电金属230另一端的第二接触点241。优选地,多晶硅240可沉积于STI区220内填充的氧化物上。
第一接触点211可以包含蚀刻于多晶硅栅210上的第一接触孔和填充于第一接触孔内的导电材料。同样地,第二接触点241可以包含蚀刻于多晶硅240上的第二接触孔以及可填充于第二接触孔内的导电材料。作为选择地,第一接触点211和第二接触点241还可以具有能够将多晶硅栅210和多晶硅240电连接至导电金属230的其他结构。
依据本发明的屏蔽结构200的制备方法如图5所示,其可以包含以下步骤:
步骤1:在多晶硅栅210上设置第一接触点211,具体地,可在多晶硅栅210上蚀刻出第一接触孔并在第一接触孔内填充导电材料;
步骤2:在STI区220内沉积多晶硅240,并在多晶硅240上设置第二接触点241,具体地,可先在STI区220内填充氧化物,并将多晶硅240沉积于氧化物上,然后在多晶硅240上蚀刻出第二接触孔并在第二接触孔内填充导电材料以形成第二接触点241;
步骤3:使用导电金属230将第一接触点211和第二接触点241电连接。
本发明通过STI区内填充一层氧化物后在沉积一层多晶硅,并将接触点设置于多晶硅上,利用多晶硅与STI区内氧化物蚀刻的选择比不同的原理——即对多晶硅进行蚀刻所使用的试剂不会和氧化物发生反应,使得蚀刻深度至多到达多晶硅与氧化物接触面而不会继续加深,确保蚀刻时接触点可停留在多晶硅上,由此多晶硅的深度决定接触点位于STI内的深度,从而保接触点在STI内具有稳定的深度。
以上实施例仅表达了本发明的实施方式,其描述较为具体和详细,但并不能因此而理解为对本发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。
Claims (9)
1.一种用于LDMOS的屏蔽接触结构,其特征在于,包含设置于多晶硅栅上的第一接触点、设置于STI区内的第二接触点和连接所述第一接触点和所述第二接触点的导电金属,其特征在于,所述第二接触点设置于所述STI区内的多晶硅上。
2.根据权利要求1所述的屏蔽接触结构,其特征在于,所述STI区内填充有氧化物,所述多晶硅沉积于所述氧化物上。
3.根据权利要求1所述的屏蔽接触结构,其特征在于,所述第一接触点包含蚀刻于所述多晶硅栅上的第一接触孔和填充于所述第一接触孔内的导电材料。
4.根据权利要求1所述的屏蔽接触结构,其特征在于,所述第二接触点包含蚀刻于所述多晶硅上的第二接触孔和填充于所述第二接触孔内的导电材料。
5.一种LDMOS器件,其特征在于,包含上述权利要求任一项所述的屏蔽接触结构。
6.一种用于LDMOS的屏蔽接触结构的制备方法,其特征在于,包含以下步骤:
步骤1:在多晶硅栅上设置第一接触点;
步骤2:在STI区内沉积多晶硅,并在所述多晶硅上设置第二接触点;
步骤3:使用导电金属将所述第一接触点和所述第二接触点电连接。
7.根据权利要求6所述的制备方法,其特征在于,所述步骤2包含在STI区内填充有氧化物,并将所述多晶硅沉积于所述氧化物上。
8.根据权利要求6所述的制备方法,其特征在于,所述步骤1包含在所述多晶硅栅上蚀刻出第一接触孔以及在所述第一接触孔内填充导电材料。
9.根据权利要求6所述的制备方法,其特征在于,所述步骤2包含在所述多晶硅上蚀刻出第二接触孔以及在所述第二接触孔内填充导电材料。
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Citations (5)
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US20130277742A1 (en) * | 2012-04-24 | 2013-10-24 | United Microelectronics Corp. | Semiconductor structure and method for manufacturing the same |
US20140061791A1 (en) * | 2012-08-28 | 2014-03-06 | United Microelectronics Corp. | Mos transistor |
JP2019106554A (ja) * | 2019-04-02 | 2019-06-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN110323279A (zh) * | 2018-03-29 | 2019-10-11 | 拉碧斯半导体株式会社 | 半导体装置 |
CN110323138A (zh) * | 2019-06-20 | 2019-10-11 | 上海华虹宏力半导体制造有限公司 | 一种ldmos器件的制造方法 |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US20130277742A1 (en) * | 2012-04-24 | 2013-10-24 | United Microelectronics Corp. | Semiconductor structure and method for manufacturing the same |
US20140061791A1 (en) * | 2012-08-28 | 2014-03-06 | United Microelectronics Corp. | Mos transistor |
CN110323279A (zh) * | 2018-03-29 | 2019-10-11 | 拉碧斯半导体株式会社 | 半导体装置 |
JP2019106554A (ja) * | 2019-04-02 | 2019-06-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN110323138A (zh) * | 2019-06-20 | 2019-10-11 | 上海华虹宏力半导体制造有限公司 | 一种ldmos器件的制造方法 |
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