JP2008521213A5 - - Google Patents

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Publication number
JP2008521213A5
JP2008521213A5 JP2007540633A JP2007540633A JP2008521213A5 JP 2008521213 A5 JP2008521213 A5 JP 2008521213A5 JP 2007540633 A JP2007540633 A JP 2007540633A JP 2007540633 A JP2007540633 A JP 2007540633A JP 2008521213 A5 JP2008521213 A5 JP 2008521213A5
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Japan
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chip
package
cavity
wafer
sub
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JP2007540633A
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Japanese (ja)
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JP2008521213A (ja
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Priority claimed from US10/990,252 external-priority patent/US7098070B2/en
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Publication of JP2008521213A publication Critical patent/JP2008521213A/ja
Publication of JP2008521213A5 publication Critical patent/JP2008521213A5/ja
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JP2007540633A 2004-11-16 2005-11-03 スルー・バイア接続を有する両面ｓｏｉウエハ・スケール・パッケージを作製するためのデバイスおよび方法 Pending JP2008521213A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/990,252 US7098070B2 (en) 2004-11-16 2004-11-16 Device and method for fabricating double-sided SOI wafer scale package with through via connections
PCT/EP2005/055734 WO2006053832A1 (en) 2004-11-16 2005-11-03 Device and method for fabricating double-sided soi wafer scale package with through via connections

Publications (2)

Publication Number Publication Date
JP2008521213A JP2008521213A (ja) 2008-06-19
JP2008521213A5 true JP2008521213A5 (enExample) 2008-09-18

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JP2007540633A Pending JP2008521213A (ja) 2004-11-16 2005-11-03 スルー・バイア接続を有する両面ｓｏｉウエハ・スケール・パッケージを作製するためのデバイスおよび方法

Country Status (7)

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US (3) US7098070B2 (enExample)
EP (1) EP1851797B1 (enExample)
JP (1) JP2008521213A (enExample)
CN (1) CN100481421C (enExample)
AT (1) ATE548756T1 (enExample)
TW (1) TWI351727B (enExample)
WO (1) WO2006053832A1 (enExample)

Families Citing this family (202)

* Cited by examiner, † Cited by third party
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