JP2008521213A - スルー・バイア接続を有する両面ｓｏｉウエハ・スケール・パッケージを作製するためのデバイスおよび方法 - Google Patents

スルー・バイア接続を有する両面ｓｏｉウエハ・スケール・パッケージを作製するためのデバイスおよび方法 Download PDF

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JP2008521213A
JP2008521213A JP2007540633A JP2007540633A JP2008521213A JP 2008521213 A JP2008521213 A JP 2008521213A JP 2007540633 A JP2007540633 A JP 2007540633A JP 2007540633 A JP2007540633 A JP 2007540633A JP 2008521213 A JP2008521213 A JP 2008521213A
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chip
package
wafer
cavity
sub
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JP2008521213A5 (enExample
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チェン、ホワード、ハオ
スー、ルイス、ルーチェン
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International Business Machines Corp
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International Business Machines Corp
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Led Device Packages (AREA)
JP2007540633A 2004-11-16 2005-11-03 スルー・バイア接続を有する両面ｓｏｉウエハ・スケール・パッケージを作製するためのデバイスおよび方法 Pending JP2008521213A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/990,252 US7098070B2 (en) 2004-11-16 2004-11-16 Device and method for fabricating double-sided SOI wafer scale package with through via connections
PCT/EP2005/055734 WO2006053832A1 (en) 2004-11-16 2005-11-03 Device and method for fabricating double-sided soi wafer scale package with through via connections

Publications (2)

Publication Number Publication Date
JP2008521213A true JP2008521213A (ja) 2008-06-19
JP2008521213A5 JP2008521213A5 (enExample) 2008-09-18

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JP2007540633A Pending JP2008521213A (ja) 2004-11-16 2005-11-03 スルー・バイア接続を有する両面ｓｏｉウエハ・スケール・パッケージを作製するためのデバイスおよび方法

Country Status (7)

Country Link
US (3) US7098070B2 (enExample)
EP (1) EP1851797B1 (enExample)
JP (1) JP2008521213A (enExample)
CN (1) CN100481421C (enExample)
AT (1) ATE548756T1 (enExample)
TW (1) TWI351727B (enExample)
WO (1) WO2006053832A1 (enExample)

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JP2007067215A (ja) * 2005-08-31 2007-03-15 Sanyo Electric Co Ltd 回路基板、回路基板の製造方法および回路装置
JP2013516060A (ja) * 2009-12-24 2013-05-09 アイメック 窓介在型ダイパッケージング
KR20180030391A (ko) * 2016-09-14 2018-03-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 더미 커넥터를 구비한 반도체 패키지와 이를 형성하는 방법
WO2021240982A1 (ja) * 2020-05-25 2021-12-02 ソニーセミコンダクタソリューションズ株式会社 半導体装置とその製造方法、及び電子機器

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WO2007000695A2 (en) * 2005-06-29 2007-01-04 Koninklijke Philips Electronics N.V. Package, subassembly and methods of manufacturing thereof
JP4507101B2 (ja) 2005-06-30 2010-07-21 エルピーダメモリ株式会社 半導体記憶装置及びその製造方法
US20070126085A1 (en) * 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
EP1881527A1 (en) * 2006-07-17 2008-01-23 STMicroelectronics S.r.l. Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured
JP5107539B2 (ja) * 2006-08-03 2012-12-26 新光電気工業株式会社 半導体装置および半導体装置の製造方法
US7545029B2 (en) * 2006-08-18 2009-06-09 Tessera, Inc. Stack microelectronic assemblies
JP2008066481A (ja) * 2006-09-06 2008-03-21 Shinko Electric Ind Co Ltd パッケージ、半導体装置、パッケージの製造方法及び半導体装置の製造方法
US7589009B1 (en) * 2006-10-02 2009-09-15 Newport Fab, Llc Method for fabricating a top conductive layer in a semiconductor die and related structure
SE533579C2 (sv) * 2007-01-25 2010-10-26 Silex Microsystems Ab Metod för mikrokapsling och mikrokapslar
JP2009071095A (ja) * 2007-09-14 2009-04-02 Spansion Llc 半導体装置の製造方法
TWI355068B (en) * 2008-02-18 2011-12-21 Cyntec Co Ltd Electronic package structure
US8824165B2 (en) 2008-02-18 2014-09-02 Cyntec Co. Ltd Electronic package structure
US9001527B2 (en) * 2008-02-18 2015-04-07 Cyntec Co., Ltd. Electronic package structure
US8247267B2 (en) 2008-03-11 2012-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level IC assembly method
US8044755B2 (en) * 2008-04-09 2011-10-25 National Semiconductor Corporation MEMS power inductor
US7705411B2 (en) * 2008-04-09 2010-04-27 National Semiconductor Corporation MEMS-topped integrated circuit with a stress relief layer
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US7098070B2 (en) 2006-08-29
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US20060105496A1 (en) 2006-05-18
US20060113598A1 (en) 2006-06-01
US7736949B2 (en) 2010-06-15
ATE548756T1 (de) 2012-03-15
TW200634946A (en) 2006-10-01

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