WO2006053832A1 - Device and method for fabricating double-sided soi wafer scale package with through via connections - Google Patents

Device and method for fabricating double-sided soi wafer scale package with through via connections Download PDF

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Publication number
WO2006053832A1
WO2006053832A1 PCT/EP2005/055734 EP2005055734W WO2006053832A1 WO 2006053832 A1 WO2006053832 A1 WO 2006053832A1 EP 2005055734 W EP2005055734 W EP 2005055734W WO 2006053832 A1 WO2006053832 A1 WO 2006053832A1
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WO
WIPO (PCT)
Prior art keywords
chip
recited
package
wafer
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2005/055734
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English (en)
French (fr)
Inventor
Howard Hao Chen
Louis Lu-Chen Hsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IBM United Kingdom Ltd
International Business Machines Corp
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IBM United Kingdom Ltd
International Business Machines Corp
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Application filed by IBM United Kingdom Ltd, International Business Machines Corp filed Critical IBM United Kingdom Ltd
Priority to JP2007540633A priority Critical patent/JP2008521213A/ja
Priority to EP05807945A priority patent/EP1851797B1/en
Priority to AT05807945T priority patent/ATE548756T1/de
Publication of WO2006053832A1 publication Critical patent/WO2006053832A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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Definitions

  • the present invention relates to semiconductor processing and devices, and more particularly to devices and methods, which employ silicon-on-insulator (SOI) technology to provide a double-sided chip structure.
  • SOI silicon-on-insulator
  • CMOS complementary metal-oxide-semiconductor
  • SoP package
  • NVRAM non-volatile random access memory
  • DRAM dynamic random access memory
  • GaAs Gallium Arsenide
  • An efficient method to integrate different chips on a two-dimensional (2-D) or three-dimension (3-D) package can not only enhance circuit performance but also reduce manufacturing cost. If the chips are stacked vertically, the through vias should also be used to further reduce the interconnect delay and maximize circuit performance.
  • each SOI chip includes a handler making mechanical contact to a first metallization pattern, the first metallization pattern making electrical contact to a semiconductor device, and the semiconductor device making electrical contact to a second metallization pattern on the opposite surface of the semiconductor device.
  • a semiconductor device or package includes a wafer having a first side including an electronic component, and a second side, opposite the first side, forming a cavity.
  • a chip or component is placed in the cavity.
  • a through via connects the chip to the electronic component through a portion of the wafer.
  • FIG. 1 is a cross-sectional view of a silicon-on-insulator structure/wafer showing electronic components formed thereon;
  • FIG. 2 is a cross-sectional view showing through vias etched, dielectric liners formed and filled with a conductive material in accordance with one embodiment of the present invention
  • FIG. 3 is a cross-sectional view showing a protective coating formed on a first side of the wafer in accordance with the present invention
  • FIG. 4 is a cross-sectional view showing polishing/etching of a silicon substrate portion of the wafer in preparation for etching in accordance with the present invention
  • FIG. 5 is a cross-sectional view showing silicon substrate (backside) photolithography patterning in accordance with the present invention
  • FIG. 6 is a cross-sectional view showing backside etching to form a cavity in accordance with the present invention
  • FIG. 7 is a cross-sectional view showing pockets opened around through vias within the cavity in accordance with the present invention.
  • FIG. 8 is a cross-sectional view showing selective deposition of solder on through vias in accordance with the present invention.
  • FIG. 9 is a cross-sectional view showing the placement of sub-chips into the backside cavity and aligning the sub-chips with the through vias in accordance with the present invention.
  • FIG. 10 is a cross-sectional view showing soldering and bonding of the sub-chips to the through vias to permit the sub-chips and components of the original to coact to perform a function in accordance with the present invention
  • FIG. 11 is a cross-sectional view showing a thermally conductive underfill and deposition of a thermally conductive layer in accordance with the present invention.
  • FIG. 12 is a cross-sectional view showing the protective coating being removed from the front side of the wafer in accordance with the present invention.
  • FIG. 13 is a cross-sectional view showing front side global interconnect formation and C4 formation in accordance with the present invention.
  • FIG. 14 is a cross-sectional view showing the formation of a backside heat sink in accordance with the present invention.
  • FIG. 15 is a perspective view showing a plurality of sub-chips placed and connected by through vias to a mother chip in accordance with one embodiment of the present invention.
  • FIG. 16 is a top schematic view of a mother chip with daughter (sub-chips) placed therein showing through via placement and function in accordance with one embodiment of the present invention.
  • the present invention provides a low-cost and high-yield double-sided wafer scale package preferably on a silicon-on-insulator (SOI) wafer.
  • a mother chip is formed on the front side of the SOI wafer with a fully or partially depleted body to achieve high performance.
  • a plurality of thinned daughter chips are then mounted inside the cavities on the backside of the SOI wafer, opposite the mother chip.
  • metal studs are fabricated to facilitate interconnection between the mother and daughter chips.
  • the present methods do not need the chips to be transferred from a temporary carrier to a permanent carrier, which reduces the cost. Accordingly, by employing through via connections and cavity formation, sub-chips (daughter chips) can be directly diced out of a wafer and mounted on the backside of the mother chip. The method further avoids the use of vertical stacking in a 3-D package to facilitate heat dissipation. In addition, multiple chips manufactured in different technologies can be integrated on the same package.
  • the double-sided package protocol adopts two-dimensional chip packaging schemes on both sides of the wafer.
  • mother chips such as central processing units and serializer/deserializer (SerDes) chips are fabricated.
  • SerDes serializer/deserializer
  • the performance of these chips is boosted by the floating body effect as well as low junction capacitance.
  • the floating body effect is an inherent characteristic of SOI MOSFETs. Since the potential of the body is not fixed, the holes that are injected into the body cause the potential in the body to rise, resulting in lower threshold voltage, higher drain current and faster gate.
  • the buried oxide layer also eliminates the area junction capacitance between the source/drain diffusion and the substrate, which allows the transistor to operate faster with less capacitance to charge and discharge. With secondary components placed on the backside of the wafer, the mother chips will have smaller dimensions and higher yield than equivalent system-on-chip (SoC) designs.
  • the remaining area on the front side of the SOI wafer can be used to form decoupling capacitors and other discrete devices.
  • the backside of the SOI wafer may have thicker material that can be thinned down before etching to form the cavities for the daughter chips.
  • the daughter chips that can be embedded in the cavities may include high-speed radio frequency (RF) input/output (I/O) chips, memory chips such as non-volatile random access memory (NVRAM) , magnetic RAM (MRAM) , ferroelectric RAM (FRAM) , and embedded dynamic RAM (eDRAM) whose deep trench capacitor process is not fully compatible with conventional CMOS processes, decoupling capacitors, high-Q semiconductor inductors, and micro-electromechanical systems (MEMS) .
  • RF radio frequency
  • NVRAM non-volatile random access memory
  • MRAM magnetic RAM
  • FRAM ferroelectric RAM
  • eDRAM embedded dynamic RAM
  • the present invention may form deep vias from the pads of the mother chips on the front side of the SOI wafer, through the buried oxide layer, to the pads of the daughter chips on the backside of the SOI wafer.
  • These through vias not only provide the power supplies, signals and controls, but also enable the communication, testing, and monitoring of the mother and daughter chips.
  • To fabricate the through vias no devices or interconnects should be formed underneath the designated pads of the mother chip. Since the total thickness of the top silicon layer and the buried oxide layer is within a few hundred microns, the size of these through vias can be much smaller than a traditional multi-chip package.
  • FIG. 1 a silicon-on-insulator (SOI) wafer 10 with a top silicon layer 43, a buried dielectric (e.g., oxide) layer 42, and a bottom substrate 40 (e.g., silicon) are illustratively shown.
  • An integrated circuit system 11 includes active devices 44, metal interconnects 45, and discrete devices
  • the buried oxide layer 42 on SOI wafer 10 may include a thickness of say, 5 micrometers or less.
  • trenches 50 may be formed.
  • high-density plasma reactive ion etching RIE
  • RIE plasma reactive ion etching
  • Through vias 51 are formed through a top silicon layer 43 after lithographic patterning, etching, sidewall dielectric coating 52, and metal or conductive filling 53.
  • the ratio of via depth to via size may range from between about 1 to about 5.
  • BEOL back end of line
  • CF 4 , Cl 2 and/or CF 4 based plasma etching may be employed successively, with a proper end-point detection method. Such detection methods are known in the art.
  • vias 51 are extended below the buried oxide layer 42, it may be necessary to over-etch the buried oxide layer 42.
  • Insulating materials 52 such as the oxide/nitride sidewall spacers, are preferably employed to prevent the vias 51 from being shorted to any adjacent conductive layers, well regions, or the substrate layer.
  • the vias 51 can then be filled with conductive metal 53, such as copper, tungsten, aluminum, doped polycrystalline material, alloys and/or any other conductive material.
  • a conformal chemical vapor deposition (CVD) deep-etch technique can be used to eliminate any void formation inside the vias 51 during the filling process.
  • a layer of protective coating 60 such as oxide, nitride, oxy-nitride, or glass is formed on a top surface of the wafer 10 to protect it from being damaged during the backside processing.
  • Other materials or protection schemes may also be employed.
  • the silicon substrate 40 on the backside of the wafer is thinned, by for example, chemical-mechanical polishing (CMP) or high-density plasma etching (e.g., RIE) to a proper thickness "d". It is preferable that "d" may be a few microns thicker than the thickest chip to be mounted on the backside.
  • CMP chemical-mechanical polishing
  • RIE high-density plasma etching
  • a photolithography pattern 64 is generated by applying a photoresist 66 and patterning the resist 66 using known methods. Resist 66 is then employed as a mask in an etching process to form a backside cavity or cavities 68.
  • the size of the cavity 68 should be slightly larger than the chip to be mounted inside (below the open surface) and margins should be provided in case of misalignment. Multiple chips may be placed inside the same cavity 68.
  • the cavities 68 are formed after etching and the conductive material 53 of through vias 51 is exposed at the surface of the buried oxide layer 42.
  • the resist 66 is removed from substrate 40.
  • an extra etching step may be employed to open a pocket 70 on top of each via 51 by thin photoresist patterning and exposure at the surface of the buried oxide 42.
  • the pocket 70 formation is preferable during the ensuing bonding and soldering reflow steps, to provide the space for solder to flow and thus form better contacts .
  • solder balls 74 may be employed to form solder balls 74 on exposed studs 53 in vias 51 and inside the pockets 70.
  • the process selectively forms metal on studs 53.
  • Low melting-temperature material is preferable in forming the solder balls 74.
  • Solder balls 74 may include tin or lead alloys and may employ a process similar to a controlled collapse chip connection (C4) bonding method.
  • chips (sub-chips) 80 and 82 are illustratively shown making contact with studs 53 of vias 51.
  • Chips 80 and 82 may include thinned chips (referred to earlier as daughter chips) , which are flipped upside down, placed inside the cavity 68, and bonded to the mother chip (wafer 10) .
  • the depth (d) of the cavities 68 is preferably deeper than the thickness of all the daughter chips (80 and 82) .
  • Chips 80 and 82 may be formed in a separate processing step and may themselves include a cavity therein with even smaller sub-chips connected thereto in accordance with the present invention.
  • Chips 80 and 82 may be placed in cavity 68 having gaps 84 therebetween and between walls 86 and chips 80 and 82. Alternately, chips 80 and 82 may include spacers or layers of material to ensure a proper fit and automatically align studs 53 with contacts 88 and 90 of each chip 80 and 82. These chips 80 and 82 may also be aligned using tooling or other gapping methods. In one embodiment, chips 80 and 82 are connected or attached to one another prior to placing them into cavity 68.
  • a bonding process may include a temperature of about 400 0 C to be carried out to join solder balls for contacts 88 and 90 of the daughter chips 80 and 82 with the solder balls 74 for through vias 51 for the mother chip 10.
  • an under-fill process is employed to fill the gaps 84 and 86 and any other locations between chips 80 and 82 and wafer 10 with a thermally conductive agent 98, such as a thermal paste, or standard filling polymer or other fillers. It is preferred that the agent 98 be thermally conductive to promote heat dissipation, but act as an electrical insulator.
  • the top surface of the cavity 68 may further be filled with a more thermally conductive material 102 such as, for example, chemical vapor deposited (CVD) diamond.
  • a metal film 104 may also be formed on the backside of wafer 10 to seal the daughter chips inside the cavities 68.
  • the top protective layer 60 of a mother chip 120 (on wafer 10) can be stripped. This may be in preparation for further processing on the system such as global or local interconnects and vias, attaching other components or forming additional layers or features, etc.
  • more metal layers 106, contact pads 108, and C4 balls 110 can be formed on the front side of the wafer 10 of mother chip 120. Further processing may be performed to form additional structures or to provide packaging for system 100.
  • a final double-side chip assembly 100 can be cut from the wafer 10 (e.g., dicing the wafer to form chip packages), where each assembly has a mother chip 120 on the front side and a plurality of daughter chips (e.g., 80 and 82) mounted on the backside.
  • the buried oxide layer 42 of the SOI wafer 10 is used as the holding plate for through via interconnection between the mother chip 120 and daughter chips 80 and 82.
  • a heat sink 111 can be mounted on the backside of the chip as illustratively shown in FIG. 14.
  • Heat sink 111 may be attached, e.g., using a thermal adhesive material, or may be formed be depositing materials and etching the material into a predetermined shape (e.g., fins and troughs) .
  • a SOI wafer scale package 200 includes one mother chip 202, such as a processor (or memory device or combination thereof) formed on a top silicon layer (e.g., 43 of FIG. 1) to achieve high performance, and several daughter chips 204, 206, 208, 210 and 212. These chips may include for example, SRAM cache, eDRAM, NVRAM, FPGA, and high-speed RF interface chips mounted on the backside of the assembly 200. Through via connections 251 are illustratively shown in one area between the mother chip 202 and daughter chips 204-212. Vias and the chip placement and alignment need to be performed after appropriate planning.
  • mother and daughter chips be co-designed for the package 200 to ensure coaction, proper alignment/placement and proper functioning.
  • a package 300 where the mother chip 302 includes 3 macros Ml, M2, and M3 (sub-chips) .
  • Package 300 indicates aspects to be considered during co-design of mother and daughter chips in a system.
  • through via connections 351 are only permitted in the empty space between the adjacent macros (Ml, M2, M3) and edges of the mother chips' substrate 340.
  • Through vias 351 may be designated for different tasks, such as carrying power Vdd, or Vss or signals (Signal) as illustratively indicated in FIG. 16.
  • motherchip 302 may be comprised of multiple chips Cl, C2, C3 and C4 and connected using macros, structures or subchips.

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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PCT/EP2005/055734 2004-11-16 2005-11-03 Device and method for fabricating double-sided soi wafer scale package with through via connections Ceased WO2006053832A1 (en)

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EP05807945A EP1851797B1 (en) 2004-11-16 2005-11-03 Device and method for fabricating double-sided soi wafer scale package with through via connections
AT05807945T ATE548756T1 (de) 2004-11-16 2005-11-03 Einrichtung und verfahren zur herstellung einer doppelseitigen kapselung auf soi-wafermassstab mit durchkontaktierungen

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