TWI351727B - Device and method for fabricating double-sided soi - Google Patents

Device and method for fabricating double-sided soi Download PDF

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Publication number
TWI351727B
TWI351727B TW094139868A TW94139868A TWI351727B TW I351727 B TWI351727 B TW I351727B TW 094139868 A TW094139868 A TW 094139868A TW 94139868 A TW94139868 A TW 94139868A TW I351727 B TWI351727 B TW I351727B
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Taiwan
Prior art keywords
wafer
package
layer
sub
chamber
Prior art date
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TW094139868A
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English (en)
Chinese (zh)
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TW200634946A (en
Inventor
Howard Hao Chen
Louis Lu-Chen Hsu
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Ibm
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Publication of TW200634946A publication Critical patent/TW200634946A/zh
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Publication of TWI351727B publication Critical patent/TWI351727B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0652—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
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    • H01L2224/06181—On opposite sides of the body
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    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Led Device Packages (AREA)
TW094139868A 2004-11-16 2005-11-14 Device and method for fabricating double-sided soi TWI351727B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/990,252 US7098070B2 (en) 2004-11-16 2004-11-16 Device and method for fabricating double-sided SOI wafer scale package with through via connections

Publications (2)

Publication Number Publication Date
TW200634946A TW200634946A (en) 2006-10-01
TWI351727B true TWI351727B (en) 2011-11-01

Family

ID=35677682

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094139868A TWI351727B (en) 2004-11-16 2005-11-14 Device and method for fabricating double-sided soi

Country Status (7)

Country Link
US (3) US7098070B2 (enExample)
EP (1) EP1851797B1 (enExample)
JP (1) JP2008521213A (enExample)
CN (1) CN100481421C (enExample)
AT (1) ATE548756T1 (enExample)
TW (1) TWI351727B (enExample)
WO (1) WO2006053832A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI834089B (zh) * 2021-07-20 2024-03-01 大陸商安徽寒武紀信息科技有限公司 一種系統整合單晶片、生成方法與可讀存儲介質

Families Citing this family (201)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
US6297548B1 (en) 1998-06-30 2001-10-02 Micron Technology, Inc. Stackable ceramic FBGA for high thermal applications
WO2004015764A2 (en) 2002-08-08 2004-02-19 Leedy Glenn J Vertical system integration
WO2007000695A2 (en) * 2005-06-29 2007-01-04 Koninklijke Philips Electronics N.V. Package, subassembly and methods of manufacturing thereof
JP4507101B2 (ja) 2005-06-30 2010-07-21 エルピーダメモリ株式会社 半導体記憶装置及びその製造方法
JP4979213B2 (ja) * 2005-08-31 2012-07-18 オンセミコンダクター・トレーディング・リミテッド 回路基板、回路基板の製造方法および回路装置
US20070126085A1 (en) * 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
EP1881527A1 (en) * 2006-07-17 2008-01-23 STMicroelectronics S.r.l. Process for manufacturing a semiconductor wafer having SOI-insulated wells and semiconductor wafer thereby manufactured
JP5107539B2 (ja) * 2006-08-03 2012-12-26 新光電気工業株式会社 半導体装置および半導体装置の製造方法
US7545029B2 (en) * 2006-08-18 2009-06-09 Tessera, Inc. Stack microelectronic assemblies
JP2008066481A (ja) * 2006-09-06 2008-03-21 Shinko Electric Ind Co Ltd パッケージ、半導体装置、パッケージの製造方法及び半導体装置の製造方法
US7589009B1 (en) * 2006-10-02 2009-09-15 Newport Fab, Llc Method for fabricating a top conductive layer in a semiconductor die and related structure
SE533579C2 (sv) * 2007-01-25 2010-10-26 Silex Microsystems Ab Metod för mikrokapsling och mikrokapslar
JP2009071095A (ja) * 2007-09-14 2009-04-02 Spansion Llc 半導体装置の製造方法
TWI355068B (en) * 2008-02-18 2011-12-21 Cyntec Co Ltd Electronic package structure
US8824165B2 (en) 2008-02-18 2014-09-02 Cyntec Co. Ltd Electronic package structure
US9001527B2 (en) * 2008-02-18 2015-04-07 Cyntec Co., Ltd. Electronic package structure
US8247267B2 (en) 2008-03-11 2012-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level IC assembly method
US8044755B2 (en) * 2008-04-09 2011-10-25 National Semiconductor Corporation MEMS power inductor
US7705411B2 (en) * 2008-04-09 2010-04-27 National Semiconductor Corporation MEMS-topped integrated circuit with a stress relief layer
US20090261416A1 (en) * 2008-04-18 2009-10-22 Wolfgang Raberg Integrated mems device and control circuit
SG142321A1 (en) 2008-04-24 2009-11-26 Micron Technology Inc Pre-encapsulated cavity interposer
US20110073357A1 (en) * 2008-06-02 2011-03-31 Nxp B.V. Electronic device and method of manufacturing an electronic device
US20090305463A1 (en) * 2008-06-06 2009-12-10 International Business Machines Corporation System and Method for Thermal Optimized Chip Stacking
US7885494B2 (en) * 2008-07-02 2011-02-08 Sony Ericsson Mobile Communications Ab Optical signaling for a package-on-package stack
US8005326B2 (en) * 2008-07-10 2011-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Optical clock signal distribution using through-silicon vias
US8637953B2 (en) * 2008-07-14 2014-01-28 International Business Machines Corporation Wafer scale membrane for three-dimensional integrated circuit device fabrication
US8138036B2 (en) * 2008-08-08 2012-03-20 International Business Machines Corporation Through silicon via and method of fabricating same
US8384224B2 (en) 2008-08-08 2013-02-26 International Business Machines Corporation Through wafer vias and method of making same
US8299566B2 (en) 2008-08-08 2012-10-30 International Business Machines Corporation Through wafer vias and method of making same
US8035198B2 (en) * 2008-08-08 2011-10-11 International Business Machines Corporation Through wafer via and method of making same
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
US7851925B2 (en) 2008-09-19 2010-12-14 Infineon Technologies Ag Wafer level packaged MEMS integrated circuit
US8987868B1 (en) * 2009-02-24 2015-03-24 Xilinx, Inc. Method and apparatus for programmable heterogeneous integration of stacked semiconductor die
JP2010287866A (ja) * 2009-06-15 2010-12-24 Renesas Electronics Corp 半導体装置
WO2011017202A2 (en) 2009-08-06 2011-02-10 Rambus Inc. Packaged semiconductor device for high performance memory and logic
US8063424B2 (en) * 2009-11-16 2011-11-22 International Business Machines Corporation Embedded photodetector apparatus in a 3D CMOS chip stack
US8119431B2 (en) * 2009-12-08 2012-02-21 Freescale Semiconductor, Inc. Method of forming a micro-electromechanical system (MEMS) having a gap stop
EP2339627A1 (en) * 2009-12-24 2011-06-29 Imec Window interposed die packaging
US8901724B2 (en) * 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US9219023B2 (en) * 2010-01-19 2015-12-22 Globalfoundries Inc. 3D chip stack having encapsulated chip-in-chip
US9015023B2 (en) 2010-05-05 2015-04-21 Xilinx, Inc. Device specific configuration of operating voltage
US9484279B2 (en) * 2010-06-02 2016-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming EMI shielding layer with conductive material around semiconductor die
US8399292B2 (en) 2010-06-30 2013-03-19 International Business Machines Corporation Fabricating a semiconductor chip with backside optical vias
US8598695B2 (en) 2010-07-23 2013-12-03 Tessera, Inc. Active chip on carrier or laminated chip having microelectronic element embedded therein
WO2012024500A1 (en) * 2010-08-18 2012-02-23 Life Technologies Corporation Chemical coating of microwell for electrochemical detection device
US8518746B2 (en) 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
CN101976660B (zh) * 2010-09-10 2015-04-15 上海华虹宏力半导体制造有限公司 具有散热结构的绝缘体上硅衬底硅片及其制成方法
US8470612B2 (en) 2010-10-07 2013-06-25 Infineon Technologies Ag Integrated circuits with magnetic core inductors and methods of fabrications thereof
US9337116B2 (en) 2010-10-28 2016-05-10 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die
TWI453864B (zh) * 2010-11-12 2014-09-21 財團法人工業技術研究院 半導體結構及其製作方法
DE102010056056A1 (de) * 2010-12-23 2012-06-28 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines elektrischen Anschlussträgers
US9024408B2 (en) * 2010-12-29 2015-05-05 Stmicroelectronics, Inc. Double side wafer process, method and device
KR101761834B1 (ko) * 2011-01-28 2017-07-27 서울바이오시스 주식회사 웨이퍼 레벨 발광 다이오드 패키지 및 그것을 제조하는 방법
CN102163590A (zh) * 2011-03-09 2011-08-24 中国科学院上海微系统与信息技术研究所 基于埋置式基板的三维多芯片封装模块及方法
FR2973943B1 (fr) * 2011-04-08 2013-04-05 Soitec Silicon On Insulator Procédés de formation de structures semi-conductrices collées comprenant deux structures semi-conductrices traitées ou plus supportées par un substrat commun, et structures semi-conductrices formées par ces procédés
US8970045B2 (en) * 2011-03-31 2015-03-03 Soitec Methods for fabrication of semiconductor structures including interposers with conductive vias, and related structures and devices
US20120248621A1 (en) * 2011-03-31 2012-10-04 S.O.I.Tec Silicon On Insulator Technologies Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods
US8338294B2 (en) 2011-03-31 2012-12-25 Soitec Methods of forming bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods
USD673921S1 (en) * 2011-04-21 2013-01-08 Kabushiki Kaisha Toshiba Portion of a substrate for an electronic circuit
USD673922S1 (en) * 2011-04-21 2013-01-08 Kabushiki Kaisha Toshiba Portion of a substrate for an electronic circuit
US8803269B2 (en) * 2011-05-05 2014-08-12 Cisco Technology, Inc. Wafer scale packaging platform for transceivers
US8481425B2 (en) 2011-05-16 2013-07-09 United Microelectronics Corp. Method for fabricating through-silicon via structure
US8822336B2 (en) 2011-06-16 2014-09-02 United Microelectronics Corp. Through-silicon via forming method
US8828745B2 (en) 2011-07-06 2014-09-09 United Microelectronics Corp. Method for manufacturing through-silicon via
US8497558B2 (en) * 2011-07-14 2013-07-30 Infineon Technologies Ag System and method for wafer level packaging
US8518823B2 (en) 2011-12-23 2013-08-27 United Microelectronics Corp. Through silicon via and method of forming the same
US8609529B2 (en) 2012-02-01 2013-12-17 United Microelectronics Corp. Fabrication method and structure of through silicon via
TWI573203B (zh) * 2012-02-16 2017-03-01 索泰克公司 製作包含有具導電貫孔間置結構之半導體構造之方法及其相關構造與元件
US8691600B2 (en) 2012-05-02 2014-04-08 United Microelectronics Corp. Method for testing through-silicon-via (TSV) structures
US8691688B2 (en) 2012-06-18 2014-04-08 United Microelectronics Corp. Method of manufacturing semiconductor structure
US9275933B2 (en) 2012-06-19 2016-03-01 United Microelectronics Corp. Semiconductor device
US8900996B2 (en) 2012-06-21 2014-12-02 United Microelectronics Corp. Through silicon via structure and method of fabricating the same
US8525296B1 (en) 2012-06-26 2013-09-03 United Microelectronics Corp. Capacitor structure and method of forming the same
US8716856B2 (en) * 2012-08-02 2014-05-06 Globalfoundries Singapore Pte. Ltd. Device with integrated power supply
US10094988B2 (en) * 2012-08-31 2018-10-09 Micron Technology, Inc. Method of forming photonics structures
US8912844B2 (en) 2012-10-09 2014-12-16 United Microelectronics Corp. Semiconductor structure and method for reducing noise therein
US9035457B2 (en) 2012-11-29 2015-05-19 United Microelectronics Corp. Substrate with integrated passive devices and method of manufacturing the same
KR102190382B1 (ko) 2012-12-20 2020-12-11 삼성전자주식회사 반도체 패키지
US8716104B1 (en) 2012-12-20 2014-05-06 United Microelectronics Corp. Method of fabricating isolation structure
US9209121B2 (en) 2013-02-01 2015-12-08 Analog Devices, Inc. Double-sided package
US9997443B2 (en) * 2013-02-25 2018-06-12 Infineon Technologies Ag Through vias and methods of formation thereof
US9583414B2 (en) 2013-10-31 2017-02-28 Qorvo Us, Inc. Silicon-on-plastic semiconductor device and method of making the same
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US9061890B2 (en) * 2013-03-13 2015-06-23 Intel Corporation Methods of forming buried electromechanical structures coupled with device substrates and structures formed thereby
KR102048251B1 (ko) * 2013-03-14 2019-11-25 삼성전자주식회사 메모리 칩 패키지, 그것을 포함하는 메모리 시스템, 그것의 구동 방법
US8884398B2 (en) 2013-04-01 2014-11-11 United Microelectronics Corp. Anti-fuse structure and programming method thereof
US9000490B2 (en) 2013-04-19 2015-04-07 Xilinx, Inc. Semiconductor package having IC dice and voltage tuners
US9287173B2 (en) 2013-05-23 2016-03-15 United Microelectronics Corp. Through silicon via and process thereof
US9123730B2 (en) 2013-07-11 2015-09-01 United Microelectronics Corp. Semiconductor device having through silicon trench shielding structure surrounding RF circuit
US9024416B2 (en) 2013-08-12 2015-05-05 United Microelectronics Corp. Semiconductor structure
US8916471B1 (en) 2013-08-26 2014-12-23 United Microelectronics Corp. Method for forming semiconductor structure having through silicon via for signal and shielding structure
US9048223B2 (en) 2013-09-03 2015-06-02 United Microelectronics Corp. Package structure having silicon through vias connected to ground potential
US9117804B2 (en) 2013-09-13 2015-08-25 United Microelectronics Corporation Interposer structure and manufacturing method thereof
TWI566395B (zh) * 2013-11-18 2017-01-11 元太科技工業股份有限公司 有機發光二極體顯示器及其製造方法
US9343359B2 (en) 2013-12-25 2016-05-17 United Microelectronics Corp. Integrated structure and method for fabricating the same
US10340203B2 (en) 2014-02-07 2019-07-02 United Microelectronics Corp. Semiconductor structure with through silicon via and method for fabricating and testing the same
US9412736B2 (en) 2014-06-05 2016-08-09 Globalfoundries Inc. Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias
WO2016003456A1 (en) * 2014-07-02 2016-01-07 Intel Corporation Electronic assembly that includes stacked electronic devices
US9731959B2 (en) 2014-09-25 2017-08-15 Analog Devices, Inc. Integrated device packages having a MEMS die sealed in a cavity by a processor die and method of manufacturing the same
CN104332455B (zh) * 2014-09-25 2017-03-08 武汉新芯集成电路制造有限公司 一种基于硅通孔的片上半导体器件结构及其制备方法
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US9236328B1 (en) * 2014-10-27 2016-01-12 International Business Machines Corporation Electrical and optical through-silicon-via (TSV)
US9530709B2 (en) 2014-11-03 2016-12-27 Qorvo Us, Inc. Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US9533878B2 (en) 2014-12-11 2017-01-03 Analog Devices, Inc. Low stress compact device packages
TWI719982B (zh) 2015-05-15 2021-03-01 美商西凱渥資訊處理科技公司 半導體裝置中之空腔形成
US10594355B2 (en) * 2015-06-30 2020-03-17 Skyworks Solutions, Inc. Devices and methods related to radio-frequency filters on silicon-on-insulator substrate
KR20170011366A (ko) * 2015-07-22 2017-02-02 삼성전자주식회사 반도체 칩 및 이를 가지는 반도체 패키지
US9786641B2 (en) * 2015-08-13 2017-10-10 International Business Machines Corporation Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics applications
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
US9859382B2 (en) 2015-12-04 2018-01-02 Globalfoundries Inc. Integrated CMOS wafers
US10256863B2 (en) * 2016-01-11 2019-04-09 Qualcomm Incorporated Monolithic integration of antenna switch and diplexer
US10090262B2 (en) 2016-05-09 2018-10-02 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10468329B2 (en) 2016-07-18 2019-11-05 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
CN109844938B (zh) 2016-08-12 2023-07-18 Qorvo美国公司 具有增强性能的晶片级封装
CN109844937B (zh) 2016-08-12 2023-06-27 Qorvo美国公司 具有增强性能的晶片级封装
JP7022112B2 (ja) 2016-08-12 2022-02-17 コーボ ユーエス，インコーポレイティド 性能を向上させたウェーハレベルパッケージ
US9837302B1 (en) * 2016-08-26 2017-12-05 Qualcomm Incorporated Methods of forming a device having semiconductor devices on two sides of a buried dielectric layer
US10020335B2 (en) 2016-09-09 2018-07-10 Omnivision Technologies, Inc. Short-resistant chip-scale package
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10276548B2 (en) * 2016-09-14 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages having dummy connectors and methods of forming same
US10090339B2 (en) 2016-10-21 2018-10-02 Qorvo Us, Inc. Radio frequency (RF) switch
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US20180151291A1 (en) * 2016-11-29 2018-05-31 Qualcomm Incorporated Inductor with embedded diode
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10468736B2 (en) 2017-02-08 2019-11-05 Aptiv Technologies Limited Radar assembly with ultra wide band waveguide to substrate integrated waveguide transition
CN110622628B (zh) * 2017-03-15 2021-10-26 香港物流及供应链管理应用技术研发中心 射频通信引导装置
US10490471B2 (en) 2017-07-06 2019-11-26 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10366972B2 (en) * 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10998273B2 (en) * 2017-12-22 2021-05-04 Hrl Laboratories, Llc Hybrid integrated circuit architecture
US11536800B2 (en) * 2017-12-22 2022-12-27 Hrl Laboratories, Llc Method and apparatus to increase radar range
US11527482B2 (en) * 2017-12-22 2022-12-13 Hrl Laboratories, Llc Hybrid integrated circuit architecture
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US12062700B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US12165951B2 (en) 2018-07-02 2024-12-10 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
WO2020029096A1 (zh) * 2018-08-07 2020-02-13 深圳市为通博科技有限责任公司 芯片封装结构及其制造方法
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
CN109496353B (zh) * 2018-10-15 2022-08-16 深圳市汇顶科技股份有限公司 具有薄膜晶体管器件的集成装置及其制备方法
US10957537B2 (en) 2018-11-12 2021-03-23 Hrl Laboratories, Llc Methods to design and uniformly co-fabricate small vias and large cavities through a substrate
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
CN111341750B (zh) 2018-12-19 2024-03-01 奥特斯奥地利科技与系统技术有限公司 包括有导电基部结构的部件承载件及制造方法
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
KR102771428B1 (ko) 2019-01-23 2025-02-26 코르보 유에스, 인크. Rf 반도체 디바이스 및 이를 형성하는 방법
US12125825B2 (en) 2019-01-23 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11473191B2 (en) * 2019-02-27 2022-10-18 Applied Materials, Inc. Method for creating a dielectric filled nanostructured silica substrate for flat optical devices
US11527808B2 (en) * 2019-04-29 2022-12-13 Aptiv Technologies Limited Waveguide launcher
JP7232137B2 (ja) * 2019-06-25 2023-03-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US11581289B2 (en) 2019-07-30 2023-02-14 Stmicroelectronics Pte Ltd Multi-chip package
US11264358B2 (en) 2019-09-11 2022-03-01 Google Llc ASIC package with photonics and vertical power delivery
US11296005B2 (en) 2019-09-24 2022-04-05 Analog Devices, Inc. Integrated device package including thermally conductive element and method of manufacturing same
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12129168B2 (en) 2019-12-23 2024-10-29 Qorvo Us, Inc. Microelectronics package with vertically stacked MEMS device and controller device
US11276668B2 (en) 2020-02-12 2022-03-15 Google Llc Backside integrated voltage regulator for integrated circuits
JP2021174955A (ja) * 2020-04-30 2021-11-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2021190440A (ja) * 2020-05-25 2021-12-13 ソニーセミコンダクタソリューションズ株式会社 半導体装置とその製造方法、及び電子機器
US11551993B2 (en) * 2020-08-28 2023-01-10 Ge Aviation Systems Llc Power overlay module and method of assembling
US11972970B1 (en) 2020-09-01 2024-04-30 Hrl Laboratories, Llc Singulation process for chiplets
US11362436B2 (en) 2020-10-02 2022-06-14 Aptiv Technologies Limited Plastic air-waveguide antenna with conductive particles
US11757166B2 (en) 2020-11-10 2023-09-12 Aptiv Technologies Limited Surface-mount waveguide for vertical transitions of a printed circuit board
US12178142B2 (en) 2020-11-13 2024-12-24 International Business Machines Corporation Layered substrate structures with aligned optical access to electrical devices
EP4260369A2 (en) 2020-12-11 2023-10-18 Qorvo US, Inc. Multi-level 3d stacked package and methods of forming the same
US11901601B2 (en) 2020-12-18 2024-02-13 Aptiv Technologies Limited Waveguide with a zigzag for suppressing grating lobes
US11626668B2 (en) 2020-12-18 2023-04-11 Aptiv Technologies Limited Waveguide end array antenna to reduce grating lobes and cross-polarization
US11749883B2 (en) 2020-12-18 2023-09-05 Aptiv Technologies Limited Waveguide with radiation slots and parasitic elements for asymmetrical coverage
US11681015B2 (en) 2020-12-18 2023-06-20 Aptiv Technologies Limited Waveguide with squint alteration
US11502420B2 (en) 2020-12-18 2022-11-15 Aptiv Technologies Limited Twin line fed dipole array antenna
US11444364B2 (en) 2020-12-22 2022-09-13 Aptiv Technologies Limited Folded waveguide for antenna
US11668787B2 (en) 2021-01-29 2023-06-06 Aptiv Technologies Limited Waveguide with lobe suppression
US12058804B2 (en) 2021-02-09 2024-08-06 Aptiv Technologies AG Formed waveguide antennas of a radar assembly
WO2022186857A1 (en) 2021-03-05 2022-09-09 Qorvo Us, Inc. Selective etching process for si-ge and doped epitaxial silicon
US11721905B2 (en) 2021-03-16 2023-08-08 Aptiv Technologies Limited Waveguide with a beam-forming feature with radiation slots
US11616306B2 (en) 2021-03-22 2023-03-28 Aptiv Technologies Limited Apparatus, method and system comprising an air waveguide antenna having a single layer material with air channels therein which is interfaced with a circuit board
EP4084222A1 (en) 2021-04-30 2022-11-02 Aptiv Technologies Limited Dielectric loaded waveguide for low loss signal distributions and small form factor antennas
US11973268B2 (en) 2021-05-03 2024-04-30 Aptiv Technologies AG Multi-layered air waveguide antenna with layer-to-layer connections
US11962085B2 (en) 2021-05-13 2024-04-16 Aptiv Technologies AG Two-part folded waveguide having a sinusoidal shape channel including horn shape radiating slots formed therein which are spaced apart by one-half wavelength
US11616282B2 (en) 2021-08-03 2023-03-28 Aptiv Technologies Limited Transition between a single-ended port and differential ports having stubs that match with input impedances of the single-ended and differential ports
CN113643739B (zh) * 2021-09-02 2025-02-07 西安紫光国芯半导体股份有限公司 一种llc芯片及缓存系统
US12224502B2 (en) 2021-10-14 2025-02-11 Aptiv Technologies AG Antenna-to-printed circuit board transition
US12463109B2 (en) * 2021-10-15 2025-11-04 Hrl Laboratories, Llc Thermal isolation between embedded MECA modules
US12315776B2 (en) 2021-11-08 2025-05-27 Analog Devices, Inc. Integrated device package with an integrated heat sink
CN114551592A (zh) * 2021-12-16 2022-05-27 深圳市汇芯通信技术有限公司 一种氮化镓集成电路芯片及其制备方法
US12205920B2 (en) * 2022-02-03 2025-01-21 Ciena Corporation Enhanced thermal control of a hybrid chip assembly
CN114464540B (zh) * 2022-02-11 2025-01-28 展讯通信（上海）有限公司 元器件封装方法及元器件封装结构
US20230260894A1 (en) * 2022-02-17 2023-08-17 Mediatek Inc. Semiconductor device with integrated deep trench capacitors
US12456816B2 (en) 2022-05-02 2025-10-28 Aptiv Technologies AG Waveguide with slot antennas and reflectors
US12265172B2 (en) 2022-05-25 2025-04-01 Aptiv Technologies AG Vertical microstrip-to-waveguide transition
US12315999B2 (en) 2022-07-15 2025-05-27 Aptiv Technologies AG Solderable waveguide antenna
US12424767B2 (en) 2022-11-15 2025-09-23 Aptiv Technologies AG Planar surface features for waveguide and antenna
US12148992B2 (en) 2023-01-25 2024-11-19 Aptiv Technologies AG Hybrid horn waveguide antenna

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0521539A (ja) * 1991-07-12 1993-01-29 Hitachi Ltd 半導体装置および計算機
JP2943950B2 (ja) * 1991-08-22 1999-08-30 本田技研工業株式会社 半導体装置と、その製造方法
JP2823029B2 (ja) * 1992-03-30 1998-11-11 日本電気株式会社 マルチチップモジュール
US5394490A (en) 1992-08-11 1995-02-28 Hitachi, Ltd. Semiconductor device having an optical waveguide interposed in the space between electrode members
US5786635A (en) * 1996-12-16 1998-07-28 International Business Machines Corporation Electronic package with compressible heatsink structure
JPH10186185A (ja) 1996-12-19 1998-07-14 Fuji Xerox Co Ltd 光バス、光バスの製造方法および信号処理装置
US6300686B1 (en) * 1997-10-02 2001-10-09 Matsushita Electric Industrial Co., Ltd. Semiconductor chip bonded to a thermal conductive sheet having a filled through hole for electrical connection
US6730541B2 (en) * 1997-11-20 2004-05-04 Texas Instruments Incorporated Wafer-scale assembly of chip-size packages
EP0926726A1 (en) * 1997-12-16 1999-06-30 STMicroelectronics S.r.l. Fabrication process and electronic device having front-back through contacts for bonding onto boards
DE19813239C1 (de) * 1998-03-26 1999-12-23 Fraunhofer Ges Forschung Verdrahtungsverfahren zur Herstellung einer vertikalen integrierten Schaltungsstruktur und vertikale integrierte Schaltungsstruktur
US6175160B1 (en) * 1999-01-08 2001-01-16 Intel Corporation Flip-chip having an on-chip cache memory
WO2000074134A1 (de) * 1999-05-27 2000-12-07 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur vertikalen integration von elektrischen bauelementen mittels rückseitenkontaktierung
JP4360577B2 (ja) * 2000-03-29 2009-11-11 京セラ株式会社 半導体装置
US6355501B1 (en) * 2000-09-21 2002-03-12 International Business Machines Corporation Three-dimensional chip stacking assembly
US6444560B1 (en) * 2000-09-26 2002-09-03 International Business Machines Corporation Process for making fine pitch connections between devices and structure made by the process
JP2002156561A (ja) * 2000-11-17 2002-05-31 Minolta Co Ltd 光集積モジュール
FR2817399B1 (fr) * 2000-11-30 2003-10-31 St Microelectronics Sa Puce electronique multifonctions
KR100394808B1 (ko) * 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US6787916B2 (en) * 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
US6888178B2 (en) * 2002-01-24 2005-05-03 Massachusetts Institute Of Technology Method and system for magnetically assisted statistical assembly of wafers
US6762076B2 (en) * 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6645832B2 (en) * 2002-02-20 2003-11-11 Intel Corporation Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack
JP2003282817A (ja) * 2002-03-27 2003-10-03 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
TWI231579B (en) * 2002-12-31 2005-04-21 Advanced Semiconductor Eng Flip chip package
US6872589B2 (en) * 2003-02-06 2005-03-29 Kulicke & Soffa Investments, Inc. High density chip level package for the packaging of integrated circuits and method to manufacture same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI834089B (zh) * 2021-07-20 2024-03-01 大陸商安徽寒武紀信息科技有限公司 一種系統整合單晶片、生成方法與可讀存儲介質

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US7489025B2 (en) 2009-02-10
US7098070B2 (en) 2006-08-29
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US20060105496A1 (en) 2006-05-18
US20060113598A1 (en) 2006-06-01
US7736949B2 (en) 2010-06-15
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JP2008521213A (ja) 2008-06-19
TW200634946A (en) 2006-10-01

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