CN100481421C - 形成半导体封装的方法 - Google Patents

形成半导体封装的方法 Download PDF

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CN100481421C
CN100481421C CNB2005800359390A CN200580035939A CN100481421C CN 100481421 C CN100481421 C CN 100481421C CN B2005800359390 A CNB2005800359390 A CN B2005800359390A CN 200580035939 A CN200580035939 A CN 200580035939A CN 100481421 C CN100481421 C CN 100481421C
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chip
hole
wafer
sub
cavity
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CN101044618A (zh
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H·H·陈
L·L-C·许
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

本发明涉及半导体加工和装置领域，提供一种形成半导体封装的方法，包括以下步骤：穿过晶片的第一面形成通孔；在所述晶片的第二面形成空腔，暴露所述通孔的一部分；在所述空腔中设置至少一个子芯片，并且将所述子芯片连接到所述通孔；其中，所述晶片包括顶部硅层和通过掩埋介电层与顶部硅层相隔离的硅衬底，所述穿过晶片的第一面形成通孔的步骤包括穿过顶部硅层和掩埋介电层蚀刻过孔以及用导体填充所述过孔。

Description

形成半导体封装的方法
技术领域
本发明涉及半导体加工和装置，更具体而言涉及采用绝缘体上硅(SOI)技术提供双面芯片结构的装置和方法。
背景技术
随着互补金属氧化物半导体(CMOS)技术的不断的按比例缩小达到其物理极限，超大规模集成电路(VLSI)系统级封装(SoP)的集成变得日益重要。由于不同芯片技术之间的不兼容性，在封装上许多不同芯片的集成通常不是成本有效的。例如，制造具有浮栅器件的非易失性随机存取存储器(NVRAM)和具有深沟槽的动态随机存取存储器(DRAM)需要额外的掩模和加工步骤。在与硅芯片不同的衬底上制造高速砷化镓(GaAs)芯片。
在二维(2-D)或者三维(3-D)封装上集成不同芯片的有效方法不仅可以提高电路的性能，而且可以降低制造成本。如果垂直地层叠芯片，还应该使用通孔以进一步减少互连延迟和使电路的性能最大化。
最近已经开发出先进的三维晶片至晶片垂直层叠集成技术以提高系统性能。在名称为“Etch stop layer for silicon via etch in three-dimensionalwafer-to-wafer vertical stack”的美国专利No.6,645,832中描述了一种使用硅化镍(NiSi)作为用于硅过孔蚀刻的蚀刻停止层的方法。在3-D封装中，使用介电层接合两个垂直地层叠的晶片，并且需要硅过孔蚀刻以便在晶片之间提供导电性。
通过选择性地蚀刻穿过顶部晶片的硅直到被蚀刻停止层停止，形成过孔。用绝缘材料的层涂敷硅过孔的侧壁，形成阻挡层。然后用导电材料填充过孔，以提供电连接。
在名称为“Process of vertically stacking multiple wafers supportingdifferent active integrated circuit devices”的美国专利No.6,762,076中，使用一种金属至金属的接合方法接合邻近的晶片并提供电连接。
在名称为“Three-dimensional chip stacking assembly”的美国专利No.6,355,501中，将多个绝缘体上硅(SOI)芯片层叠到一起，并且通过对准在芯片的顶面和底面处预先制造的接触来实现芯片之间的互连。通过背面化学机械抛光(CMP)显著地减薄每个芯片，以去除掩埋氧化物层后的所有材料.在3-D组件中，每个SOI芯片包括与第一金属化图形形成机械接触的处理物(handler)、与半导体器件形成电接触的第一金属化图形，以及与半导体器件的相反表面上的第二金属化图形形成电接触的半导体器件。
在名称为“Process for making fine pitch connections between devicesand structure made by the process”的美国专利No.6,737,297中，公开了一种通过对准在芯片表面上的销(stud)与在临时对准衬底上的过孔，利用预先制造的全局布线在临时衬底上将两个或者多个芯片接合到一起的方法。然后将二维芯片组件转移到具有热沉装置的永久支撑载体上，接着融化并从组件中去除临时对准结构的透明板。
在名称为“Wafer level stack chip package and method formanufacturing same”的美国专利No.6,607,938中，在再分布衬底上层叠半导体芯片。在将相应晶片上的多个薄芯片层叠到一起之后，由层叠晶片组件切割出层叠芯片结构，然后剥离掉载体材料.
在名称为“Wafer-scale assembly of chip-size packages”的美国专利No.6,730,541中，使具有用于每个接触衬垫的焊料球的聚合物膜与晶片对准。对晶片的背面施加红外能量，以均匀地加热晶片。然后重复该步骤，以顺序地装配插入物(interposer)和具有焊料球的第二聚合物膜。
发明内容
一种半导体器件或封装，包括晶片，所述晶片具有包括电子部件的第一面和与所述第一面相反并形成空腔的第二面。芯片或部件被置于所述空腔中。通孔穿过所述晶片的一部分将所述芯片连接到所述电子部件。
通过结合附图阅读本发明的示例性实施例的以下详细描述，本发明的这些和其它目的、特征和优点将变得显而易见。
附图说明
现在将仅通过实例，参考附图描述本发明的优选实施例，其中：
图1是示出了形成于其上的电子部件的绝缘体上硅结构/晶片的截面图；
图2是截面图，其示出了根据本发明的一个实施例的所蚀刻的通孔、所形成的并且用导电材料填充的介电衬里；
图3是截面图，其示出了根据本发明形成在晶片的第一面的保护涂层；
图4是截面图，其示出了根据本发明为了准备蚀刻而对晶片的硅衬底部分进行的抛光/蚀刻；
图5是截面图，其示出了根据本发明的硅衬底(背面)光刻构图；
图6是截面图，其示出了根据本发明的背面蚀刻以形成空腔；
图7是截面图，其示出了根据本发明在空腔内的在通孔周围开口的凹槽(pocket)；
图8是截面图，其示出了根据本发明在通孔上焊料的选择性淀积；
图9是截面图，其示出了根据本发明在背面空腔中设置子芯片并使子芯片与通孔对准；
图10是截面图，其示出了根据本发明将子芯片焊接并接合到通孔以允许子芯片和原来的部件共同作用来执行功能；
图11是截面图，其示出了根据本发明导热底部填充(underfill)和淀积导热层；
图12是截面图，其示出了根据本发明从晶片的正面去除保护涂层；
图13是截面图，其示出了根据本发明的正面全局互连形成和C4形成；
图14是截面图，其示出了根据本发明的背面热沉的形成；
图15是透视图，其示出了根据本发明的一个实施例，通过通孔设置并连接到母芯片的多个子芯片；以及
图16是根据本发明的一个实施例的具有设置在其中的子体(子芯片)的母芯片的顶部示意图，其示出了通孔设置和功能。
具体实施方式
本发明提供一种优选地在绝缘体上硅(SOI)晶片上的低成本且高产量的双面晶片级封装(wafer scale package).在具有完全或者部分耗尽体的SOI晶片的正面形成母芯片以实现高性能。然后，在SOI晶片的与母芯片相反的背面的空腔内部安装多个减薄的子体芯片.穿过硅和掩埋氧化物制造金属销以便于母芯片与子体芯片之间的互连。
有利地，本方法不需要将芯片从临时载体转移到永久载体，这降低了成本。因此，通过采用通孔连接和形成腔，可以从晶片直接切下子芯片(子体芯片)并在母芯片的背面安装子芯片。本方法还避免了在3-D封装中使用垂直层叠(vertical stacking)以利于散热.此外，可以在同一封装上集成以不同技术制造的多个芯片。
双面封装方案在晶片的两侧采用二维芯片封装模式.在SOI晶片正面的薄硅层中，制造母芯片例如中央处理单元和并串行转换器/串并行转换器(SerDes)芯片。通过浮体效应以及低结电容提高这些芯片的性能。
浮体效应是SOI MOSFET的固有特性。因为体电位不固定，注入到体中的空穴使得体中的电位升高，导致较低的阈值电压、较高的漏极电流和较快的栅.并且掩埋氧化物层消除了源极/漏极扩散区与衬底之间的区域结电容，这允许晶体管以较小的充电和放电电容较快地运行。通过设置在晶片的背面的二级部件，母芯片将具有比等效的系统级芯片(SoC)设计更小的尺寸和更高的产量。
可以使用在SOI晶片正面的剩余区域形成解耦电容器和其它分立器件.在蚀刻以形成用于子体芯片的空腔之前，SOI晶片的背面可具有可以被减薄的较厚材料。可以嵌入到空腔中的子体芯片可包括高速射频(RF)输入/输出(I/O)芯片、其深沟槽电容器工艺与常规CMOS工艺不完全兼容的存储器芯片例如非易失性随机存取存储器(NVRAM)、磁RAM(MRAM)、铁电RAM(FRAM)和嵌入式动态RAM(eDRAM)、解耦电容器、高Q半导体电感器、以及微机电系统(MEMS)。
本发明可形成这样的深过孔，该深过孔从在SOI晶片正面的母芯片的衬垫出发，穿过掩埋氧化物层，到达在SOI晶片背面的子体芯片的衬垫。这些通孔不仅提供功率供给、信号和控制，而且还能够通讯、测试和监视母芯片和子体芯片。为制造通孔，在母芯片的指定衬垫下不应形成器件或者互连。由于顶部硅层和掩埋氧化物层的总厚度在几百微米的范围内，所以这些通孔的尺寸可以比常规多芯片封装的尺寸小得多。
应该理解，虽然将根据具有SOI晶片的给定的示例性体系结构描述本发明；但是其它的体系结构、结构、衬底材料以及工艺特征和步骤可以在本发明的范围内被改变。
现在详细参考附图，附图中相同的标号代表相同或者相似的元件，并且从图1开始，示例性地示出了具有顶部硅层43、掩埋介电(例如氧化物)层42、以及底部衬底40(例如硅)的绝缘体上硅(SOI)晶片10。集成电路系统11包括形成在硅晶片10上的有源器件44、金属互连45、以及分立器件48。在SOI晶片上的掩埋氧化物层42可包括例如5微米或者更小的厚度。
参考图2，可形成沟槽50。在一个实施例中，可以使用高密度等离子体反应离子蚀刻(RIE)产生穿过层32、42和43向下直到硅衬底40的沟槽50，以形成通孔51，该通孔51允许在晶片10的背面安装其它芯片，并且在这里将被详细地描述。
在光刻构图、蚀刻、侧壁介电涂敷52、以及金属或者导电填充53之后，穿过顶部硅层43形成通孔51。在一个实施例中，过孔深度与过孔尺寸(例如沟槽宽度)的比率的范围在约1至约5之间。为了分别地蚀刻后段制程(BEOL)绝缘材料32、硅层43、以及掩埋氧化物层42，可以用合适的终点检测法依次使用CF4、Cl2和/或CF4基等离子体蚀刻。这样的检测方法在本技术领域是已知的。
为确保过孔51延伸至掩埋氧化物层42之下，有必要过蚀刻掩埋氧化物层42。优选地采用绝缘材料52例如氧化物/氮化物侧壁隔离物，以防止过孔51与任何相邻的导电层、阱区、或者衬底层短路。然后可以用导电金属53例如铜、钨、铝、掺杂的多晶材料、合金和/或任何其它导电材料填充过孔51。可以使用保形的化学气相淀积(CVD)深蚀刻技术来消除在填充工艺期间在过孔51内部的任何空隙(void)的形成。
参考图3，在晶片10的顶面上形成保护涂层60例如氧化物、氮化物、氧氮化物、或者玻璃的层，以在背面加工期间保护晶片10的顶面不被损伤。也可以采用其它材料或者保护方案。
参考图4，通过例如化学机械抛光(CMP)或者高密度等离子体蚀刻(例如RIE)，将在晶片的背面的硅衬底40减薄至合适的厚度“d”。优选地，“d”比将要安装在背面的最厚的芯片的厚度大几微米。
参考图5和6，通过使用已知的方法施加光致抗蚀剂66并且构图抗蚀剂66，产生光刻图形64。然后在蚀刻工艺中采用抗蚀剂66作为掩模形成一个或多个背面空腔68。空腔68的尺寸应该稍大于将要安装到其内部(开口表面之下)的芯片，并且应该提供容限以防对不准。在同一空腔68内部可设置多个芯片。
在蚀刻之后形成空腔68，并且在掩埋氧化物层42的表面处暴露出通孔51的导电材料53。从衬底40去除抗蚀剂66。
参考图7，可采用额外的蚀刻步骤，以通过在掩埋氧化物42的表面处的薄光致抗蚀剂构图和曝光，在每个过孔51的顶部上开设凹槽70。优选在随后的接合和焊接回流步骤期间形成凹槽70，以为焊料流动提供空间，从而形成更好的接触。
参考图8，可采用选择性镀敷工艺在过孔51中的暴露的销53上和凹槽70的内部形成焊料球74。该工艺在销53上选择性地形成金属。优选在形成焊料球74时使用低熔化温度的材料。焊料球74可包括锡或者铅合金，并且可采用与受控塌陷芯片连接(C4)接合法相似的工艺。
参考图9，示例性地示出了芯片(子芯片)80和82与过孔51的销53形成接触。芯片80和82可包括减薄的芯片(之前称为子体芯片)，这些减薄的芯片被上面朝下地倒置，置于空腔68内部，并且接合到母芯片(晶片10)。优选地，空腔68的深度(d)比所有子体芯片(80和82)的厚度大。根据本发明，芯片80和82可以在分开的加工步骤中形成，并且在芯片80和82本身中可以包括使更小的子芯片连接至其的空腔。
可以在芯片80与82之间以及壁86与芯片80和82之间具有间隙84地将芯片80和82置于空腔68中。可选地，芯片80和82可以包括间隔物或者材料层，以确保销53与每个芯片80和82的接触88和90的适当配合和自动对准。还可以使用切削加工(tooling)或者其它开缝(gapping)方法对准这些芯片80和82。在一个实施例中，在将芯片80和82置于空腔68中之前，使芯片80和82彼此连接或附接。
接合工艺可包括在约400℃的温度进行，以使用于子体芯片80和82的接触88和90的焊料球与用于母芯片10的通孔51的焊料球74接合。
参考图10，示出了在凹槽区域70内过剩的接合材料94的聚集。现在芯片80和82被接合到过孔51。
参考图11，采用底部填充工艺，以用导热试剂98例如散热膏(thermalpaste)、或者标准填充聚合物或者其它填充物，填充间隙84和86以及在芯片80和82与晶片10之间的任何其它部位。优选试剂98是导热的以促进散热，并作为电绝缘体。空腔68的顶面可以进一步用更导热的材料102例如化学气相淀积(CVD)的金刚石填充。还可在晶片10的背面形成金属膜104，以密封空腔68内的子体芯片。
参考图12，在背面安装子体芯片80和82之后，可以剥离母芯片120(在晶片10上)的顶部保护层60。这可以为在系统上的进一步加工例如全局或局部互连和过孔、附接其它部件或者形成额外的层或者技术特征等做准备。
参考图13，可以在母芯片120的晶片10的正面形成更多的金属层106、接触衬垫108、以及C4球110。可进行进一步加工以形成额外的结构或者提供用于系统100的封装。
可以从晶片10切割出最终的双面芯片组件100(例如，对晶片切片以形成芯片封装)，其中每个组件具有在正面的母芯片120和安装在背面的多个子体芯片(例如80和82)。使用SOI晶片10的掩埋氧化物层42作为在母芯片120与子体芯片80和82之间的通孔互连的保持板。
可以在芯片的背面安装热沉111，如图14中所示例性地示出的。热沉111可使用例如热粘合材料附接，或者可通过淀积材料并将该材料蚀刻成预定的形状(例如鳍片(fin)和槽)而形成。
参考图15，SOI晶片级封装200包括一个母芯片202例如形成在顶部硅层(例如图1的43)上的处理器(或者存储器装置或者其组件)以实现高性能，以及几个子体芯片204、206、208、210和212。这些芯片可包括例如安装在组件200的背面的SRAM高速缓冲存储器、eDRAM、NVRAM、FPGA、以及高速RF接口芯片。在母芯片202与子体芯片204-212之间的一个区域中示例性地示出了通孔连接251。需要在适当地规划之后进行过孔和芯片的设置和对准。优选为封装200共同设计母芯片和子体芯片，以确保共同作用、适当对准/设置和适当的功能。
参考图16，即封装300的一个实例，其中母芯片302包括3个宏M1、M2、和M3(子芯片)。封装300指出了在系统中共同设计母芯片和子体芯片期间要考虑的方面。在该实施例中，仅允许通孔连接351存在于在相邻的宏(M1、M2、M3)与母芯片衬底的边缘340之间的空白区中。通孔351可以被指定用于不同的任务，例如承载电力Vdd、或Vss或者信号(Signal)，如图16中所示例性地示出的。在可选实施例中，母芯片302可以由多个芯片C1、C2、C3和C4组成并使用宏、结构或者子芯片连接。
已描述了制造具有掩埋氧化物通孔连接的双面SOI晶片级封装的装置和方法的优选实施例(其旨在示例而非限制)，注意本领域的技术人员根据上述内容可以做出修改和改变。因此，应该理解，在所公开的本发明的特定的实施例中可以做出改变，这些改变在由所附权利要求所概括的本发明的范围内。

Claims (9)

1.一种形成半导体封装的方法，包括以下步骤：
穿过晶片的第一面形成通孔；
在所述晶片的第二面形成空腔，暴露所述通孔的一部分；以及
在所述空腔中设置至少一个子芯片，并且将所述子芯片连接到所述通孔；其中，所述晶片包括顶部硅层和通过掩埋介电层与顶部硅层相隔离的硅衬底，所述穿过晶片的第一面形成通孔的步骤包括穿过顶部硅层和掩埋介电层蚀刻过孔以及用导体填充所述过孔。
2.根据权利要求1的方法，其中所述在所述晶片的第二面形成空腔暴露所述通孔的一部分的步骤包括蚀刻所述晶片的硅衬底以暴露所述通孔的所述一部分。
3.根据权利要求1的方法，其中暴露所述通孔的一部分包括在所述空腔中在所述通孔的周围开设凹槽。
4.根据权利要求1的方法，还包括将焊料选择性淀积到所述通孔的所述暴露的部分的步骤。
5.根据权利要求1的方法，其中所述在所述空腔中设置至少一个子芯片并将所述子芯片连接到所述通孔的步骤包括将所述子芯片的接触焊接到所述通孔的步骤。
6.根据权利要求1的方法，还包括用导热材料底部填充所述子芯片的步骤。
7.根据权利要求1的方法，还包括在所述子芯片上方淀积导热层的步骤。
8.根据权利要求1的方法，还包括设置热沉以从所述子芯片散热的步骤。
9.根据权利要求1的方法，其中将所述子芯片连接到所述通孔包括使所述子芯片的接触与焊接的通孔对准并接触，并且施加热以将所述接触接合到所述通孔。
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