CN102124562B - 使用接口晶片作为永久载板制造三维集成电路装置的方法和设备 - Google Patents

使用接口晶片作为永久载板制造三维集成电路装置的方法和设备 Download PDF

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Publication number
CN102124562B
CN102124562B CN200980132049XA CN200980132049A CN102124562B CN 102124562 B CN102124562 B CN 102124562B CN 200980132049X A CN200980132049X A CN 200980132049XA CN 200980132049 A CN200980132049 A CN 200980132049A CN 102124562 B CN102124562 B CN 102124562B
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wafer
active circuit
circuit layer
interface
layer
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CN102124562A (zh
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S·J·科伊斯特
S·皮鲁肖查曼
R·哈农
M·法罗克
虞蓉卿
刘菲
S·赖伊尔
A·扬
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Core Usa Second LLC
GlobalFoundries Inc
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International Business Machines Corp
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Abstract

提供了一种制造3D集成电路结构的方法。提供接口晶片，所述接口晶片包括第一布线层和穿透硅通路，提供第一有源电路层晶片，所述第一有源电路层晶片包括有源电路。将所述第一有源电路层晶片接合至所述接口晶片。随后，移除所述第一有源电路层晶片的第一部分，以使得所述第一有源电路层晶片的第二部分保持附着至所述接口晶片。包括所述接口晶片和所述第一有源电路层晶片的所述第二部分的堆叠结构被接合至基底晶片。此后，薄化所述接口晶片以形成接口层，以及形成金属化层于所述接口层上，所述金属化层通过所述接口层中的所述穿透硅通路耦合至所述第一布线层。还提供了一种编码有包括用于执行制造3D集成电路结构的方法的指令的程序的实体计算机可读介质。

Description

使用接口晶片作为永久载板制造三维集成电路装置的方法和设备
技术领域
本发明通常涉及集成电路的领域，尤其涉及三维(3D)集成电路装置的制造。 
背景技术
业界目前正积极研发三维(3D)集成电路装置。3D集成电路装置制造所面临的一个问题是，通用基板薄化技术无法产生可控制厚度的最终基板，其厚度薄到足以实现具有合理纵横比的高密度的穿透硅通路。一项克服此问题的已知技术是利用埋置氧化物层(BOX)作为蚀刻停止层。但是，此技术仅对绝缘体上硅(SOI)晶片有用。另外，即使是SOI晶片，此技术对于具有延伸于埋置氧化物下方的结构(如嵌入式DRAM(e-DRAM)沟槽)的SOI电路也无法发挥作用。 
另一项克服此问题的已知技术是利用双埋置氧化物层(双BOX)结构。然而，此技术却使制造成本大幅增加。另外，如同单埋置氧化物层结构的解决方案，双BOX技术也需要保护基板不受其它晶片的影响。需要这种保护的原因是，尽管SOI晶片用作蚀刻停止层，但其无法提供不同基板间的选择性。 
又另一项克服此问题的已知技术是不使用蚀刻停止层而是执行「盲」(blind)薄化。但此技术无法激进地薄化晶片，因而产生了均匀性问题。另外，对于需要高密度3D通路的集成电路，此技术还强制使用不能用铜填充的高纵横比通路。事实上，通路必须使用钨，其电阻率为铜的三倍。 
在制造3D集成电路装置时所面临的另一问题是，为形成多层堆叠而堆叠三层或更多层会导致产量降低。一项尝试克服此问题的技术是通过至临时处理晶片的接合来堆叠层。然而，使用这种临时处理晶片(如，玻璃晶片)将引起重叠变形，其降低了晶片间的重叠对准。也就是说，此技术在后续的光刻步骤中无法实现高精确度的光学对准。没有高精确度的光学对准，将降低通路密度且必须使用具有高寄生电容的大的捕获焊垫。另外，使用这种至临时处理晶片的接合在堆叠晶片的方式上很没有弹性。 
另一尝试克服此问题的技术是仅使用晶片的直接面对面连接。但这种直接面对面连接有问题，因为接下来在整个堆叠制程中，必须使用底部晶片(通常是逻辑晶片)作为处理晶片。尽管这在制造两层堆叠时是可以接受的，但对于多层(即，三层或更多层)堆叠，这意味着逻辑晶片必须经历许多接合及薄化步骤。这对于整个集成电路，包括在堆叠中常常是最昂贵晶片的逻辑晶片，增加了不幸失败及损失的机率。 
发明内容
本发明的一个实施例提供了一种制造3D集成电路结构的方法。根据所述方法，提供接口晶片，所述接口晶片包括第一布线层和穿透硅通路。提供第一有源电路层晶片，所述第一有源电路层晶片包括有源电路，将所述第一有源电路层晶片面朝下地接合至所述接口晶片。随后，移除所述第一有源电路层晶片的第一部分，以使得所述第一有源电路层晶片的第二部分保持附着至所述接口晶片。提供基底晶片，所述基底晶片包括第二布线层。所述堆叠结构包括所述接口晶片和所述第一有源电路层晶片的所述第二部分。接着，薄化所述接口晶片以形成接口层，以及形成金属化层于所述接口层上。所述金属化层通过所述接口层中的所述穿透硅通路耦合至所述第一布线层。 
本发明的另一实施例提供了一种编码有包括用于执行制造3D集成电路结构的方法的指令的程序的实体计算机可读介质。 
参考以下所述的详细说明，将可了解本发明的其它目的、特征及优点。然而，应理解，具体描述及具体实例尽管代表本发明的优选实施例，但仅是通过说明的方式而给出的，且自然而然地可在不脱离本 发明的情况下执行各种修改。 
附图说明
图1至11示出了根据本发明的一个实施例的用于制造三维集成电路装置的制程的横截面图； 
图12示出了根据本发明的一个实施例的具有逻辑层-有源电路层-接口层堆叠结构的3D集成电路结构； 
图13示出了根据本发明的一个实施例的其中所有层为SOI晶片的3D集成电路结构； 
图14示出了根据本发明的一个实施例的在堆叠结构的接口层中具有电路元件的3D集成电路结构；及 
图15为半导体设计、制造和/或测试中所用的设计方法的流程图。 
具体实施方式
以下参考附图详细说明本发明的优选实施例。 
本发明的实施例使用接口晶片作为在三维(3D)集成电路装置制造期间的永久载板。在一个示范性实施例中，使用接口晶片在堆叠各层期间作为堆叠中用于除了基底晶片外之所有层的载板。因此，不需要将各层接合至临时处理晶片。在堆叠各层及将其附着至基底晶片之后，并不丢弃此载板(即，接口晶片)，而是永久地保留在3D集成电路装置的堆叠层及封装之间作为接口。例如，在该示范性实施例中，接口晶片以与封装相同的间距具有穿透硅通路，且具有将引线重新布线至堆叠底层之接口的重分配布线。因此，本发明克服使用临时处理晶片形成层堆叠时所出现的问题。 
图1至11示出了根据本发明的一个实施例的制造三维集成电路装置的制程。如图1所示，制程始于接口晶片100，其是完成的集成电路中的堆叠有源电路层和封装之间的接口。具体的，接口晶片100的暴露表面将承载完成的集成电路中的C4(控制破裂芯片连接)焊料凸块。这些C4(或倒装芯片)焊料凸块用于将集成电路附着至封装(如， 树脂或陶瓷模块)。接口晶片100是由在后续基板移除步骤中所用的蚀刻剂中不可溶的材料(即，在相对于P-层选择性蚀刻P+层的蚀刻剂中不可溶的材料)制成的基板。 
在该实施例中，接口晶片并非由P+基板形成，所以其不会受到移除堆叠中有源电路层的晶片基板的蚀刻的影响。接口晶片100是以与封装相同的间距具有穿透硅通路102的硅基板。在此实施例中，接口晶片中通路的深度及大小不同于其它晶片中通路的深度及大小。另外，在该实施例中，以钨金属填充穿透硅通路。在进一步实施例中，以其它冶金，如铜，填充穿透硅通路。接口晶片100的穿透硅通路不需要以与堆叠中其它层的穿透硅通路相同的材料制成。接口晶片100还具有布线层104，其分配信号及功率至集成电路的堆叠层。在该实施例中，接口晶片100对红外线辐射是透明的。 
此外，提供第一有源电路层晶片200。第一有源电路层晶片200以P+/P-硅基板形成，其为具有P-顶部有源电路层204的P+晶片202。在该实施例中，P-顶部有源电路层204外延生长于P+晶片上且具有介于约5和20微米之间的厚度。另外，在该实施例中，P+晶片为硼掺杂晶片，其掺杂浓度介于约1×1018cm-3至3×1020cm-3之间，和P-外延层具有掺杂浓度小于约1×1018cm-3。在进一步实施例中，P-外延层未经特意掺杂，或为N型掺杂，其浓度小于约1×1018cm-3。 
将穿透硅通路206蚀刻至P-顶部有源电路层204中，使其结束于P+晶片202附近。在进一步实施例中，通路206穿过P+晶片202的表面。在该实施例中，以铜填充穿透硅通路。在进一步实施例中，以其它冶金填充穿透硅通路。有源电路(即，有源组件，如晶体管)和一个或多个布线层208形成于第一有源电路层晶片200的顶面。 
接下来，如图2所示，第一有源电路层晶片200面朝下地对准接口晶片100。比起其中一个晶片利用临时处理晶片(如，玻璃的临时处理晶片)的情况，使用两个硅晶片的面对面对准允许更高精确度的对准。将第一有源电路层晶片200接合至接口晶片100，使得接口晶片当作第一有源电路层的永久载板。在该实施例中，利用铜-铜或是铜 -铜和粘着接合(如，使用聚合物粘合剂)的组合。在进一步实施例中，利用了其它冶金(如铜合金或镍-金合金)。 
然后选择性移除第一有源电路层晶片200的P+层202，如图3所示。在该实施例中，首先利用一系列非选择性基板薄化制程(如，晶片研磨和抛光)，然后再利用湿式化学蚀刻相对于P-层204选择性移除其余P+层202。使用如HNA(氢氟酸/硝酸/乙酸)的选择性蚀刻剂，执行第一有源电路层晶片200的P+层202的最后移除。由于接口晶片100的块体在此选择性蚀刻剂中为不可溶的，制程是有鲁棒性的。此外，在该实施例中，接口晶片100以轻掺杂的N-或P-硅制成，以便执行红外线(IR)对准。在其它实施例中，接口晶片100也是P+硅基板。 
该选择性移除P+层未实质上影响到保留下来的P-外延层204、有源电路和布线层104和208、或接口晶片100。因此，使用P+/P-基板可使P+层被选择性移除，使得可控制地薄化晶片至P-层的厚度，其可以变得非常薄(如，约5-20微米厚)。 
接下来，在该实施例中，执行回蚀刻(如，使用反应离子蚀刻)，以暴露P-层204中通路206的顶部部分。在其中通路206进入P+层202的其它实施例中，不需要这种蚀刻，因为通路的顶部部分在选择性移除P+层之后已经暴露。然后将具有绝缘和一个或多个耦合至通路206的后段制程(BEOL)金属化层的布线层210图案化到P-层204的背面上，如图4所示。在该实施例中，布线层210的每一个金属化层通过以下方式形成：沉积介电层、蚀刻该介电层和沉积金属于蚀刻区域中。 
接着重复这些步骤任意次数，以在接口晶片100上形成多层堆叠，其中接口晶片用作此堆叠的永久载板。例如，在所示的实施例中，再重复这些步骤一次，以形成第二有源电路层。更具体地说，形成第二有源电路层晶片300，如图5所示。第二有源电路层晶片300也以P+/P-硅基板形成，其是具有P-顶部有源电路层304的P+晶片302。在该实施例中，P-顶部有源电路层304是外延生长的，且具有介于约5和20 微米之间的厚度。将穿透硅通路306蚀刻至P-顶部有源电路层304中，使结束于P+晶片302附近，以及形成有源电路和一个或多个布线层308于第二有源电路层晶片300的顶面。 
接下来，如图6所示，使第二有源电路层晶片300面朝下地对准附着至接口晶片100的第一P-层204上的布线层210。比起晶片之一利用临时处理晶片(如，玻璃的临时处理晶片)的情况，使用两个硅晶片的面对面对准允许更高精确度的对准。使用铜-铜或是铜-铜和粘着接合的组合，将第二有源电路层晶片300接合至布线层210，使得接口晶片用作第一和第二有源电路层的永久载板。在进一步实施例中，利用其它冶金(如铜合金或镍-金合金)。 
然后选择性移除第二有源电路层晶片300的P+层302，如图7所示。在该实施例中，首先利用一系列非选择性基板薄化制程(如，晶片研磨和抛光)，然后再利用湿式化学蚀刻相对于第二有源电路层晶片300的P-层304选择性移除第二有源电路层晶片300的其余P+层302。该选择性移除第二有源电路层晶片300的P+层302未实质上影响到保留下来的P-层204和304、有源电路和布线层104、208、210和308、或接口晶片100。因此，接口晶片100是很有鲁棒性的，能够应付移除被用于形成多层堆叠的所有有源电路层晶片的P+层的多个基板移除蚀刻。 
接着执行回蚀刻以暴露第二P-层304中的通路306的顶部部分。然后将具有绝缘和一个或多个耦合至通路306的BEOL金属化层的布线层310图案化到第二P-层304的背面上，如图8所示。 
将接口晶片当作有源电路层的堆叠的永久载板，以此方式在将所要数量的有源电路层接合到一起之后，形成的结构被附着至基底晶片800，如图9所示。该实施例的基底晶片800由块体硅或SOI制成，且其顶部为具有绝缘和一个或多个BEOL金属化层的布线层808。在该实施例中，基底晶片800没有穿透硅通路。在一些实施例中，基底晶片包括有源电路(如，晶体管)和/或无源电路元件(如，电阻器和电容器)。在接口晶片100当作堆叠的永久载板的情况下，接口晶片 和附着至接口晶片的有源电路层的堆叠面朝下地对准基底晶片。因此，由于这些组件在该实施例中已「翻转」两次，先前堆叠在接口晶片100上的所有有源电路层现在相对于基底晶片800为面向上方，如图9中的箭头所示。 
接着将多层堆叠的顶部布线层310接合至基底晶片800。在该实施例中，利用铜-铜或是铜-铜和粘着接合(如，使用聚合物粘合剂)的组合。在进一步实施例中，利用其它冶金(如铜合金或镍-金合金)。接着处理永久载板(即，接口晶片)，以保留在3D集成电路装置中的堆叠层和封装之间作为接口。具体的，使接口晶片100薄化。在该实施例中，以两个步骤达成该薄化。第一，执行晶片研磨和抛光的组合，使接口晶片薄化至接口晶片100中的通路102上方。然后，通过干式蚀刻(如，使用反应离子蚀刻)，使接口晶片100进一步薄化，以形成暴露通路102的顶部部分的接口层101，如图10所示。接着沉积背面介电层820于接口层101的背面上。 
如图11所示，接着抛光和/或蚀刻背面介电层820，和沉积接触金属化层822于接口层101的通路102上。在该实施例中，沉积简单的球限制金属化于通路上，以便能够沉积C4焊料凸块。在其它实施例中，形成更复杂的介电层和金属化层。然后，沉积C4焊料凸块825于接触金属化层822上，以完成3D集成电路结构。在该实施例中，C4焊料凸块的直径大约为100μm的数量级以及间距为200μm的数量级或以下。接着使用这些C4(或倒装芯片)焊料凸块将集成电路接合至封装(如，树脂或陶瓷模块)。 
上述示范性制程仅是用来解说本发明的原理。通过简单地改变接口晶片上堆叠的层的数量、类型和顺序，即可产生许多不同的3D集成电路结构。例如，虽然上述示范性制程产生具有1+2+1堆叠(1基底晶片、2有源电路层和1接口层)的结构，但通过简单地重复上述有源电路层堆叠制程N次，即可形成具有1+N+1堆叠的结构。在1+N+1堆叠结构中，额外的有源电路层(每一个类似于由层210、204和208形成的有源电路层)被堆叠在图11的结构中第一有源电路层的层210 和最后一个(第N个)有源电路层的层308之间(例如，见图12)。 
同样地，仅执行有源电路层堆叠制程一次，可形成具有1+1+1堆叠的结构。在1+1+1堆叠结构中，第二有源电路层(由层310、304和308所形成的有源电路层)不存在于图11的结构中。因此，可按与在基底晶片上仅堆叠一个有源电路层一致的方式使用本发明的堆叠多个有源电路层于基底晶片顶部上的制程。 
在进一步实施例中，使用逻辑晶片(即，含逻辑电路的晶片)作为基底晶片(即，包括逻辑电路的基底晶片)。例如，图12示出了根据本发明的一个实施例的具有逻辑晶片-有源电路层-接口层堆叠结构的3D集成电路结构。该示范性实施例具有被堆叠在N个有源电路层(即存储器层)顶部上的接口层，N个有源电路层又堆叠在逻辑晶片的顶部上。存储器层可以是任何类型的存储器，如SRAM存储器、e-DRAM存储器、或此二者之组合。逻辑晶片含有控制和/或逻辑电路，如存储器控制器或处理器核心。在另一实施例中，将接口层和仅一个有源电路层(如，存储器层)堆叠在逻辑晶片的顶部上。 
此外，上述制程中所使用的一个或多个晶片可以是绝缘体上硅(SOI)晶片。例如，图13示出了根据本发明的一个实施例的其中所有层均在SOI晶片上形成的3D集成电路结构。在替代性实施例中，基底晶片是SOI基板(如图13)，而有源电路层和接口层的晶片是块体硅晶片(如图12)。在又另一实施例中，基底晶片是SOI基板(如图13)，有源电路层的晶片包括SOI晶片(如图13)和块体硅晶片(如图12)二者，以及接口层的晶片是SOI或块体硅晶片。 
图14示出了根据本发明的一个实施例的在堆叠结构的接口层中具有电路元件的3D集成电路结构。在该实施例中，通过有源电路和/或无源电路元件的配置，接口层包括额外的功能性。例如，接口层可包括解耦电容器层，以稳定电压栅。可选地或者附加地，接口层可包括由有源晶体管和例如解耦电容器的无源组件所形成的电压调节电路。 
因此，本发明的实施例利用接口晶片在三维(3D)集成电路装置 制造期间作为永久载板。接口晶片在层堆叠期间被用作堆叠中所有层的载板，因此并不需要用到临时处理晶片。该载板(即，接口晶片)永久地保留在3D集成电路装置中的堆叠层和封装之间作为接口。因此，本发明克服了使用临时处理晶片形成3D集成的层堆叠时所出现的问题。另外，可针对不同的堆叠类型，如两个有源层的堆叠和多层堆叠，轻易地调整该永久载板技术。 
上述本发明的实施例是用来解说本发明的原理。这些装置的制造制程与现有技术的半导体制造方法兼容，因而本领域技术人员可进行各种修改和调整。所有此类修改仍然属于本发明的范畴之内。例如，上述各种层的厚度、材料类型、沉积技术等并没有限制的意图。 
此外，本发明实例的一些特征可在未相应使用其它特征的情况下用来获得益处。因此，应将上述说明视为只是本发明的原理、教导、实例和示范实施例的举例说明，而非其限制。 
应理解，这些实施例仅是此处创新教导的许多有利运用的例子。一般而言，本申请的说明书中所做的陈述不一定限制任何所要求保护的发明。再者，某些陈述可能适用于一些发明特征但对于其它发明特征则不适用。一般而言，除非另有指明，否则在不失一般性的原则下，单数形式也可以指单数形式，反之也然。 
上述电路是集成电路芯片的一部分设计。芯片设计在图形计算机程序语言中建立并存储于计算机存储介质(如磁盘、磁带、实体硬盘、或虚拟硬盘，如在存储存取网络中)。如果设计者并不制造芯片或并不制造用于制造芯片的光刻掩模，则设计者以实体方式(如，通过提供存储设计的存储介质的拷贝)或以电子方式(如，通过因特网)直接或间接地将所完成的设计传送到此类实体。接着将存储的设计转换成制造光刻掩模的适当格式(如，GDSII)，该掩模通常包括所讨论的将在晶片上形成的芯片设计的多个拷贝。利用光刻掩模限定晶片将被蚀刻或以其它方式处理的区域(和/或其上的层)。 
上述方法可用于制造集成电路芯片。制造商可以以原料晶片的形式(即，作为具有多个未封装芯片的单一晶片)、作为裸芯片、或以 封装形式分配所产生的集成电路芯片。在封装形式的情况中，芯片被安装于单一芯片封装中(诸如引线已固定于母板的塑料载板、或其它更高阶的载板)或安装于多芯片封装中(诸如具有表面互连或埋置互连之一或二者的陶瓷载板)。在任何情况中，芯片接着将与其它芯片、分立电路元件和/或其它信号处理装置整合，作为(a)中间产品，诸如母板；或(b)终端产品的一部分。终端产品可以是包括集成电路芯片的任何产品，其范围涵盖玩具和其它低阶应用至具有显示器、键盘、或其它输入装置和中央处理器的先进的计算机产品。 
图15示出了例如在半导体IC逻辑设计、仿真测试、布图和制造中使用的示范性设计流程900的方块图。设计流程900包括处理设计结构或装置以产生上述和图1-14所示的设计结构和/或装置逻辑或功能等效表示的方法和机制。设计流程900所处理和/或产生的设计结构可在机器可读传输或存储介质上编码，以包括数据和/或指令：当在数据处理系统上执行或以其它方式处理时，在逻辑上、结构上、机械上或另行在功能上产生硬件组件、电路、装置或系统的等效表示。设计流程900可根据所设计的表达类型而有所变化。例如，建立专用IC(ASIC)的设计流程900可以不同于用于设计标准组件的设计流程900，或不同于将设计体现成可编程阵列的设计流程900，可编程阵列例如是 
Figure BDA0000047133130000101
Inc.或 
Figure BDA0000047133130000102
Inc.提供的可编程门阵列(PGA)或场可编程门阵列(FPGA)。 
图15示出了多个此类设计结构，包括优选由设计程序910处理的输入设计结构920。设计结构920可以是由设计程序910产生和处理的逻辑仿真设计结构，用以产生硬件装置的逻辑等效的功能表示。设计结构920也可包含或替代地包含数据和/或程序指令：当由设计程序910处理时，产生硬件装置实体结构的功能表示。无论是代表功能和/或结构设计特征，均可使用如由核心开发者/设计者实施的电子计算机辅助设计(EGAD)产生设计结构920。当编码于机器可读数据传输、门阵列或存储介质上时，可由设计程序910内的一个或多个硬件和/或软件模块存取和处理设计结构920，以仿真或另行在功能上表 示电子组件、电路、电子或逻辑模块、设备、装置、或系统，如图1-14中所显示的。因此，设计结构920可包含文件或其它数据结构，所述其它数据结构包括人类和/或机器可读源代码、编译结构和计算机可执行代码结构，其在由设计或仿真数据处理系统处理时，在功能上仿真或以其它方式表示硬件逻辑设计的电路或其它层级。此类数据结构可包括硬件描述语言(HDL)设计实体或其它数据结构，所述其它数据结构符合和/或兼容于低阶HDL设计语言，如Verilog和VHDL，和/或兼容于高阶设计语言，如C或C++。 
设计程序910优选采用和并入硬件和/或软件模块，以便合成、转换、或以其它方式处理图1-14中所示组件、电路、装置、或逻辑结构的设计/仿真功能等效物，从而产生网表980，其可含有如设计结构920的设计结构。网表980可包含例如编译或以其它方式处理的数据结构，其表示线路、离散组件、逻辑门、控制电路、I/O装置、模型等的列表，其描述了集成电路设计中与其它组件和电路的连接。网表980可使用迭代程序合成，其中根据装置的设计规范和参数将网表980重新合成一次或多次。如同本文所述的其它设计结构类型，可将网表980记录于机器可读数据存储介质上或程序化于可编程门阵列中。介质可以是非易失性存储介质，如磁盘驱动器或光驱、可编程门阵列、小型闪存或其它闪存。此外，或替代地，介质可以是系统或高速缓存、缓冲器空间、或电气或光学传导装置和材料，其中数据包可经由因特网或其它网络连接的适当形式传输到这些介质上且在其上存储。 
设计程序910包括硬件和软件模块，用于处理包括网表980的各种输入数据结构类型。上述数据结构类型例如可驻存在库组件930内且包括一组常用组件、电路和装置，包括用于特定制造技术(如，不同的技术节点、32nm、45nm、90nm等)的模型、布图和符号表示。数据结构类型可以进一步包括设计规范940、特征数据950、验证数据960、设计规则970和测试数据文件985，测试数据文件可以包括输入测试模式、输出测试结果和其它测试信息。设计程序910可以进一步包括例如标准机械设计程序，如应力分析、热分析、机械事件仿真、制程仿真，用于如铸造、模制和模压形成等作业。在不脱离本发明的 范畴和精神的情况下，机械设计的本领域技术人员应明白可能的机械设计工具和设计程序910中所使用的应用程序的范围。设计程序910也可包括用于执行标准电路设计程序的模块，标准电路设计程序诸如是时序分析、验证、设计规则检查、放置与布线作业等。 
设计程序910采用和并入逻辑和实体设计工具，如HDL编译和仿真模型建立工具，以连同任何额外机械设计或数据(若适用)与所述支持数据结构的部分或全部一起处理设计结构920，从而产生第二设计结构990。设计结构990以机械装置和结构的数据交换所使用的数据格式(如，以IGES、DXF、Parasolid XT、JT、DRG、或任何其它存储或呈现此机械设计结构的恰当格式存储的信息)驻存于存储介质或可编程门阵列上。类似于设计结构920，设计结构990优选包含一个或多个文件、数据结构、或其它计算机编码的数据或指令，其驻存于传输或数据存储介质上且在由ECAD系统处理时，产生图1-14所示的本发明的一个或多个实施例的逻辑上或另行在功能上等效的形式。在一个实施例中，设计结构990可以包含编译后的、可执行的HDL仿真模型，其在功能上仿真图1-14所示的装置。 
设计结构990也可采用集成电路的布图数据和/或符号数据格式(如，以GDSII(GDS2)、GL1、OASIS、映射文件、或任何其它存储该设计数据结构的适当格式存储的信息)的交换所使用的数据格式。设计结构990可以包含信息如：符号数据、映射文件、测试数据文件、设计内容文件、制造数据、布图参数、线路、金属层级、通路、形状、通过生产线布线的数据和制造商或其它设计者/开发者需要的任何其它数据，用以产生上述和图1-14所示的装置或结构。设计结构990接着可以进行至阶段995，例如，其中设计结构990：进行至试产(tape-out)、发布以进行制造、发布至掩模工厂、送至另一设计厂、送回客户等。 
本文所描述的发明是在美国政府的资助下完成的，合同序号：N66001-04-C-8032，由Defense Advanced Research Projects Agency(DARPA)给予。美国政府对本发明具有特定的权利。 

Claims (23)

1.一种制造3D集成电路的方法，所述方法包含以下步骤：
提供接口晶片，所述接口晶片包括第一布线层和穿透硅通路；
提供第一有源电路层晶片，所述第一有源电路层晶片包括有源电路和穿透硅通路；
将所述第一有源电路层晶片面朝下地接合至所述接口晶片；
在将所述第一有源电路层晶片面朝下地接合至所述接口晶片之后，移除所述第一有源电路层晶片的第一部分，以使得所述第一有源电路层晶片的第二部分保持附着至所述接口晶片；
在移除所述第一有源电路层晶片的所述第一部分之后，在所述第一有源电路层晶片的所述第二部分上制造第二布线层；
提供第二有源电路层晶片，所述第二有源电路层晶片包括有源电路；
将所述第二有源电路层晶片面朝下地接合至所述第二布线层；
在将所述第二有源电路层晶片面朝下地接合至所述第二布线层之后，移除所述第二有源电路层晶片的第一部分，以使得所述第二有源电路层晶片的第二部分保持附着至所述第二布线层；
在移除所述第二有源电路层晶片的所述第一部分之后，在所述第二有源电路层晶片的所述第二部分上制造第三布线层；
提供基底晶片，所述基底晶片包括第四布线层；
将所述第三布线层面朝下地接合至所述基底晶片；
在将所述第三布线层面朝下地接合至所述基底晶片之后，薄化所述接口晶片以形成接口层，以及在所述接口层上形成包含焊料凸块的金属化层，所述焊料凸块通过所述接口层中的所述穿透硅通路耦合至所述第一布线层；和
将所述焊料凸块接合至封装，
其中所述接口晶片是由如下材料形成的，所述材料在移除所述第一有源电路层晶片的所述第一部分的移除步骤中使用的蚀刻剂中是不可溶的。
2.一种制造3D集成电路结构的方法，所述方法包含以下步骤：
提供接口晶片，所述接口晶片包括第一布线层和穿透硅通路；
提供第一有源电路层晶片，所述第一有源电路层晶片包括有源电路；
将所述第一有源电路层晶片面朝下地接合至所述接口晶片；
在接合所述第一有源电路层晶片之后，移除所述第一有源电路层晶片的第一部分，以使得所述第一有源电路层晶片的第二部分保持附着至所述接口晶片；
提供基底晶片，所述基底晶片包括第二布线层；
将堆叠结构面朝下地接合至所述基底晶片，所述堆叠结构包括所述接口晶片和所述第一有源电路层晶片的所述第二部分；和
在接合所述堆叠结构之后，薄化所述接口晶片以形成接口层，以及形成金属化层于所述接口层上，所述金属化层通过所述接口层中的所述穿透硅通路耦合至所述第一布线层，
其中所述接口晶片是由如下材料形成的，所述材料在移除所述第一有源电路层晶片的所述第一部分的移除步骤中使用的蚀刻剂中是不可溶的。
3.如权利要求2所述的方法，进一步包含以下步骤：
提供包括有源电路的另一有源电路层晶片；
将所述另一有源电路层晶片面朝下地接合于所述接口晶片和所述第一有源电路层晶片的所述第二部分之上；和
在接合所述另一有源电路层晶片之后，移除所述另一有源电路层晶片的第一部分，以使得所述另一有源电路层晶片的第二部分保持在所述接口晶片和所述第一有源电路层晶片的所述第二部分之上，
其中面朝下地接合至所述基底晶片的所述堆叠结构还包括所述另一有源电路层晶片的所述第二部分。
4.如权利要求3所述的方法，进一步包含以下步骤：
重复所述提供另一有源电路层晶片、接合所述另一有源电路层晶片、和移除所述另一有源电路层晶片的第一部分的步骤N次，
其中面朝下地接合至所述基底晶片的所述堆叠结构还包括另外N个有源电路层晶片的第二部分。
5.如权利要求3所述的方法，进一步包含以下步骤：
在移除所述另一有源电路层晶片的所述第一部分之后，在所述另一有源电路层晶片的所述第二部分上制造另一布线层；和
重复所述提供另一有源电路层晶片、接合所述另一有源电路层晶片、移除所述另一有源电路层晶片的第一部分和制造另一布线层的步骤N次，
其中在将所述堆叠结构面朝下地接合至所述基底晶片的所述步骤中，将在所述第N个晶片的第二部分上的布线层面朝下地接合至所述基底晶片。
6.如权利要求3所述的方法，进一步包含以下步骤：
在移除所述第一有源电路层晶片的所述第一部分之后，在所述第一有源电路层晶片的所述第二部分上制造第三布线层；和
在移除所述另一有源电路层晶片的所述第一部分之后，在所述另一有源电路层晶片的所述第二部分上制造第四布线层，
其中在接合所述另一有源电路层晶片的所述步骤中，将所述另一有源电路层晶片面朝下地接合至所述第三布线层，和
在接合所述堆叠结构的所述步骤中，将所述第四布线层面朝下地接合至所述基底晶片。
7.如权利要求2所述的方法，进一步包含以下步骤：
在移除所述第一有源电路层晶片的所述第一部分之后，在所述第一有源电路层晶片的所述第二部分上制造第三布线层，
其中在接合所述堆叠结构的所述步骤中，将所述第三布线层面朝下地接合至所述基底晶片。
8.如权利要求2所述的方法，其中所述接口层上的所述金属化层包含焊料凸块。
9.如权利要求2所述的方法，其中所述第一有源电路层晶片包含块体硅晶片。
10.如权利要求2所述的方法，其中所述第一有源电路层晶片包含SOI晶片。
11.如权利要求2所述的方法，其中所述接口晶片包含SOI晶片。
12.如权利要求2所述的方法，其中所述接口晶片进一步包括有源电路和/或无源电路元件。
13.如权利要求2所述的方法，其中所述接口晶片进一步包括解耦电容器和/或电压调节电路。
14.如权利要求2所述的方法，其中所述基底晶片包括逻辑电路。
15.一种用于制造3D集成电路结构的设备，所述设备包含：
配置为提供接口晶片的模块，所述接口晶片包括第一布线层和穿透硅通路；
配置为提供第一有源电路层晶片的模块，所述第一有源电路层晶片包括有源电路；
配置为将所述第一有源电路层晶片面朝下地接合至所述接口晶片的模块；
配置为在接合所述第一有源电路层晶片之后，移除所述第一有源电路层晶片的第一部分，以使得所述第一有源电路层晶片的第二部分保持附着至所述接口晶片的模块；
配置为提供基底晶片的模块，所述基底晶片包括第二布线层；
配置为将堆叠结构面朝下地接合至所述基底晶片的模块，所述堆叠结构包括所述接口晶片和所述第一有源电路层晶片的所述第二部分；和
配置为在接合所述堆叠结构之后，薄化所述接口晶片以形成接口层，以及形成金属化层于所述接口层上的模块，所述金属化层通过所述接口层中的所述穿透硅通路耦合至所述第一布线层，
其中所述接口晶片是由如下材料形成的，所述材料在移除所述第一有源电路层晶片的所述第一部分时使用的蚀刻剂中是不可溶的。
16.如权利要求15所述的设备，进一步包含：
配置为提供包括有源电路的另一有源电路层晶片的模块；
配置为将所述另一有源电路层晶片面朝下地接合于所述接口晶片和所述第一有源电路层晶片的所述第二部分之上的模块；和
配置为在接合所述另一有源电路层晶片之后，移除所述另一有源电路层晶片的第一部分，以使得所述另一有源电路层晶片的第二部分保持在所述接口晶片和所述第一有源电路层晶片的所述第二部分之上的模块，
其中面朝下地接合至所述基底晶片的所述堆叠结构还包括所述另一有源电路层晶片的所述第二部分。
17.如权利要求16所述的设备，进一步包含：
配置为重复提供另一有源电路层晶片、接合所述另一有源电路层晶片、和移除所述另一有源电路层晶片的第一部分N次的模块，
其中面朝下地接合至所述基底晶片的所述堆叠结构还包括另外N个有源电路层晶片的第二部分。
18.如权利要求16所述的设备，进一步包含：
配置为在移除所述另一有源电路层晶片的所述第一部分之后，在所述另一有源电路层晶片的所述第二部分上制造另一布线层的模块；和
配置为重复提供另一有源电路层晶片、接合所述另一有源电路层晶片、移除所述另一有源电路层晶片的第一部分和制造另一布线层N次的模块，
其中在将所述堆叠结构面朝下地接合至所述基底晶片时，将在所述第N个晶片的第二部分上的布线层面朝下地接合至所述基底晶片。
19.如权利要求16所述的设备，进一步包含：
配置为在移除所述第一有源电路层晶片的所述第一部分之后，在所述第一有源电路层晶片的所述第二部分上制造第三布线层的模块；和
配置为在移除所述另一有源电路层晶片的所述第一部分之后，在所述另一有源电路层晶片的所述第二部分上制造第四布线层的模块，
其中在接合所述另一有源电路层晶片时，将所述另一有源电路层晶片面朝下地接合至所述第三布线层，和
在接合所述堆叠结构时，将所述第四布线层面朝下地接合至所述基底晶片。
20.如权利要求15所述的设备，进一步包含：
配置为在移除所述第一有源电路层晶片的所述第一部分之后，在所述第一有源电路层晶片的所述第二部分上制造第三布线层的模块，
其中在接合所述堆叠结构时，将所述第三布线层面朝下地接合至所述基底晶片。
21.如权利要求15所述的设备，其中所述接口层上的所述金属化层包含焊料凸块。
22.如权利要求15所述的设备，其中所述接口晶片包含SOI晶片。
23.如权利要求15所述的设备，其中所述接口晶片进一步包括有源电路和/或无源电路元件。
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