WO2020077499A1 - 具有薄膜晶体管器件的集成装置及其制备方法 - Google Patents

具有薄膜晶体管器件的集成装置及其制备方法 Download PDF

Info

Publication number
WO2020077499A1
WO2020077499A1 PCT/CN2018/110277 CN2018110277W WO2020077499A1 WO 2020077499 A1 WO2020077499 A1 WO 2020077499A1 CN 2018110277 W CN2018110277 W CN 2018110277W WO 2020077499 A1 WO2020077499 A1 WO 2020077499A1
Authority
WO
WIPO (PCT)
Prior art keywords
groove
substrate
chip
integrated device
thin film
Prior art date
Application number
PCT/CN2018/110277
Other languages
English (en)
French (fr)
Inventor
王文轩
沈健
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN201880002041.0A priority Critical patent/CN109496353B/zh
Priority to PCT/CN2018/110277 priority patent/WO2020077499A1/zh
Publication of WO2020077499A1 publication Critical patent/WO2020077499A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • Embodiments of the present application relate to the field of electronics, and more specifically, to an integrated apparatus having a thin film transistor device and a method of manufacturing the same.
  • TFTs thin film transistors
  • the mutual interference between the pixels can be reduced and the stability of the picture can be improved.
  • the TFT technology using non-silicon substrates can fundamentally solve the cost problem of large-scale semiconductor integrated circuits.
  • the TFT technology can also realize large-area production, large-scale production, and integrated production of circuit devices (for example, the drive circuit region and the pixel region can be formed integrally). Therefore, TFT technology is widely used in the fields of flat panel displays and flat photoelectric sensors.
  • the line width and operating speed of the TFT are not as good as those of the integrated circuit. Therefore, it is necessary to externally connect a corresponding integrated circuit (Integrated Integrated Circuit (IC)) chip when driving the TFT array and reading signals.
  • IC integrated Circuit
  • the TFT array and the IC chip are connected through a flexible printed circuit (FPC), and then connected to external discrete devices through electrical connection components such as FPC and PCB. For example, power supply components.
  • each row and column of the TFT array needs to be connected to the IC chip. If there are 200 * 200 pixel units (generally display devices are much larger than this value), at least 400 terminals need to be connected to the IC chip. Therefore, the connection between the TFT array and the IC chip takes up too much space, and at the same time requires a large number of FPCs as the connection medium, which reduces the effective area of display or detection in the entire system structure, making the internal structure of the liquid crystal panel bloated and complicated.
  • an integrated device with a thin film transistor device and a preparation method thereof which can simplify and miniaturize the connection between a TFT array and an IC chip.
  • an integrated device including a thin film transistor device including:
  • the thin film transistor device is disposed above the etch barrier layer, and the substrate is disposed below the etch barrier layer;
  • the etching rate of the etching barrier layer is greater than the etching rate of the substrate.
  • At least one via penetrating through the etching barrier layer, the chip is disposed in the groove-like structure, and the chip is connected to the thin film transistor device through the at least one via hole.
  • the etching barrier layer covers at least the opening of the groove-like structure.
  • the thickness of the etch stop layer ranges from 400 nm to 500 nm.
  • the difference between the etching rate of the etching barrier layer and the etching rate of the substrate is greater than or equal to a preset value.
  • the material of the etch stop layer includes any one of the following materials:
  • Oxides, nitrides and organic materials are examples of materials.
  • a pad is provided in the via.
  • the material of the pad provided in the via hole is a metal material or conductive glass.
  • the thickness of the chip is less than or equal to the depth of the groove-like structure.
  • the depth of the groove-like structure is equal to the thickness of the substrate.
  • the angle formed by the side surface of the groove-like structure and the lower surface of the groove-like structure is greater than a preset angle.
  • the chip is provided with at least one pad.
  • the upper surface of the chip is provided with the at least one pad.
  • the at least one pad and the at least one via correspond to each other.
  • the chip includes a data driving chip, and the data driving chip is connected to the electrode layer in the thin film transistor device through the at least one via.
  • the chip includes a scan driving chip, and the scan driving chip is connected to the electrode layer in the thin film transistor device through the at least one via.
  • the integrated device further includes:
  • Filling material in the groove-like structure is used to fix the chip in the groove-like structure.
  • the difference between the thermal expansion coefficient of the filler material and the thermal expansion coefficient of the substrate is less than or equal to a preset threshold.
  • the filler material and the substrate material are the same material.
  • the filler material can flow before curing.
  • the filling material completely fills the groove-like structure.
  • the filling material partially fills the groove-like structure.
  • the thin film transistor device includes:
  • connection layer connected to the external device and / or the pad in the via.
  • the integrated device further includes:
  • a photodiode which is disposed above the etching barrier layer, and the photodiode is connected to the electrode layer in the thin film transistor device.
  • the material used for the substrate is glass material or polyimide material.
  • the integrated device further includes:
  • connection end the at least one connection end is used for electrical connection with an external device, and the at least one connection end is disposed above the substrate.
  • one of the at least one connecting end is connected to a pad provided in one of the at least one via.
  • the at least one second connection terminal is connected to the electrode layer in the thin film transistor device.
  • the second connection end is a pad or a solder ball.
  • a display device including:
  • an electronic device including:
  • a method for preparing an integrated device including a thin film transistor device including:
  • An etching barrier layer is provided on the upper surface of the substrate
  • At the bottom of the groove-like structure at least one via hole penetrating the etching barrier layer is provided;
  • a thin film transistor device is provided above the etch barrier layer, wherein the chip is connected to the thin film transistor device through the at least one via.
  • the providing an etch stop layer on the upper surface of the substrate includes:
  • the etch barrier layer is provided on the upper surface of the substrate.
  • the forming of a groove-like structure on the lower surface of the substrate includes:
  • the groove-like structure is formed by an etching process.
  • the etching process includes at least one of the following processes:
  • Dry etching process, wet etching process and laser etching process dry etching process, wet etching process and laser etching process.
  • the etching barrier layer covers at least the opening of the groove-like structure.
  • the thickness of the etch stop layer ranges from 400 nm to 500 nm.
  • the difference between the etching rate of the etching barrier layer and the etching rate of the substrate under the same etching conditions is greater than or equal to a preset value.
  • the material of the etch stop layer includes any one of the following materials:
  • Oxides, nitrides and organic materials are examples of materials.
  • a pad is provided in the via.
  • the material of the pad provided in the via hole is a metal material or conductive glass.
  • the thickness of the chip is less than or equal to the depth of the groove-like structure.
  • the depth of the groove-like structure is equal to the thickness of the substrate.
  • the angle formed by the side surface of the groove-like structure and the lower surface of the groove-like structure is greater than a preset angle.
  • At the bottom of the groove-like structure, at least one via hole penetrating the etch barrier layer includes:
  • the at least one via is etched to form the at least one via.
  • the method further includes:
  • a pad is provided in the via.
  • the material of the pad provided in the via hole is a metal material or conductive glass.
  • the thickness of the chip is less than or equal to the depth of the groove-like structure.
  • the depth of the groove-like structure is equal to the thickness of the substrate.
  • the chip is provided with at least one pad.
  • the at least one pad is provided on the upper surface of the chip.
  • the at least one pad and the at least one via correspond to each other.
  • the chip includes a data driving chip, and the data driving chip is connected to the electrode layer in the thin film transistor device through the at least one via.
  • the chip includes a scan driving chip, and the scan driving chip is connected to the electrode layer in the thin film transistor device through the at least one via.
  • the method further includes:
  • the groove structure is filled with a filling material, and the filling material is used to fix the chip in the groove structure.
  • the difference between the thermal expansion coefficient of the filler material and the thermal expansion coefficient of the substrate is less than or equal to a preset threshold.
  • the filler material and the substrate material are the same material.
  • the filler material can flow before curing.
  • the filling the groove-shaped structure with a filling material includes:
  • the groove-shaped structure is completely filled with the filling material.
  • the filling the groove-shaped structure with a filling material includes:
  • the groove-shaped structure is partially filled with a filling material.
  • the method further includes:
  • connection layer is provided in the thin film transistor device, and the connection layer is connected to an external device and / or the at least one via.
  • the method further includes:
  • a photodiode is provided above the substrate, and the photodiode is connected to the electrode layer in the thin film transistor device.
  • the material used for the substrate is glass material or polyimide material.
  • the method further includes:
  • At least one second connection end is provided above the substrate, and the at least one second connection end is used for electrical connection with external devices.
  • one of the at least one second connection end is connected to a connection line in the at least one via.
  • the at least one second connection terminal is connected to the electrode layer in the thin film transistor device.
  • the second connection end is a pad or a solder ball.
  • a display device including:
  • An integrated device prepared according to the method for preparing an integrated device described in the fourth aspect or any possible implementation manner of the fourth aspect.
  • an electronic device including:
  • the display device according to the fifth aspect.
  • the integration device and the method for preparing the integration device integrate the chip for controlling the thin film transistor device in the substrate of the thin film transistor device, which not only prevents the chip from occupying the thin film transistor device
  • the working area can also greatly reduce the external connection terminals of the integrated device, thereby effectively simplifying the overall structure of the integrated device.
  • FIG. 1 is an exemplary side cross-sectional view of an integrated apparatus including a thin film transistor device according to an embodiment of the present application.
  • FIG 2 is another exemplary side cross-sectional view of an integrated apparatus including a thin film transistor device according to an embodiment of the present application.
  • FIG 3 is an exemplary plan cross-sectional view of an integrated device including a thin film transistor device according to an embodiment of the present application.
  • FIG. 4 is an exemplary process flow diagram of a method for manufacturing an integrated device according to an embodiment of the present application.
  • FIG. 5 is an exemplary side cross-sectional view of a structure formed after an etching barrier layer is provided on a substrate.
  • FIG. 6 is an exemplary side cross-sectional view of a structure formed by notching the lower surface of the base in the structure shown in FIG. 5.
  • FIG. 7 is an exemplary side cross-sectional view of a structure formed after at least one via hole is provided on an etch barrier layer in the structure shown in FIG. 6.
  • FIG. 8 is an exemplary side cross-sectional view of a structure after a pad is provided in at least one via in the structure shown in FIG. 7.
  • FIG. 9 is an exemplary side cross-sectional view formed by disposing a chip in a groove-like structure in the structure shown in FIG. 8.
  • FIG. 10 is an exemplary side cross-sectional view of a structure formed after a thin film transistor device is provided on the lower surface of an etch barrier layer in the structure shown in FIG. 9.
  • FIG. 11 is an exemplary cross-sectional view of a structure formed after filling the groove-like structure in the structure shown in FIG. 9.
  • FIG. 12 is an exemplary side cross-sectional view of a structure formed after a thin film transistor device is provided on the upper surface of the etch barrier layer in the structure shown in FIG. 5.
  • FIG. 13 is an exemplary side cross-sectional view of a structure formed by performing a groove treatment on the lower surface of the substrate in the structure shown in FIG. 12.
  • FIG. 14 is an exemplary side cross-sectional view of a structure formed after at least one via hole is provided on the etch barrier layer in the structure shown in FIG. 13.
  • FIG. 15 is an exemplary side cross-sectional view of a structure after a pad is provided in at least one via in the structure shown in FIG. 14.
  • FIG. 16 is an exemplary side cross-sectional view formed by disposing a chip in a groove-like structure in the structure shown in FIG. 15.
  • Embodiments of the present application provide an integrated device including a thin film transistor device and a method for manufacturing the same.
  • the integrated device may include multiple TFTs.
  • the TFT device is also called a TFT array , TFT array device or photoelectric sensor.
  • the TFT device of the embodiment of the present application can simplify and miniaturize the connection between the TFT device and the IC chip.
  • the integrated device in the embodiments of the present application can be applied to the field of TFT flat panel display, TFT-based flat panel sensors, and other products and applications based on TFT processes.
  • the TFT device can be applied to an optoelectronic display device having an active matrix or a self-luminous optoelectronic display device.
  • an optoelectronic display device having an active matrix or a self-luminous optoelectronic display device.
  • the integrated device may serve as an optical biometric sensor, such as an optical fingerprint sensor, for implementing biometric sensing operations.
  • an optical biometric sensor such as an optical fingerprint sensor
  • the integrated device receives the optical signal formed by the reflection of the finger, and converts the optical signal into an electrical signal, which can reflect the fingerprint of the user's finger information.
  • the area where the integrated device is located is the sensing area of the integrated device.
  • the sensing area may be located below the display area of the display screen. Therefore, when the user needs to unlock the terminal device or verify other biometrics, he only needs to press his finger on the display screen, located at the The integrated device in the sensing area can perform fingerprint sensing operation.
  • the application of this embodiment does not specifically limit the light emitting source of the optical signal used for fingerprint recognition.
  • the light-emitting source may be light emitted by light-emitting pixels in the display screen, or may be light emitted by a backlight source below the display screen, and the backlight source may be light emitted by an LED wick.
  • the LED wick may include: Red LED wick, blue LED wick, green LED wick, infrared LED wick, ultraviolet LED wick and white LED wick. It should be understood that the embodiments of the present application do not limit the types of LED wicks specifically included in the LED wick, and different types of LED wicks can be matched according to specific applications.
  • the integrated device as an optical fingerprint sensor is only an example, and in other alternative embodiments, the integrated device may also be applied to color document scanning, vein imaging, and counterfeit banknote recognition.
  • the embodiments of the present application do not specifically limit the use of the integrated device.
  • FIG. 1 is an exemplary block diagram of an integrated apparatus including a thin film transistor device according to an embodiment of the present application.
  • the integrated device may include:
  • the substrate 100, the chip 103, the etch stop layer 114 and the thin film transistor device 105 are formed.
  • the thin film transistor device 105 is disposed above the etch stop layer 114, and the substrate 100 is disposed below the etch stop layer 114.
  • the etching rate of the etching barrier layer 114 is greater than the etching rate of the substrate 100.
  • a groove-shaped structure 101 is formed on the lower surface of the substrate 100 extending upward.
  • At the bottom of the groove-shaped structure 101 is provided with at least one via 102 penetrating the etch barrier 114, for example, between the bottom of the groove-shaped structure 101 and the upper surface of the etch barrier 114 are formed at least One via 102.
  • the chip is disposed in the groove-like structure, and the chip is connected to the thin film transistor device through the at least one via 102.
  • a groove process may be performed on a part of the lower surface of the substrate 100 of the integrated device to form the groove-like structure 101 shown in FIG. 1.
  • a metal electrical connection layer ie, a pad provided in at least one via 102 shown in FIG. 1 is arranged in the groove-shaped structure 101.
  • the chip 103 is installed in the groove-like structure 101, and is electrically connected to the at least one via 102 through the metal electrical connection layer.
  • the electrode layer of the thin film transistor device 105 prepared on the substrate is also connected to the at least one via 102.
  • the connection between the chip 103 and the thin film transistor device 105 is achieved.
  • the integration device in the embodiment of the present application integrates the chip 103 for controlling the thin film transistor device 105 in the substrate 100 of the thin film transistor device 105, which not only avoids the chip 103 occupying the effective working area of the TFT, but also can The amplitude reduces the external connection terminals of the integrated device, thereby effectively simplifying the overall structure of the integrated device.
  • the material of the substrate 100 may be a standard substrate material involved in the TFT process, such as a glass material or a polyimide material. It should be understood that the embodiment of the present application does not limit the specific material model of the substrate 100.
  • the material of the substrate 100 when it is a glass material, it may be alkali-free glass. Since the strain temperature of the alkali-free glass can be higher than 625 ° C, the substrate 100 can have good chemical stability.
  • the material of the substrate 100 may be a light-transmitting material, thereby ensuring The light emitted by the backlight can be transmitted to the display screen through the substrate 100.
  • the substrate 100 may be a glass substrate.
  • the material of the substrate 100 may also be other light-transmitting materials such as light-transmitting plastics.
  • the material of the etch stop layer 114 includes any one of the following materials:
  • Oxides, nitrides and organic materials are examples of materials.
  • the material of the etch stop layer 114 may be silicon nitride.
  • the thickness of the etch stop layer 114 ranges from 400 nm to 500 nm.
  • the thermal expansion coefficient of the material of the etch stop layer 114 is similar to the thermal expansion coefficient of the substrate 100.
  • the difference between the thermal expansion coefficient of the material of the etch stop layer 114 and the thermal expansion coefficient of the substrate 100 is less than or equal to a preset value.
  • the difference between the etching rate of the etching barrier layer 114 and the etching rate of the substrate 100 under the same etching conditions is greater than or equal to a preset value.
  • the material of the etch stop layer 114 is a transparent material.
  • the chip 103 may be a chip processed through a redistribution layer (RDL) process and a micro-bump process.
  • RDL redistribution layer
  • the chip 103 may be a flip chip (Flip Chip).
  • the chip 103 may be a plurality of chips arranged along the parallel direction and / or the vertical direction of the upper surface of the substrate 100. That is, a plurality of chips arranged along the parallel direction and / or the vertical direction of the upper surface of the substrate 100 can be packaged in the groove-like structure 101.
  • signals can be transmitted between the multiple chips 103 through electrical connection.
  • the depth of the groove-like structure is equal to the thickness of the substrate. Therefore, the difficulty in the process of providing the at least one opening can be effectively reduced.
  • the depth of the groove-like structure 101 is greater than 100 microns (um). Further, the at least one opening also needs to penetrate a part of the base between the bottom of the groove-like structure 101 and the upper surface of the base 100.
  • the angle formed by the side surface of the groove-like structure and the lower surface of the groove-like structure is greater than a preset angle, thereby reducing the installation of the chip 103 on the The operation difficulty when the groove-shaped structure 101 is described.
  • the etch stop layer 114 covers at least the opening of the groove-like structure 101.
  • the thickness of the chip 103 is less than or equal to the depth of the groove-like structure 101, thereby ensuring that the chip 103 can be completely integrated in the substrate 100.
  • the maximum width of the etching barrier layer 114 in the plane of the upper surface of the substrate 100 is greater than the maximum width of the opening of the groove-like structure 101 in the plane of the upper surface of the substrate 100.
  • the width of the etching barrier layer 114 in the plane of the upper surface of the substrate 100 is greater than the width of the opening of the groove-like structure 101 in the plane of the upper surface of the substrate 100 .
  • the base 100 may also be referred to as a substrate 100 or a substrate 100.
  • the thin film transistor device 105 in the embodiments of the present application may be various thin films prepared on the substrate 100.
  • a semiconductor active layer for example, a semiconductor active layer, a dielectric layer, and a metal electrode layer.
  • the embodiment of the present application does not specifically limit the manufacturing process of the thin film transistor device 105.
  • the manufacturing process of the thin film transistor device 105 may be a manufacturing process in the prior art.
  • FIG. 2 is an exemplary cross-sectional view of the thin film transistor device 105 of the embodiment of the present application.
  • the thin film transistor device 105 may be a thin film transistor device having a bottom gate structure.
  • the gate electrode 106 of the thin film transistor device 105 may be connected to the chip 103, and the chip 103 is also connected to an external power supply, which is used to provide a scanning voltage for the thin film transistor device 105 .
  • the drain 109 of the thin film transistor device 105 may be connected to the internal device of the thin film transistor device 105, the source 108 of the thin film transistor device may be connected to at least one via 102 shown in FIG. 1, the thin film transistor A channel region 107 exists between the drain 109 of the device 105 and the source 108 of the thin film transistor device 105.
  • the material of the channel region 107 includes but is not limited to: amorphous silicon (a-Si) material, indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), And low temperature poly-silicon (LTPS).
  • a-Si amorphous silicon
  • IGZO Indium Gallium Zinc Oxide
  • LTPS low temperature poly-silicon
  • light-transmitting materials such as indium tin oxide or zinc oxide.
  • the thin film transistor device 105 may further include: a dielectric layer 111.
  • the dielectric layer includes but is not limited to: insulating dielectric layers such as oxides and nitrides.
  • the integrated device may further include a photodiode 110.
  • the photodiode 110 is a key element for implementing photoelectric conversion in various photoelectric detection systems.
  • the photodiode 110 is used to convert optical signals (for example, infrared light signals, visible light signals, and ultraviolet light signals) into electrical signals. Further, the photodiode 110 may send the converted electrical signal to the thin film transistor formed by the substrate 100 and the thin film transistor device 105, and the thin film transistor outputs the electrical signal. It should be understood that, in other embodiments, the photodiode 110 is also called a photoelectric sensing unit or a photodetector.
  • the photodiode 110 may be disposed above the substrate 100, and the photodiode 110 is connected to the electrode layer in the thin film transistor device 105.
  • the photodiode 110 is connected to the drain electrode 109 of the electrode layer in the thin film transistor device 105.
  • the integrated device shown in FIG. 1 may include a plurality of photodiodes 110 shown in FIG. 2, and the plurality of photodiodes 110 may be distributed in an array.
  • Each photodiode 110 is connected to a drain of the electrode layer of the thin film transistor device 105.
  • the structure and specific material composition of the photodiode 110 may be determined according to parameters such as the wavelength range of light to be detected, process capability, and the like.
  • the embodiments of the present application are not limited to this.
  • the photodiode 110 may be a PIN-type photodiode or a PN-type photodiode.
  • the photodiode 110 may include a bottom-up N-type doped semiconductor layer, an intrinsic semiconductor layer, and a P-type doped semiconductor layer.
  • the N-type doped semiconductor layer serves as the cathode of the photodiode 110
  • the intrinsic semiconductor layer serves as the light absorbing layer of the photodiode 110
  • the P-type doped semiconductor layer serves as the anode of the photodiode 110.
  • the PIN-type photodiode may also be called a PIN junction diode or a PIN diode.
  • the thin film transistor device 105 may further include:
  • connection layer 112 is connected to an external device and / or the at least one via 102.
  • the connection layer 112 can not only realize the connection between the various layers inside the thin film transistor device 105, but also can realize the connection between the thin film transistor device 105 and the external device and the chip 103 and the external device Connection, which in turn realizes the electrical interconnection function of the integrated device.
  • the chip 103 and the thin film transistor device 105 can realize electrical interconnection and signal transmission with other peripheral circuits or other elements of the device to which the chip 103 belongs through the connection layer 112.
  • connection layer 112 may be metal or a transparent conductive material such as ITO.
  • the embodiment of the present application does not specifically limit the specific material of the connection layer 112.
  • connection requirements between the layers in the thin film transistor device 105, the connection requirements between the layers in the thin film transistor device and the chip 103, and the inside of the thin film transistor device 105 The connection requirements of each layer with external devices determine the number of layers of the connection layer 112. However, the embodiment of the present application does not limit the specific number of the connection layer 112.
  • connection layer 112 may be drawn from the upper surface of the substrate 100, or the connection layer 112 may be drawn from any layer of the thin film transistor device 105.
  • the material of the connection layer 112 may be a transparent conductive material. For example ITO. This ensures the normal transmission of light.
  • a pad 115 may be provided in the via hole 102.
  • the material of the pad 115 provided in the via hole 102 is a metal material or conductive glass.
  • At least one pad is provided on the chip 103.
  • the at least one pad 104 is provided on the upper surface of the chip 103.
  • the at least one pad 104 may be uniformly or unevenly distributed on the upper surface of the chip 103.
  • the at least one pad 104 and the at least one via 102 have a one-to-one correspondence.
  • the at least one via 102 may be arranged according to the arrangement of the at least one pad 104.
  • the chip 103 integrated in the substrate 100 and the external device and the thin film transistor device 105 can be electrically connected through the at least one pad 104 and the at least one via 102.
  • the embodiment of the application does not limit the specific form of the at least one pad 104.
  • the at least one pad 104 may be a solder joint or a solder ball or any form of connection terminal for electrically connecting with a flexible printed circuit (FPC).
  • FPC flexible printed circuit
  • the chip 103 in the embodiment of the present application may be a chip having pads (Pad) prepared on one surface before entering the integrated process flow, for example, the pad 104 shown in FIG.
  • the pad 104 is electrically connected to the thin film transistor device 105 through the at least one via 102.
  • the pad 104 can be understood as a pin connecting the chip 103 to the outside world.
  • the upper surface of the chip 103 is the side where the pad has been prepared before entering the integrated process flow, and the side opposite to the lower surface of the chip 103 is the lower surface of the chip 103.
  • the pad 104 shown in FIG. 1 located on the upper surface of the chip 103 is only an example, and the embodiments of the present application are not limited thereto.
  • the at least one pad may be provided on the lower surface or side surface of the chip 103.
  • the chip 103 includes a data driving chip, and the data driving chip may be connected to the electrode layer in the thin film transistor device 105 through the at least one via 102.
  • the data driving chip may be connected to the source electrode in the electrode layer through the at least one via hole 102.
  • the chip 103 includes a scan driving chip, and the scan driving chip is connected to the electrode layer in the thin film transistor device 105 through the at least one via 102.
  • the scan driving chip may be connected to the gate electrode in the electrode layer through the at least one via hole 102.
  • the integrated device further includes:
  • Filling material in the groove-like structure is used to fix the chip in the groove-like structure.
  • the difference between the coefficient of thermal expansion (CTE) of the filler material and the coefficient of thermal expansion of the substrate 100 is less than or equal to a preset threshold.
  • the filling material and the material of the substrate 100 may be the same material.
  • the filler material may be an epoxy compound (Epoxy Molding Compound) (EMC) material.
  • EMC epoxy Molding Compound
  • the filling material may flow before curing, thereby ensuring that the filling material is filled into the groove-shaped structure 101 and cured, the The upper surface of the filler material is a flat surface.
  • a pad is prepared on the upper surface of the chip 103 before entering the integrated process flow, for bonding to the bottom of the groove-like structure 101 of the substrate 100.
  • the embodiments of the present application are not limited to this.
  • the chip 103 shown in FIG. 1 may also be prepared with pads on the lower surface of the chip, thereby, when the chip 103 is fixed into the groove-like structure 101, The lower surface can be attached to the bottom of the groove-like structure 101.
  • the filling material completely fills the groove-like structure.
  • the filling material partially fills the groove-like structure.
  • 3 is a plan cross-sectional view of the integrated device of an embodiment of the present application.
  • the integrated device further includes at least one connection terminal 113, and the at least one connection terminal 113 is used to electrically connect with an external device, and the at least one The connection terminal 113 is disposed above the substrate 100.
  • the at least one connection terminal 113 enables electrical interconnection and signal transmission between the internal circuit of the integrated device and other peripheral circuits or other elements of the device to which the integrated device belongs.
  • one connecting end 113 of the at least one connecting end 113 is connected to one connecting line 102 in the at least one via 102.
  • the at least one connection terminal 113 is connected to the electrode layer in the thin film transistor device 105.
  • connection end is a pad or a solder ball.
  • the integrated device includes six chips 103 and each chip 103 is connected to a connection terminal 113 through a connection line 102, but the embodiment of the present application is not limited thereto.
  • an embodiment of the present application further provides a display device, and the display device may include the above integrated device.
  • the display device may include the above integrated device.
  • a liquid crystal display device for example, a liquid crystal display device.
  • the liquid crystal display device may include a liquid crystal panel and a backlight module for providing a light source to the liquid crystal panel.
  • the liquid crystal panel may include the above-mentioned TFT device (including a plurality of thin film transistors), and horizontal and vertical scan lines and data lines.
  • the scan lines of each row control the gates of the TFTs of one row, and the data lines of each column are connected
  • the drain of each TFT is connected to a pixel electrode to form a pixel capacitor.
  • the pixel capacitor includes opposing pixel electrodes and a common electrode.
  • the pixel electrode is connected to the drain of the TFT.
  • the common electrode can be connected to a constant Voltage signal.
  • the liquid crystal molecules are filled between the pixel electrode and the common electrode, and the voltage difference between the pixel electrode and the common electrode can be controlled by adjusting the output voltage of the data line, thereby adjusting the deflection angle of the liquid crystal molecules and controlling the luminous flux.
  • an embodiment of the present application further provides an electronic device, and the electronic device may include the foregoing display device.
  • the electronic device may be a terminal device such as a TV, mobile phone, tablet computer, or e-book.
  • FIG. 4 is a schematic flowchart of a method for preparing an integrated device according to an embodiment of the present application. It should be understood that the method 200 shown in FIG. 4 may be used to prepare the integrated device shown in FIGS. 1 to 3. The method 200 shown in FIG. 4 can also prepare the integrated device shown in FIGS. 1 to 3 corresponding to the sequence of FIGS. 5 to 10 and 1. The method for preparing an integrated device according to an embodiment of the present application will be described below with reference to FIGS. 1, 4 to 10.
  • the method 200 may include:
  • an etching barrier layer is provided on the upper surface of the substrate.
  • FIG. 5 is an exemplary side cross-sectional view of a structure formed after an etching barrier layer is provided on a substrate. As shown in FIG. 5, the upper surface of the substrate 100 is provided with an etch stop layer 114.
  • the S120 may specifically include:
  • the etching barrier layer is provided on the upper surface of the substrate.
  • the deposition method includes but is not limited to:
  • PVD Physical vapor deposition
  • CVD chemical vapor deposition
  • the etching barrier layer covers at least the opening of the groove-like structure.
  • the thickness of the etch stop layer ranges from 400 nm to 500 nm.
  • the difference between the etching rate of the etching barrier layer and the etching rate of the substrate under the same etching conditions is greater than or equal to a preset value.
  • the material of the etch stop layer includes any one of the following materials:
  • Oxides, nitrides and organic materials are examples of materials.
  • a groove-like structure is formed on the lower surface of the substrate.
  • the S220 may specifically include:
  • the position of the groove-like structure is determined by a photolithography process; at the position of the groove-like structure, the groove-like structure is formed by an etching process.
  • FIG. 6 is an exemplary side cross-sectional view of a structure formed by grooving the lower surface of the substrate in the structure shown in FIG. 5.
  • the structure shown in FIG. 5 may be turned upside down to form the groove-like structure 101 shown in FIG. 6 on the lower surface shown in FIG. 5.
  • the etching process includes at least one of the following processes:
  • Dry etching process, wet etching process and laser etching process dry etching process, wet etching process and laser etching process.
  • the dry etching process may include at least one of the following etching processes:
  • etching reactive ion etching
  • chemical dry etching chemical dry etching
  • plasma etching plasma etching
  • CF4 tetrafluoromethane
  • SF6 sulfur hexafluoride
  • the etching rate can also be changed by changing the mixing ratio of the etching gas.
  • the chemical raw material of the wet etching process may include, but is not limited to, an etching solution containing hydrofluoric acid.
  • an etching method combining dry etching and wet etching, or a laser etching method combined with wet etching can be used to effectively ensure the shape of the etching And the flatness of the bottom.
  • the depth of the groove-like structure is equal to the thickness of the substrate.
  • the angle formed by the side of the groove-like structure and the lower surface of the groove-like structure is greater than a preset angle.
  • At least one via hole penetrating the etching barrier layer is provided at the bottom of the groove-like structure.
  • the S230 may specifically include:
  • the position of the at least one via hole is determined on the etching barrier layer by a photolithography process; etching is performed at the position of the at least one via hole to form the at least one via hole.
  • FIG. 7 is an exemplary side cross-sectional view of a structure formed after at least one via hole is provided on the etch barrier layer in the structure shown in FIG. 6. As shown in FIG. 7, at least one via 102 may be provided between the bottom of the groove-like structure 101 and the lower surface of the etch stop layer 114.
  • the method 200 shown in FIG. 4 may further include:
  • a pad is provided in the via.
  • FIG. 8 is an exemplary side cross-sectional view of a structure after a pad is provided in at least one via in the structure shown in FIG. 7.
  • the pad 115 shown in FIG. 8 may be directly provided in the via hole 102 shown in FIG. 7.
  • the material of the pad provided in the via hole is a metal material or conductive glass.
  • FIG. 9 is an exemplary side cross-sectional view formed by disposing a chip in a groove-like structure in the structure shown in FIG. 8. As shown in FIG. 9, the pad 104 on the chip 103 and the pad 115 provided in the via 102 may be fixedly connected.
  • the chip may be fixedly disposed in the groove-like structure by bonding with the at least one via.
  • the thickness of the chip is less than or equal to the depth of the groove-like structure.
  • the chip is provided with at least one pad.
  • the at least one pad is provided on the upper surface of the chip.
  • the at least one pad and the at least one via are in one-to-one correspondence.
  • the chip includes a data driving chip, and the data driving chip is connected to the electrode layer in the thin film transistor device through the at least one via.
  • the chip includes a scan driving chip, and the scan driving chip is connected to the electrode layer in the thin film transistor device through the at least one via.
  • a thin film transistor device is provided above the etch barrier layer, wherein the chip is connected to the thin film transistor device through the at least one via.
  • FIG. 10 is an exemplary side cross-sectional view of a structure formed after a thin film transistor device is provided on the lower surface of the etch stop layer in the structure shown in FIG. 9.
  • a thin film transistor device 105 may be provided above the etch stop layer 114 shown in FIG. 9.
  • the specific process of arranging the thin film transistor device above the substrate includes but is not limited to: a TFT process based on amorphous silicon (a-Si), a low temperature polysilicon (LTPS) TFT technology of technology and TFT technology based on Indium Gallium Zinc Oxide (IGZO).
  • a-Si amorphous silicon
  • LTPS low temperature polysilicon
  • IGZO Indium Gallium Zinc Oxide
  • the uses of the thin film transistor device may include, but are not limited to: flat panel display devices, photoelectric flat panel sensing devices, or temperature flat panel sensing devices.
  • the method 200 may further include:
  • the groove structure is filled with a filling material, and the filling material is used to fix the chip in the groove structure.
  • FIG. 11 is an exemplary cross-sectional view of a structure formed after filling the groove-like structure in the structure shown in FIG. 9.
  • the groove-shaped structure shown in FIG. 9 may be directly filled with the filling material, thereby forming the structure shown in FIG. 11.
  • the thin film transistor device 105 when preparing an integrated device, the thin film transistor device 105 may be filled with the filling material first, or the thin film transistor device 105 may be set to be filled with the filling material first. The embodiment does not specifically limit this.
  • the difference between the thermal expansion coefficient of the filler material and the thermal expansion coefficient of the substrate is less than or equal to a preset threshold.
  • the filler material and the substrate material are the same material.
  • the filler material may flow before curing.
  • the groove-shaped structure is completely filled with the filling material.
  • the groove-shaped structure is partially filled with a filling material.
  • the method 200 may further include:
  • connection layer is provided in the thin film transistor device, and the connection layer is connected to an external device and / or the at least one via.
  • connection layer 112 may be provided in the thin film transistor device 105.
  • the method 200 may further include:
  • a photodiode is provided above the substrate, and the photodiode is connected to the electrode layer in the thin film transistor device.
  • the material used for the substrate is glass material or polyimide material.
  • the method 200 may further include:
  • At least one second connection end is provided above the substrate, and the at least one second connection end is used for electrical connection with external devices.
  • one of the at least one second connection end is connected to a connection line in the at least one via.
  • the at least one second connection terminal is connected to the electrode layer in the thin film transistor device.
  • the second connection end is a pad or a solder ball.
  • the above-mentioned embodiments of the method 200 for preparing an integrated device may be executed by a robot or a CNC machining method, and the device software or process for performing the method 200 may be executed by executing a computer program stored in a memory Code to perform the above method 200.
  • FIG. 12 is an exemplary side cross-sectional view of a structure formed after a thin film transistor device is provided on the upper surface of the etch stop layer in the structure shown in FIG. 5.
  • 13 is an exemplary side cross-sectional view of a structure formed by performing a groove treatment on the lower surface of the substrate in the structure shown in FIG. 12.
  • 14 is an exemplary side cross-sectional view of a structure formed after at least one via hole is provided on the etch barrier layer in the structure shown in FIG. 13.
  • 15 is an exemplary side cross-sectional view of a structure after a pad is provided in at least one via in the structure shown in FIG. 14.
  • FIG. 16 is an exemplary side cross-sectional view formed by disposing a chip in a groove-like structure in the structure shown in FIG. 15.
  • the integrated device may also be prepared according to the process sequence of FIG. 5, FIG. 12 to FIG. 16, and FIG. 1.
  • the disclosed integrated device, components in the integrated device, and method of preparing the integrated device may be implemented in other ways.
  • the above-described integrated device embodiments are only exemplary.
  • the division of the components is only a division of logical functions.
  • there may be other divisions for example, multiple components or components may be combined Or it can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or components, and may be in electrical, mechanical, or other forms.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Human Computer Interaction (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

提供了一种具有薄膜晶体管器件的集成装置及其制备方法。所述集成装置包括：基底、芯片、刻蚀阻挡层和薄膜晶体管器件；所述薄膜晶体管器件设置在所述刻蚀阻挡层的上方，所述基底设置在所述刻蚀阻挡层的下方；在同一刻蚀条件下所述刻蚀阻挡层的刻蚀速率大于所述基底的刻蚀速率，所述基底的下表面向上延伸形成有槽状结构，所述槽状结构的底部设置有贯通所述刻蚀阻挡层的至少一个过孔，所述芯片设置在所述槽状结构内，所述芯片通过所述至少一个过孔连接至所述薄膜晶体管器件。本申请提供的集成装置，通过基底和薄膜晶体管器件形成薄膜晶体管(TFT)，并进一步地，使得用于控制TFT的芯片集成在TFT的基底内，能够有效简化集成装置的整体结构。

Description

具有薄膜晶体管器件的集成装置及其制备方法 技术领域
本申请实施例涉及电子领域，并且更具体地，涉及具有薄膜晶体管器件的集成装置及其制备方法。
背景技术
目前，由于将薄膜晶体管(Thin film transistor，TFT)制作在液晶面板中，可以减少各像素间的互相干扰并提升画面的稳定度。进一步地，采用非硅基底(如玻璃基底，有机高分子基底等)的TFT技术能够从根本上解决了大规模半导体集成电路的成本问题。此外，由于TFT技术也能够实现大面积生产、规模化生产以及电路器件一体化生产(例如，可以一体形成驱动电路区域和像素区域)。因此，TFT技术被广泛应用于平板显示以及平面光电传感器等领域。
但是，由于TFT工艺本身的局限性，使得TFT的线宽、工作速度等性能都不及集成电路。因此，在进行TFT阵列的驱动以及信号读取的工作时需要外接相应的集成电路(Integrated Circuit，IC)芯片。通常TFT阵列与IC芯片通过柔性电路板(Flexible Printed Circuit，FPC)进行连接，然后再通过FPC和PCB等的电气连接部件连接至外部分立器件。例如，电源部件等。
具体地，TFT阵列的每行与每列都需要与IC芯片进行连接，假如共有200*200个像素单元(一般显示器件远远大于此数值)，至少有400个端子要与IC芯片进行连接，因此，TFT阵列在与IC芯片之间的连接会占用过大的空间，同时需要大量FPC作为连接介质，降低了整个系统结构中显示或探测的有效面积，使得液晶面板的内部结构臃肿繁杂。
因此，如何精简化、小型化TFT阵列在与IC芯片之间的连接是本领域当前急需解决的技术问题。
发明内容
提供了一种具有薄膜晶体管器件的集成装置及其制备方法，能够精简化、小型化TFT阵列在与IC芯片之间的连接。
第一方面，提供了一种包括薄膜晶体管器件的集成装置，包括：
基底、芯片、刻蚀阻挡层和薄膜晶体管器件；
所述薄膜晶体管器件设置在所述刻蚀阻挡层的上方，所述基底设置在所述刻蚀阻挡层的下方；
其中，在同一刻蚀条件下所述刻蚀阻挡层的刻蚀速率大于所述基底的刻蚀速率，所述基底的下表面向上延伸形成有槽状结构，所述槽状结构的底部设置有贯通所述刻蚀阻挡层的至少一个过孔，所述芯片设置在所述槽状结构内，所述芯片通过所述至少一个过孔连接至所述薄膜晶体管器件。
在一些可能的实现方式中，所述刻蚀阻挡层至少覆盖所述槽状结构的开口。
在一些可能的实现方式中，所述刻蚀阻挡层的厚度范围为400nm～500nm。
在一些可能的实现方式中，在同一刻蚀条件下所述刻蚀阻挡层的刻蚀速率和所述基底的刻蚀速率之间的差值大于或等于预设值。
在一些可能的实现方式中，所述刻蚀阻挡层的材料包括以下材料中的任一种：
氧化物、氮化物以及有机材料。
在一些可能的实现方式中，所述过孔内设置有焊盘。
在一些可能的实现方式中，所述过孔内设置的焊盘的材料为金属材料或导电玻璃。
在一些可能的实现方式中，所述芯片的厚度小于或等于所述槽状结构的深度。
在一些可能的实现方式中，所述槽状结构的深度等于所述基底的厚度。
在一些可能的实现方式中，所述槽状结构的侧面与所述槽状结构的下表面形成的角度大于预设角度。
在一些可能的实现方式中，所述芯片设置有至少一个焊盘。
在一些可能的实现方式中，所述芯片的上表面设置有所述至少一个焊盘。
在一些可能的实现方式中，所述至少一个焊盘和所述至少一个过孔一一对应。
在一些可能的实现方式中，所述芯片包括数据驱动芯片，所述数据驱动芯片通过所述至少一个过孔连接至所述薄膜晶体管器件内的电极层。
在一些可能的实现方式中，所述芯片包括扫描驱动芯片，所述扫描驱动芯片通过所述至少一个过孔连接至所述薄膜晶体管器件内的电极层。
在一些可能的实现方式中，所述集成装置还包括：
所述槽状结构内的填充材料，所述填充材料用于将所述芯片固定在所述槽状结构内。
在一些可能的实现方式中，所述填充材料的热膨胀系数与所述基底的热膨胀系数的差值小于或等于预设阈值。
在一些可能的实现方式中，所述填充材料和所述基底的材料为同一种材料。
在一些可能的实现方式中，所述填充材料在固化前可流动。
在一些可能的实现方式中，所述填充材料完整填充所述槽状结构。
在一些可能的实现方式中，所述填充材料部分填充所述槽状结构。
在一些可能的实现方式中，所述薄膜晶体管器件包括：
连接层，所述连接层连接至外部器件和/或所述过孔内的焊盘。
在一些可能的实现方式中，所述集成装置还包括：
光电二极管，所述光电二极管设置在所述刻蚀阻挡层的上方，所述光电二极管与所述薄膜晶体管器件内的电极层相连。
在一些可能的实现方式中，所述基底采用的材料为玻璃材料或聚酰亚胺材料。
在一些可能的实现方式中，所述集成装置还包括：
至少一个连接端，所述至少一个连接端用于与外界器件电连接，所述至少一个连接端设置在所述基底的上方。
在一些可能的实现方式中，所述至少一个连接端中的一个连接端与所述至少一个过孔中的一个过孔内设置的焊盘相连。
在一些可能的实现方式中，所述至少一个第二连接端与所述薄膜晶体管器件内的电极层相连。
在一些可能的实现方式中，所述第二连接端为焊盘或锡球。
第二方面，提供了一种显示装置，包括：
第一方面或第一方面的任一可能实现方式中所述的集成装置。
第三方面，提供了一种电子设备，包括：
第二方面所述的显示装置。
第四方面，提供了一种制备包括薄膜晶体管器件的集成装置的方法，包括：
在基底的上表面设置刻蚀阻挡层；
在所述基底的下表面形成槽状结构；
在所述槽状结构的底部，设置贯通所述刻蚀阻挡层的至少一个过孔；
将芯片设置在所述槽状结构内；
在所述刻蚀阻挡层的上方设置薄膜晶体管器件，其中，所述芯片通过所述至少一个过孔连接至所述薄膜晶体管器件。
在一些可能的实现方式中，所述在基底的上表面设置刻蚀阻挡层，包括：
通过等离子体增强化学气相沉积PECVD方式，在所述基底的上表面设置所述刻蚀阻挡层。
在一些可能的实现方式中，所述在所述基底的下表面形成槽状结构，包括：
通过光刻工艺确定所述槽状结构的位置；
在所述槽状结构的位置，通过刻蚀工艺形成所述槽状结构。
在一些可能的实现方式中，所述刻蚀工艺包括以下工艺中的至少一种：
干法刻蚀工艺、湿法刻蚀工艺和激光刻蚀工艺。
在一些可能的实现方式中，所述刻蚀阻挡层至少覆盖所述槽状结构的开口。
在一些可能的实现方式中，所述刻蚀阻挡层的厚度范围为400nm～500nm。
在一些可能的实现方式中，在同一刻蚀条件下所述刻蚀阻挡层的刻蚀速率和所述基底的刻蚀速率之间的差值大于或等于预设值。
在一些可能的实现方式中，所述刻蚀阻挡层的材料包括以下材料中的任一种：
氧化物、氮化物以及有机材料。
在一些可能的实现方式中，所述过孔内设置有焊盘。
在一些可能的实现方式中，所述过孔内设置的焊盘的材料为金属材料或导电玻璃。
在一些可能的实现方式中，所述芯片的厚度小于或等于所述槽状结构的深度。
在一些可能的实现方式中，所述槽状结构的深度等于所述基底的厚度。
在一些可能的实现方式中，所述槽状结构的侧面与所述槽状结构的下表面形成的角度大于预设角度。
在一些可能的实现方式中，所述在所述槽状结构的底部，设置贯通所述刻蚀阻挡层的至少一个过孔，包括：
通过光刻工艺在所述刻蚀阻挡层上确定所述至少一个过孔的位置；
在所述至少一个过孔的位置进行刻蚀，以形成所述至少一个过孔。
在一些可能的实现方式中，所述方法还包括：
在所述过孔内设置焊盘。
在一些可能的实现方式中，所述过孔内设置的焊盘的材料为金属材料或导电玻璃。
在一些可能的实现方式中，所述芯片的厚度小于或等于所述槽状结构的深度。
在一些可能的实现方式中，所述槽状结构的深度等于所述基底的厚度。
在一些可能的实现方式中，所述芯片设置有至少一个焊盘。
在一些可能的实现方式中，所述芯片的上表面上设置有所述至少一个焊盘。
在一些可能的实现方式中，所述至少一个焊盘和所述至少一个过孔一一对应。
在一些可能的实现方式中，所述芯片包括数据驱动芯片，所述数据驱动芯片通过所述至少一个过孔连接至所述薄膜晶体管器件内的电极层。
在一些可能的实现方式中，所述芯片包括扫描驱动芯片，所述扫描驱动芯片通过所述至少一个过孔连接至所述薄膜晶体管器件内的电极层。
在一些可能的实现方式中，所述方法还包括：
采用充填材料充填所述槽状结构，所述填充材料用于将所述芯片固定在所述槽状结构内。
在一些可能的实现方式中，所述填充材料的热膨胀系数与所述基底的热膨胀系数的差值小于或等于预设阈值。
在一些可能的实现方式中，所述填充材料和所述基底的材料为同一种材料。
在一些可能的实现方式中，所述填充材料在固化前可流动。
在一些可能的实现方式中，所述采用充填材料充填所述槽状结构，包括：
采用所述填充材料完整填充所述槽状结构。
在一些可能的实现方式中，所述采用充填材料充填所述槽状结构，包括：
采用填充材料部分填充所述槽状结构。
在一些可能的实现方式中，所述方法还包括：
在所述薄膜晶体管器件内设置连接层，所述连接层连接至外部器件和/或所述至少一个过孔。
在一些可能的实现方式中，所述方法还包括：
在所述基板的上方设置光电二极管，所述光电二极管与所述薄膜晶体管器件内的电极层相连。
在一些可能的实现方式中，所述基底采用的材料为玻璃材料或聚酰亚胺材料。
在一些可能的实现方式中，所述方法还包括：
在所述基底的上方设置至少一个第二连接端，所述至少一个第二连接端用于与外界器件电连接。
在一些可能的实现方式中，所述至少一个第二连接端中的一个第二连接端与所述至少一个过孔中的一条连接线相连。
在一些可能的实现方式中，所述至少一个第二连接端与所述薄膜晶体管器件内的电极层相连。
在一些可能的实现方式中，所述第二连接端为焊盘或锡球。
第五方面，提供了一种显示装置，包括：
按照第四方面或第四方面的任一种可能实现的方式中所述的制备集成装置的方法制备的集成装置。
第六方面，提供了一种电子设备，包括：
第五方面所述的显示装置。
基于以上技术方案，本申请实施例提供的集成装置和制备集成装置的方法，将用于控制薄膜晶体管器件的芯片集成在所述薄膜晶体管器件的基底内，不仅避免了芯片占用薄膜晶体管器件的有效工作面积，还能够大幅度减少集成装置的外部连接端子，进而有效简化了集成装置的整体结构。
附图说明
图1是本申请实施例的包括薄膜晶体管器件的集成装置的示例性侧截面图。
图2是本申请实施例的包括薄膜晶体管器件的集成装置的另一示例性侧截面图。
图3是本申请实施例的包括薄膜晶体管器件的集成装置的示例性平面截面图。
图4是本申请实施例的集成装置的制备方法的示例性工艺流程图。
图5是在基底上设置刻蚀阻挡层后形成的结构的示例性侧截面图。
图6是对图5所示的结构内的基底的下表面进行开槽处理后形成的结构的示例性侧截面图。
图7是在图6所示的结构内的刻蚀阻挡层上设置至少一个过孔后形成的结构的示例性侧截面图。
图8是在图7所示的结构内的至少一个过孔设置焊盘后的结构的示例性侧截面图。
图9是将芯片设置在图8所示的结构内的槽状结构后形成的示例性侧截面图。
图10是在图9所示的结构内的刻蚀阻挡层的下表面设置薄膜晶体管器件后形成的结构的示例性侧截面图。
图11是填充图9所示的结构内的槽状结构后形成的结构的示例性截面图。
图12是在图5所示的结构内的刻蚀阻挡层的上表面设置薄膜晶体管器件后形成的结构的示例性侧截面图。
图13是对图12所示的结构内的基底的下表面进行开槽处理后形成的结构的示例性侧截面图。
图14是在图13所示的结构内的刻蚀阻挡层上设置至少一个过孔后形成的结构的示例性侧截面图。
图15是在图14所示的结构内的至少一个过孔设置焊盘后的结构的示例性侧截面图。
图16是将芯片设置在图15所示的结构内的槽状结构后形成的示例性侧截面图。
具体实施方式
本申请实施例提供了一种包括薄膜晶体管器件的集成装置及其制备方法，所述集成装置可以包括多个TFT，所述多个TFT呈阵列式分布时，所述TFT器件又称为TFT阵列、TFT阵列器件或者光电传感器。本申请实施例的TFT器件能够精简化、小型化TFT器件与IC芯片之间的连接。
本申请实施例中的集成装置可以应用于TFT平板显示领域及基于TFT的平板传感器以及其他基于TFT工艺的产品及应用。例如，所述TFT器件可应用于具有有源矩阵(active matrix)的光电显示装置或者自发光的光电显示装置。例如。液晶显示装置和有机电致发光(Electroluminescence，EL)显示装置。
可选地，在本申请的一些实施例中，所述集成装置可以作为光学生物特征传感器，例如光学指纹传感器，用于实现生物特征感应操作。具体地，用户将手指放置于显示屏的上方时，所述集成装置接收到经由手指反射后形成的光信号，并将所述光信号转化为电信号，所述电信号能够反映用户手指的指纹信息。
在指纹识别过程中，所述集成装置的所在区域为所述集成装置的感应区域。所述感应区域可以位于显示屏的显示区域的下方，由此，用户在需要对所述终端设备进行解锁或者其他生物特征验证的时候，只需要将手指按压在位于所述显示屏上，位于所述感应区域的集成装置就可以进行指纹感应操作。
申请本实施例对用于进行指纹识别的光信号的发光源不做具体限定。例如，所述发光源可以是显示屏内的发光像素发出的光，也可以是显示屏下方的背光源发出的光，所述背光源可以是LED灯芯发出的光，所述LED灯芯可以包括：红光LED灯芯、蓝光LED灯芯、绿光LED灯芯、红外LED灯芯、紫外LED灯芯以及白光LED灯芯。应理解，本申请实施例对LED灯芯具体包括的LED灯芯种类不做限制，可以根据具体应用场合搭配不同种类的LED灯芯。
应理解，所述集成装置用作光学指纹传感器仅为示例，在其他可替代实施例中，所述集成装置也可以应用于彩色文件扫描，还可以应用于静脉成像，还可以应用于伪钞识别。本申请实施例对集成装置的用途不作特殊限制。
下面将结合图1至图9，详细介绍本申请实施例的集成装置以及制备集 成装置的方法。
需要说明的是，为便于说明，在本申请的实施例中，相同的附图标记表示相同的部件，并且为了简洁，在不同实施例中，省略对相同部件的详细说明。应理解，附图示出的本申请实施例中的各种部件的厚度、长宽等尺寸，以及集成装置的整体厚度、长宽等尺寸仅为示例性说明，而不应对本申请构成任何限定。
图1是本申请实施例的包括薄膜晶体管器件的集成装置的示例性框图。
如图1所示，所述集成装置可以包括：
基底100、芯片103、刻蚀阻挡层114和薄膜晶体管器件105。
所述薄膜晶体管器件105设置在所述刻蚀阻挡层114的上方，所述基底100设置在所述刻蚀阻挡层114的下方。
其中，在同一刻蚀条件下所述刻蚀阻挡层114的刻蚀速率大于所述基底100的刻蚀速率。所述基底100的下表面向上延伸形成有槽状结构101。所述槽状结构101的底部设置有贯通所述刻蚀阻挡层114的至少一个过孔102，例如，所述槽状结构101的底部和所述刻蚀阻挡层114上表面之间形成有至少一个过孔102。所述芯片设置在所述槽状结构内，所述芯片通过所述至少一个过孔102连接至所述薄膜晶体管器件。
在具体实现中，可以通过对集成装置的基底100的下表面的部分区域进行开槽处理，以形成图1所示的槽状结构101。所述槽状结构101内布置有金属电器连接层(即图1所示的至少一个过孔102内设置的焊盘)。所述芯片103安装在所述槽状结构101内，并通过所述金属电器连接层与所述至少一个过孔102进行电连接。此外，所述基底上制备的所述薄膜晶体管器件105的电极层也连接至所述至少一个过孔102。由此实现所述芯片103和所述薄膜晶体管器件105之间的连接。
本申请实施例中的集成装置，将用于控制所述薄膜晶体管器件105的芯片103集成在所述薄膜晶体管器件105的基底100内，不仅避免了芯片103占用TFT的有效工作面积，还能够大幅度减少集成装置的外部连接端子，进而有效简化了集成装置的整体结构。
可选地，在本申请的一些实施例中，所述基底100的材料可以是TFT工艺涉及的标准基底材料，例如玻璃材料或聚酰亚胺材料。应理解，本申请实施例对基底100的具体材料型号不做限定。例如，所述基底100的材料为 玻璃材料时可以为无碱玻璃。由于所述无碱玻璃的应变温度可以高于625℃，因此，可以使得所述基底100具有良好的化学稳定性。
可选地，在本申请的一些实施例中，图1所示的集成装置用于进行指纹识别且所述发光源为背光源时，所述基底100的材料可以是透光材料，由此保证所述背光源发出的光能够通过所述基底100传输至显示屏。例如，所述基底100可以为玻璃基底。但是本申请对此不做限制，在其他实施例中，所述基底100的材料还可以为透光塑料等其它透光材料。
可选地，在本申请的一些实施例中，所述刻蚀阻挡层114的材料包括以下材料中的任一种：
氧化物、氮化物以及有机材料。
例如，所述刻蚀阻挡层114的材料可以是氮化硅。
可选地，在本申请的一些实施例中，所述刻蚀阻挡层114的厚度范围为400nm～500nm。
可选地，在本申请的一些实施例中，所述刻蚀阻挡层114的材料热膨胀系数与基底100的热膨胀系数相近。例如，所述刻蚀阻挡层114的材料热膨胀系数与基底100的热膨胀系数之间的差值小于或等于一个预设值。
可选地，在本申请的一些实施例中，在同一刻蚀条件下所述刻蚀阻挡层114的刻蚀速率与所述基底100的刻蚀速率之间的差值大于或者等于一个预设值。
可选地，在本申请的一些实施例中，所述刻蚀阻挡层114的材料为透明材料。
可选地，在本申请的一些实施例中，所述芯片103可以是经过再布线层(Redistribution Layer，RDL)处理和微凸点工艺处理后的芯片。
可选地，在本申请的一些实施例中，所述芯片103可以是倒装芯片(Flip Chip)。
应理解，本申请实施例对所述芯片103在所述槽状结构101内的摆放位置以及摆放形式不做具体限定。
例如，所述芯片103可以是包括沿基底100的上表面的平行方向和/或垂直方向排列的多个芯片。即可以将沿基底100的上表面的平行方向和/或垂直方向排列的多个芯片封装在所述槽状结构101内。可选地，所述多个芯片103之间可以通过电连接的方式实现信号的传输。
可选地，在本申请的一些实施例中，所述槽状结构的深度等于所述基底的厚度。由此，可以有效降低设置所述至少一个开孔的过程中的难度。
可选地，在本申请的一些实施例中，所述槽状结构101的深度大于100微米(um)。进一步地，所述至少一个开孔还需要贯通所述槽状结构101的底部和所述基底100的上表面之间的部分基底。
可选地，在本申请的一些实施例中，所述槽状结构的侧面与所述槽状结构的下表面形成的角度大于预设角度，由此，能够降低将所述芯片103安装在所述槽状结构101时的操作难度。
可选地，在本申请的一些实施例中，所述刻蚀阻挡层114至少覆盖所述槽状结构101的开口。
可选地，在本申请的一些实施例中，所述芯片103的厚度小于或等于所述槽状结构101的深度，进而保证所述芯片103能够完全集成设置在所述基底100内。
例如，所述刻蚀阻挡层114在所述基底100的上表面所在平面内的最大宽度大于所述槽状结构101的开口在所述基底100的上表面所在平面内的最大宽度。
又例如，沿某一方向上，所述刻蚀阻挡层114在所述基底100的上表面所在平面内的宽度大于所述槽状结构101的开口在所述基底100的上表面所在平面内的宽度。
应理解，在其他实施例中，所述基底100也可称为衬底100或者基板100。
应理解，本申请实施例中的薄膜晶体管器件105可以是在基板100上制备的各种不同的薄膜。例如，半导体主动层、介电层和金属电极层。应理解，本申请实施例对所述薄膜晶体管器件105的制作工艺不做具体限定。例如，所述薄膜晶体管器件105的制作工艺可以是现有技术的制作工艺。
图2是本申请实施例的薄膜晶体管器件105的示例性截面图。
如图2所示，所述薄膜晶体管器件105可以是具有底栅结构的薄膜晶体管器件。
所述芯片103为驱动扫描芯片时，所述薄膜晶体管器件105的栅极106可以与芯片103连接，所述芯片103还与外部电源相连，所述外部电源用于为薄膜晶体管器件105提供扫描电压。所述薄膜晶体管器件105的漏极109可以与所述薄膜晶体管器件105的内部器件连接，所述薄膜晶体管器件的源 极108可以与图1所示的至少一个过孔102相连，所述薄膜晶体管器件105的漏极109和所述薄膜晶体管器件105的源极108之间存在沟道区107。
可选地，在本申请的一些实施例中，所述沟道区107的材料包括但不限于：非晶硅(a-Si)材料、铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)，以及低温多晶硅(low temperature poly-silicon，LTPS)。例如，氧化铟锡或氧化锌等透光材料。
可选地，在本申请的一些实施例中，如图2所示，所述薄膜晶体管器件105还可以包括：电介质层111。
所述电介质层包括但不限于：氧化物和氮化物等绝缘电介质层。
可选地，如图2所示，在本申请的一些实施例中，所述集成装置还可以包括光电二极管110。
所述光电二极管110是各种光电检测系统中实现光电转换的关键元件，所述光电二极管110用于将光信号(例如，红外光信号、可见光信号及紫外光信号)转变成为电信号的器件。进一步地，所述光电二极管110可以将转换的电信号发送给由基底100和薄膜晶体管器件105形成的薄膜晶体管，所述薄膜晶体管输出所述电信号。应理解，在其他实施例中，所述光电二极管110又称为光电感应单元或光探测器。
如图2所示，所述光电二极管110可以设置在所述基底100的上方，所述光电二极管110与所述薄膜晶体管器件105内的电极层相连。例如，所述光电二极管110与所述薄膜晶体管器件105内的电极层的漏极109相连。
可选地，在本申请的一些实施例中，图1所示的集成装置可以包括多个如图2所示的光电二极管110，多个所述光电二极管110可以呈阵列式分布。其中，每个光电二极管110与所述薄膜晶体管器件105的电极层中的一个漏极相连。
可选地，在本申请的一些实施例中，可以根据需要探测的光的波长范围、工艺能力等参数确定所述光电二极管110的结构以及具体材料构成。但本申请实施例不限于此。
可选地，在本申请的一些实施例中，所述光电二极管110可以是PIN型光电二极管或PN型光电二极管。
以所述光电二极管110为PIN型光电二极管为例，所述光电二极管110可以包括：自下而上的N型掺杂半导体层、本征半导体层、P型掺杂半导体 层。其中，N型掺杂半导体层作为光电二极管110的阴极，本征半导体层作为光电二极管110的光吸收层，P型掺杂半导体层作为光电二极管110的阳极。
应理解，所述PIN型光电二极管也可称PIN结二极管、PIN二极管。
可选地，如图2所示，在本申请的一些实施例中，所述薄膜晶体管器件105还可以包括：
连接层112，所述连接层112连接至外部器件和/或所述至少一个过孔102。本申请实施例中，所述连接层112不仅能够实现所述薄膜晶体管器件105内部各个层之间的连接，还能够实现所述薄膜晶体管器件105和外部器件的连接以及所述芯片103和外部器件的连接，进而实现了集成装置的电性互联功能。换句话说，所述芯片103和所述薄膜晶体管器件105可以通过所述连接层112实现与其他外围电路或者所述芯片103所属设备的其他元件的电性互连和信号传输。
所述连接层112的材料可以是金属，也可以是ITO等透明导电材料。本申请实施例对所述连接层112的具体材料不做特殊限定。
本申请实施例中，可以根据所述薄膜晶体管器件105内部各个层之间的连接需求、所述薄膜晶体管器件内部各个层与所述芯片103之间的连接需求、以及所述薄膜晶体管器件105内部各个层与外部器件的连接需求确定所述连接层112的层数。但本申请实施例对所述连接层112的具体层数不做限定。
本申请实施例中，可以从基底100的上表面引出所述连接层112，也可以从所述薄膜晶体管器件105的任意层引出所述连接层112。可选地，若从薄膜晶体管器件105的上表面引出所述连接层112，所述连接层112的材料可以采用透明导电材料。例如ITO。由此保证光的正常传输。
可选地，如图1和图2所示，所述过孔102内可以设置有焊盘115。
可选地，在本申请的一些实施例中，所述过孔102内设置的焊盘115的材料为金属材料或导电玻璃。
可选地，如图1和图2所示，所述芯片103上设置有至少一个焊盘。
可选地，在本申请的一些实施例中，所述芯片103的上表面设置有所述至少一个焊盘104。
可选地，在本申请的一些实施例中，所述至少一个焊盘104可以均匀地或者不均匀地分布在芯片103的上表面。
可选地，在本申请的一些实施例中，所述至少一个焊盘104和所述至少一个过孔102一一对应。换句话说，可以根据所述至少一个焊盘104的布置方式布置所述至少一个过孔102。
本申请实施例中，通过所述至少一个焊盘104和所述至少一个过孔102可以实现集成在所述基底100中的所述芯片103与外界器件以及薄膜晶体管器件105的电连接，但本申请实施例对所述至少一个焊盘104的具体形式不作限定。比如所述至少一个焊盘104可以是用于与柔性印刷电路(Flexible Printed Circuit，FPC)电连接的焊点或者锡球或者任何形式的连接端。
需要说明的是，本申请实施例中的芯片103在进入本集成工艺流程之前可以是已经在其一表面制备有焊盘(Pad)的芯片，例如，如图1所示的焊盘104，所述焊盘104通过所述至少一个过孔102电连接至薄膜晶体管器件105。所述焊盘104可以理解为芯片103与外界连接的管脚。在本申请实施例中，芯片103的上表面即为进入本集成工艺流程之前表面已制备有焊盘的一面，与所述芯片103的下表面相对的一面即为芯片103的下表面。
应理解，图1所示的焊盘104位于芯片103的上表面仅为示例，本申请实施例不限于此。例如，也可以在所述芯片103的下表面或侧表面设置所述至少一个焊盘。
可选地，在本申请的一些实施例中，所述芯片103包括数据驱动芯片，所述数据驱动芯片可以通过所述至少一个过孔102连接至所述薄膜晶体管器件105内的电极层。例如，所述数据驱动芯片可以通过所述至少一个过孔102连接至所述电极层内的源极。
可选地，在本申请的一些实施例中，所述芯片103包括扫描驱动芯片，所述扫描驱动芯片通过所述至少一个过孔102连接至所述薄膜晶体管器件105内的电极层。例如，所述扫描驱动芯片可以通过所述至少一个过孔102连接至所述电极层内的栅极。
可选地，在本申请的一些实施例中，所述集成装置还包括：
所述槽状结构内的填充材料，所述填充材料用于将所述芯片固定在所述槽状结构内。
可选地，在本申请的一些实施例中，所述填充材料的热膨胀系数(Coefficient of thermal expansion，CTE)与所述基底100的热膨胀系数的差值小于或等于预设阈值。
可选地，在本申请的一些实施例中，所述填充材料和所述基底100的材料可以为同一种材料。
可选地，在本申请的一些实施例中，所述填充材料可以为环氧树脂注塑化合物(Epoxy Molding Compound，EMC)材料。
可选地，在本申请的一些实施例中，所述填充材料在固化前可流动，由此保证所述填充材料填充到所述槽状结构101并固化后，所述槽状结构101内的所述填充材料的上表面是平整表面。
在本申请的描述中，术语“上”、“下”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请而不是要求本申请必须以特定的方位构造和操作，因此不能理解为对本申请的限制。
举例来说，在图1所示的实施例中，所述芯片103的上表面在进入本集成工艺流程之前制备有焊盘，用于与基板100的槽状结构101的底部贴合。但本申请实施例不限于此。例如，在其他可替代实施例中，图1所示的芯片103也可以在所述芯片的下表面制备焊盘，由此，在将所述芯片103固定到所述槽状结构101内时，可以将下表面与所述槽状结构101的底部贴合。
可选地，在本申请的一些实施例中，所述填充材料完整填充所述槽状结构。
可选地，在本申请的一些实施例中，所述填充材料部分填充所述槽状结构。
图3是本申请实施例的集成装置的平面截面图。
可选地，如图3所示，在本申请的一些实施例中，所述集成装置还包括至少一个连接端113，所述至少一个连接端113用于与外界器件电连接，所述至少一个连接端113设置在所述基底100的上方，所述至少一个连接端113使得所述集成装置内部电路与其他外围电路或者所述集成装置所属设备的其他元件的电性互连和信号传输。
可选地，在本申请的一些实施例中，所述至少一个连接端113中的一个连接端113与所述至少一个过孔102中的一条连接线102相连。
可选地，在本申请的一些实施例中，所述至少一个连接端113与所述薄膜晶体管器件105内的电极层相连。
可选地，在本申请的一些实施例中，所述连接端为焊盘或锡球。
应理解，在图3所示的实施例中，所述集成装置包括6个芯片103以及 每个芯片103通过一条连接线102连接至一个连接端113，但本申请实施例不限于此。
可选地，在本申请实施例还提供了一种显示装置，所述显示装置可以包括上述集成装置。例如，液晶显示装置。
所述液晶显示装置可以包括液晶面板和用于给所述液晶面板提供光源的背光模组。所述液晶面板可以包括上文所述的TFT器件(包括多个薄膜晶体管)、以及纵横交错的扫描线和数据线，每一行的扫描线控制一行的TFT的栅极，每一列的数据线连接一列TFT的源极，每个TFT的漏极连接一个像素电极以形成像素电容，像素电容包括相对置的像素电极和公共电极，像素电极连接到TFT的漏极，公共电极可以连接到一个恒定的电压信号。像素电极和公共电极之间充满了液晶分子，通过调整数据线的输出电压就可以控制像素电极和公共电极之间的压差，从而调整液晶分子的偏转角度，实现光通量的控制。
可选地，本申请实施例还提供了一种电子设备，所述电子设备可以包括上述显示装置。例如，所述电子设备可以是电视、手机、平板电脑或电子书等终端设备。
图4是本申请实施例的制备集成装置的方法的示意流程图。应理解，图4所示的方法200可以用于制备图1至图3所示的集成装置。图4所示的方法200也可以对应图5至图10、图1的顺序制备图1至图3所示的集成装置。下面结合图1、图4至图10对本申请实施例的制备集成装置的方法进行说明。
如图4所述，所述方法200可以包括：
S210，在基底的上表面设置刻蚀阻挡层。
例如，图5是在基底上设置刻蚀阻挡层后形成的结构的示例性侧截面图。如图5所示，基底100的上表面设置有刻蚀阻挡层114。
可选地，在本申请的一些实施例中，所述S120具体可以包括：
通过等离子体增强化学气相沉积(PECVD)方式，在所述基底的上表面设置所述刻蚀阻挡层。
应理解，上述PECVD方式仅为示例性描述，本申请实施例不限于此。例如。在其他可替代实施例中，所述沉积的方式包括但不限于：
物理气相沉积(Physical Vapor Deposition，PVD)方式和化学气相沉积(Chemical Vapor Deposition，CVD)方式。
可选地，在本申请的一些实施例中，所述刻蚀阻挡层至少覆盖所述槽状结构的开口。
可选地，在本申请的一些实施例中，所述刻蚀阻挡层的厚度范围为400nm～500nm。
可选地，在本申请的一些实施例中，在同一刻蚀条件下所述刻蚀阻挡层的刻蚀速率和所述基底的刻蚀速率之间的差值大于或等于预设值。
可选地，在本申请的一些实施例中，所述刻蚀阻挡层的材料包括以下材料中的任一种：
氧化物、氮化物以及有机材料。
S220，在所述基底的下表面形成槽状结构。
可选地，在本申请的一些实施例中，所述S220具体可以包括：
通过光刻工艺确定所述槽状结构的位置；在所述槽状结构的位置，通过刻蚀工艺形成所述槽状结构。
例如，图6是对图5所示的结构内的基底的下表面进行开槽处理后形成的结构的示例性侧截面图。在具体实现中，可以将图5所示的结构倒置后在图5所示的下表面形成如图6所示的槽状结构101。
可选地，在本申请的一些实施例中，所述刻蚀工艺包括以下工艺中的至少一种：
干法刻蚀工艺、湿法刻蚀工艺和激光刻蚀工艺。
可选地，在本申请的一些实施例中，所述干法蚀刻(dry etching)工艺可以包括以下刻蚀工艺中的至少一种：
采用将四氟甲烷(CF4)和六氟化硫(SF6)用作蚀刻气体(etching gas)的反应性离子蚀刻(ion etching)、化学干法蚀刻(chemical dry etching)以及等离子体蚀刻(plasma etching)等。
可选地，在本申请的一些实施例中，还可以通过改变蚀刻气体的混合比可以改变蚀刻速度。
可选地，在本申请的一些实施例中，所述湿法刻蚀工艺的化学原料可以包括但不限于含氢氟酸的刻蚀液。
可选地，在本申请的一些实施例中，采用干法刻蚀与湿法刻蚀相结合的刻蚀方法，或者采用激光刻蚀结合湿法刻蚀的方法，能够有效保证刻蚀的形状以及底面平整度等。
可选地，在本申请的一些实施例中，所述槽状结构的深度等于所述基底的厚度。
可选地，在本申请的一些实施例中，所述槽状结构的侧面与所述槽状结构的下表面形成的角度大于预设角度。
S230，在所述槽状结构的底部，设置贯通所述刻蚀阻挡层的至少一个过孔。
可选地，在本申请的一些实施例中，所述S230可以具体包括：
通过光刻工艺在所述刻蚀阻挡层上确定所述至少一个过孔的位置；在所述至少一个过孔的位置进行刻蚀，以形成所述至少一个过孔。
例如，图7是在图6所示的结构内的刻蚀阻挡层上设置至少一个过孔后形成的结构的示例性侧截面图。如图7所示，可以在所述槽状结构101的底部和所述刻蚀阻挡层114下表面之间，设置至少一个过孔102。
可选地，图4所示的方法200还可包括：
在所述过孔内设置焊盘。
例如，图8是在图7所示的结构内的至少一个过孔设置焊盘后的结构的示例性侧截面图。具体地，可以直接在图7所示的过孔102内设置如图8所示的焊盘115。
可选地，在本申请的一些实施例中，所述过孔内设置的焊盘的材料为金属材料或导电玻璃。
S240，将芯片设置在所述槽状结构内。
例如，图9是将芯片设置在图8所示的结构内的槽状结构后形成的示例性侧截面图。如图9所示，可以将芯片103上的焊盘104和过孔102内设置的焊盘115固定相连。
可选地，在本申请的一些实施例中，所述芯片可以通过与所述至少一个过孔绑定(bonding)的方式，固定设置在所述槽状结构内。
可选地，在本申请的一些实施例中，所述芯片的厚度小于或等于所述槽状结构的深度。
可选地，在本申请的一些实施例中，所述芯片设置有至少一个焊盘。
可选地，在本申请的一些实施例中，所述芯片的上表面上设置有所述至少一个焊盘。
可选地，在本申请的一些实施例中，所述至少一个焊盘和所述至少一个 过孔一一对应。
可选地，在本申请的一些实施例中，所述芯片包括数据驱动芯片，所述数据驱动芯片通过所述至少一个过孔连接至所述薄膜晶体管器件内的电极层。
可选地，在本申请的一些实施例中，所述芯片包括扫描驱动芯片，所述扫描驱动芯片通过所述至少一个过孔连接至所述薄膜晶体管器件内的电极层。
应理解，本申请实施例对所述芯片在所述槽状结构内的摆放位置以及摆放方式不做具体限定。
S250，在所述刻蚀阻挡层的上方设置薄膜晶体管器件，其中，所述芯片通过所述至少一个过孔连接至所述薄膜晶体管器件。
例如，图10是在图9所示的结构内的刻蚀阻挡层的下表面设置薄膜晶体管器件后形成的结构的示例性侧截面图。在具体实现中，可以将图9所示的结构倒置后在图9所示的刻蚀阻挡层114的上方设置薄膜晶体管器件105。
应理解，本申请实施例对在所述基底的上方设置所述薄膜晶体管器件的具体工艺和所述薄膜晶体管器件的具体用途不做限定。
例如，在所述基底的上方设置所述薄膜晶体管器件的具体工艺包括但不限于：基于非晶硅(amorphous silicon，a-Si)的TFT工艺、基于低温多晶硅(Low Temperature Poly-silicon，LTPS)技术的TFT工艺以及基于氧化銦鎵鋅(Indium Gallium Zinc oxide，IGZO)的TFT工艺。
又例如，所述薄膜晶体管器件的用途可以包括但不限于：平板显示器件、光电平板感应器件或温度平板感应器件。
可选地，在本申请的一些实施例中，所述方法200还可以包括：
采用充填材料充填所述槽状结构，所述填充材料用于将所述芯片固定在所述槽状结构内。
例如，图11是填充图9所示的结构内的槽状结构后形成的结构的示例性截面图。可以直接在图9所示的槽状结构内填充所述填充材料，进而形成图11所示的结构。应理解，本申请实施例中，在制备集成装置时，可以先充填所述充填材料再设置所述薄膜晶体管器件105，也可以先设置所述薄膜晶体管器件105在充填所述充填材料，本申请实施例对此不做具体限定。
可选地，在本申请的一些实施例中，所述填充材料的热膨胀系数与所述 基底的热膨胀系数的差值小于或等于预设阈值。
可选地，在本申请的一些实施例中，所述填充材料和所述基底的材料为同一种材料。
可选地，在本申请的一些实施例中，所述填充材料在固化前可流动。
可选地，在本申请的一些实施例中，采用所述填充材料完整填充所述槽状结构。
可选地，在本申请的一些实施例中，采用填充材料部分填充所述槽状结构。
可选地，在本申请的一些实施例中，所述方法200还可以包括：
在所述薄膜晶体管器件内设置连接层，所述连接层连接至外部器件和/或所述至少一个过孔。
例如，如图2所示，可以在薄膜晶体管器件105内设置连接层112。
可选地，在本申请的一些实施例中，所述方法200还可以包括：
在所述基板的上方设置光电二极管，所述光电二极管与所述薄膜晶体管器件内的电极层相连。
可选地，在本申请的一些实施例中，所述基底采用的材料为玻璃材料或聚酰亚胺材料。
可选地，在本申请的一些实施例中，所述方法200还可以包括：
在所述基底的上方设置至少一个第二连接端，所述至少一个第二连接端用于与外界器件电连接。
可选地，在本申请的一些实施例中，所述至少一个第二连接端中的一个第二连接端与所述至少一个过孔中的一条连接线相连。
可选地，在本申请的一些实施例中，所述至少一个第二连接端与所述薄膜晶体管器件内的电极层相连。
可选地，在本申请的一些实施例中，所述第二连接端为焊盘或锡球。
应理解，方法实施例与集成装置的实施例可以相互对应，类似的描述可以参照集成装置的具体实施例。为了简洁，在此不再赘述。
还应理解，上述列举的制备集成装置的方法200的各实施例，可以通过机器人或者数控加工方式来执行，用于执行所述方法200的设备软件或工艺可以通过执行保存在存储器中的计算机程序代码来执行上述方法200。
需要说明的是，在不冲突的前提下，本申请描述的各个实施例和/或各个 实施例中的技术特征可以任意的相互组合，组合之后得到的技术方案也应落入本申请的保护范围。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
例如，图12是在图5所示的结构内的刻蚀阻挡层的上表面设置薄膜晶体管器件后形成的结构的示例性侧截面图。图13是对图12所示的结构内的基底的下表面进行开槽处理后形成的结构的示例性侧截面图。图14是在图13所示的结构内的刻蚀阻挡层上设置至少一个过孔后形成的结构的示例性侧截面图。图15是在图14所示的结构内的至少一个过孔设置焊盘后的结构的示例性侧截面图。图16是将芯片设置在图15所示的结构内的槽状结构后形成的示例性侧截面图。本申请实施例也可以按照图5、图12至图16、图1的工艺顺序制备集成装置。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的集成装置、集成装置内的部件和制备集成装置的方法，可以通过其它的方式实现。例如，以上所描述的集成装置实施例仅仅是示例性的，例如，所述部件的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个部件或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，器件或部件的间接耦合或通信连接，可以是电性，机械或其它的形式。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (68)

  1. 一种包括薄膜晶体管器件的集成装置，其特征在于，包括：
    基底、芯片、刻蚀阻挡层和薄膜晶体管器件；
    所述薄膜晶体管器件设置在所述刻蚀阻挡层的上方，所述基底设置在所述刻蚀阻挡层的下方；
    其中，在同一刻蚀条件下所述刻蚀阻挡层的刻蚀速率大于所述基底的刻蚀速率，所述基底的下表面向上延伸形成有槽状结构，所述槽状结构的底部设置有贯通所述刻蚀阻挡层的至少一个过孔，所述芯片设置在所述槽状结构内，所述芯片通过所述至少一个过孔连接至所述薄膜晶体管器件。
  2. 根据权利要求1所述的集成装置，其特征在于，所述刻蚀阻挡层至少覆盖所述槽状结构的开口。
  3. 根据权利要求1或2所述的集成装置，其特征在于，所述刻蚀阻挡层的厚度范围为400nm～500nm。
  4. 根据权利要求1至3中任一项所述的集成装置，其特征在于，在同一刻蚀条件下所述刻蚀阻挡层的刻蚀速率和所述基底的刻蚀速率之间的差值大于或等于预设值。
  5. 根据权利要求1至4中任一项所述的集成装置，其特征在于，所述刻蚀阻挡层的材料包括以下材料中的任一种：
    氧化物、氮化物以及有机材料。
  6. 根据权利要求1至5中任一项所述的集成装置，其特征在于，所述过孔内设置有焊盘。
  7. 根据权利要求6所述的集成装置，其特征在于，所述过孔内设置的焊盘的材料为金属材料或导电玻璃。
  8. 根据权利要求1至7中任一项所述的集成装置，其特征在于，所述芯片的厚度小于或等于所述槽状结构的深度。
  9. 根据权利要求8所述的集成装置，其特征在于，所述槽状结构的深度等于所述基底的厚度。
  10. 根据权利要求1至9中任一项所述的集成装置，其特征在于，所述槽状结构的侧面与所述槽状结构的下表面形成的角度大于预设角度。
  11. 根据权利要求1至10中任一项所述的集成装置，其特征在于，所述 芯片设置有至少一个焊盘。
  12. 根据权利要求11所述的集成装置，其特征在于，所述芯片的上表面设置有所述至少一个焊盘。
  13. 根据权利要求11所述的集成装置，其特征在于，所述至少一个焊盘和所述至少一个过孔一一对应。
  14. 根据权利要求1至13中任一项所述的集成装置，其特征在于，所述芯片包括数据驱动芯片，所述数据驱动芯片通过所述至少一个过孔连接至所述薄膜晶体管器件内的电极层。
  15. 根据权利要求1至14中任一项所述的集成装置，其特征在于，所述芯片包括扫描驱动芯片，所述扫描驱动芯片通过所述至少一个过孔连接至所述薄膜晶体管器件内的电极层。
  16. 根据权利要求1至15中任一项所述的集成装置，其特征在于，所述集成装置还包括：
    所述槽状结构内的填充材料，所述填充材料用于将所述芯片固定在所述槽状结构内。
  17. 根据权利要求16所述的集成装置，其特征在于，所述填充材料的热膨胀系数与所述基底的热膨胀系数的差值小于或等于预设阈值。
  18. 根据权利要求16所述的集成装置，其特征在于，所述填充材料和所述基底的材料为同一种材料。
  19. 根据权利要求16所述的集成装置，其特征在于，所述填充材料在固化前可流动。
  20. 根据权利要求16所述的集成装置，其特征在于，所述填充材料完整填充所述槽状结构。
  21. 根据权利要求16所述的集成装置，其特征在于，所述填充材料部分填充所述槽状结构。
  22. 根据权利要求1至21中任一项所述的集成装置，其特征在于，所述薄膜晶体管器件包括：
    连接层，所述连接层连接至外部器件和/或所述过孔内的焊盘。
  23. 根据权利要求1至22中任一项所述的集成装置，其特征在于，所述集成装置还包括：
    光电二极管，所述光电二极管设置在所述刻蚀阻挡层的上方，所述光电 二极管与所述薄膜晶体管器件内的电极层相连。
  24. 根据权利要求1至23中任一项所述的集成装置，其特征在于，所述基底采用的材料为玻璃材料或聚酰亚胺材料。
  25. 根据权利要求1至24中任一项所述的集成装置，其特征在于，所述集成装置还包括：
    至少一个连接端，所述至少一个连接端用于与外界器件电连接，所述至少一个连接端设置在所述基底的上方。
  26. 根据权利要求25所述的集成装置，其特征在于，所述至少一个连接端中的一个连接端与所述至少一个过孔中的一个过孔内设置的焊盘相连。
  27. 根据权利要求25所述的集成装置，其特征在于，所述至少一个第二连接端与所述薄膜晶体管器件内的电极层相连。
  28. 根据权利要求25所述的集成装置，其特征在于，所述第二连接端为焊盘或锡球。
  29. 一种显示装置，其特征在于，包括：
    权利要求1至28中任一项所述的集成装置。
  30. 一种电子设备，其特征在于，包括：
    权利要求29所述的显示装置。
  31. 一种制备包括薄膜晶体管器件的集成装置的方法，其特征在于，包括：
    在基底的上表面设置刻蚀阻挡层；
    在所述基底的下表面形成槽状结构；
    在所述槽状结构的底部，设置贯通所述刻蚀阻挡层的至少一个过孔；
    将芯片设置在所述槽状结构内；
    在所述刻蚀阻挡层的上方设置薄膜晶体管器件，其中，所述芯片通过所述至少一个过孔连接至所述薄膜晶体管器件。
  32. 根据权利要求31所述的方法，其特征在于，所述在基底的上表面设置刻蚀阻挡层，包括：
    通过等离子体增强化学气相沉积PECVD方式，在所述基底的上表面设置所述刻蚀阻挡层。
  33. 根据权利要求31或32所述的方法，其特征在于，所述刻蚀阻挡层的厚度范围为400nm～500nm。
  34. 根据权利要求31至33中任一项所述的方法，其特征在于，在同一刻蚀条件下所述刻蚀阻挡层的刻蚀速率和所述基底的刻蚀速率之间的差值大于或等于预设值。
  35. 根据权利要求31或34所述的方法，其特征在于，所述在所述基底的下表面形成槽状结构，包括：
    通过光刻工艺确定所述槽状结构的位置；
    在所述槽状结构的位置，通过刻蚀工艺形成所述槽状结构。
  36. 根据权利要求31至35中任一项所述的方法，其特征在于，所述刻蚀工艺包括以下工艺中的至少一种：
    干法刻蚀工艺、湿法刻蚀工艺和激光刻蚀工艺。
  37. 根据权利要求36所述的集成装置，其特征在于，所述刻蚀阻挡层至少覆盖所述槽状结构的开口。
  38. 根据权利要求31至37中任一项所述的方法，其特征在于，所述刻蚀阻挡层的材料包括以下材料中的任一种：
    氧化物、氮化物以及有机材料。
  39. 根据权利要求31至38中任一项所述的方法，其特征在于，所述过孔内设置有焊盘。
  40. 根据权利要求39所述的方法，其特征在于，所述过孔内设置的焊盘的材料为金属材料或导电玻璃。
  41. 根据权利要求31至40中任一项所述的方法，其特征在于，所述芯片的厚度小于或等于所述槽状结构的深度。
  42. 根据权利要求41所述的方法，其特征在于，所述槽状结构的深度等于所述基底的厚度。
  43. 根据权利要求31至42中任一项所述的方法，其特征在于，所述槽状结构的侧面与所述槽状结构的下表面形成的角度大于预设角度。
  44. 根据权利要求31至43中任一项所述的方法，其特征在于，所述在所述槽状结构的底部，设置贯通所述刻蚀阻挡层的至少一个过孔，包括：
    通过光刻工艺在所述刻蚀阻挡层上确定所述至少一个过孔的位置；
    在所述至少一个过孔的位置进行刻蚀，以形成所述至少一个过孔。
  45. 根据权利要求44所述的方法，其特征在于，所述方法还包括：
    在所述过孔内设置焊盘。
  46. 根据权利要求45所述的方法，其特征在于，所述过孔内设置的焊盘的材料为金属材料或导电玻璃。
  47. 根据权利要求31至46中任一项所述的方法，其特征在于，所述芯片的厚度小于或等于所述槽状结构的深度。
  48. 根据权利要求47所述的方法，其特征在于，所述槽状结构的深度等于所述基底的厚度。
  49. 根据权利要求31至48中任一项所述的方法，其特征在于，所述芯片设置有至少一个焊盘。
  50. 根据权利要求49所述的方法，其特征在于，所述芯片的上表面上设置有所述至少一个焊盘。
  51. 根据权利要求49所述的方法，其特征在于，所述至少一个焊盘和所述至少一个过孔一一对应。
  52. 根据权利要求31至51中任一项所述的方法，其特征在于，所述芯片包括数据驱动芯片，所述数据驱动芯片通过所述至少一个过孔连接至所述薄膜晶体管器件内的电极层。
  53. 根据权利要求31至52中任一项所述的方法，其特征在于，所述芯片包括扫描驱动芯片，所述扫描驱动芯片通过所述至少一个过孔连接至所述薄膜晶体管器件内的电极层。
  54. 根据权利要求31至53中任一项所述的方法，其特征在于，所述方法还包括：
    采用充填材料充填所述槽状结构，所述填充材料用于将所述芯片固定在所述槽状结构内。
  55. 根据权利要求54所述的方法，其特征在于，所述填充材料的热膨胀系数与所述基底的热膨胀系数的差值小于或等于预设阈值。
  56. 根据权利要求55所述的方法，其特征在于，所述填充材料和所述基底的材料为同一种材料。
  57. 根据权利要求55所述的方法，其特征在于，所述填充材料在固化前可流动。
  58. 根据权利要求55所述的方法，其特征在于，所述采用充填材料充填所述槽状结构，包括：
    采用所述填充材料完整填充所述槽状结构。
  59. 根据权利要求55所述的方法，其特征在于，所述采用充填材料充填所述槽状结构，包括：
    采用填充材料部分填充所述槽状结构。
  60. 根据权利要求31至59中任一项所述的方法，其特征在于，所述方法还包括：
    在所述薄膜晶体管器件内设置连接层，所述连接层连接至外部器件和/或所述至少一个过孔。
  61. 根据权利要求31至60中任一项所述的方法，其特征在于，所述方法还包括：
    在所述基板的上方设置光电二极管，所述光电二极管与所述薄膜晶体管器件内的电极层相连。
  62. 根据权利要求31至61中任一项所述的方法，其特征在于，所述基底采用的材料为玻璃材料或聚酰亚胺材料。
  63. 根据权利要求31至62中任一项所述的方法，其特征在于，所述方法还包括：
    在所述基底的上方设置至少一个第二连接端，所述至少一个第二连接端用于与外界器件电连接。
  64. 根据权利要求63所述的方法，其特征在于，所述至少一个第二连接端中的一个第二连接端与所述至少一个过孔中的一条连接线相连。
  65. 根据权利要求63所述的方法，其特征在于，所述至少一个第二连接端与所述薄膜晶体管器件内的电极层相连。
  66. 根据权利要求63所述的方法，其特征在于，所述第二连接端为焊盘或锡球。
  67. 一种显示装置，其特征在于，包括：
    根据权利要求31至66中任一项所述的方法制备的包括薄膜晶体管器件的集成装置。
  68. 一种电子设备，其特征在于，包括：
    权利要求67所述的显示装置。
PCT/CN2018/110277 2018-10-15 2018-10-15 具有薄膜晶体管器件的集成装置及其制备方法 WO2020077499A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201880002041.0A CN109496353B (zh) 2018-10-15 2018-10-15 具有薄膜晶体管器件的集成装置及其制备方法
PCT/CN2018/110277 WO2020077499A1 (zh) 2018-10-15 2018-10-15 具有薄膜晶体管器件的集成装置及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/110277 WO2020077499A1 (zh) 2018-10-15 2018-10-15 具有薄膜晶体管器件的集成装置及其制备方法

Publications (1)

Publication Number Publication Date
WO2020077499A1 true WO2020077499A1 (zh) 2020-04-23

Family

ID=65713858

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/110277 WO2020077499A1 (zh) 2018-10-15 2018-10-15 具有薄膜晶体管器件的集成装置及其制备方法

Country Status (2)

Country Link
CN (1) CN109496353B (zh)
WO (1) WO2020077499A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150108479A1 (en) * 2013-10-23 2015-04-23 Pixtronix, Inc. Thin-film transistors incorporated into three dimensional mems structures
CN104576754A (zh) * 2014-12-30 2015-04-29 深圳市华星光电技术有限公司 薄膜晶体管及薄膜晶体管的制备方法
CN104867942A (zh) * 2015-04-29 2015-08-26 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构
CN105446031A (zh) * 2014-09-30 2016-03-30 群创光电股份有限公司 显示面板及显示装置
CN106206611A (zh) * 2016-08-19 2016-12-07 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
CN107665057A (zh) * 2016-07-31 2018-02-06 矽创电子股份有限公司 触控显示设备

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7098070B2 (en) * 2004-11-16 2006-08-29 International Business Machines Corporation Device and method for fabricating double-sided SOI wafer scale package with through via connections
US8710568B2 (en) * 2007-10-24 2014-04-29 Denso Corporation Semiconductor device having a plurality of elements on one semiconductor substrate and method of manufacturing the same
WO2018063327A1 (en) * 2016-09-30 2018-04-05 Intel Corporation Overpass dice stacks and methods of using same
CN107123656B (zh) * 2017-07-03 2019-12-03 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150108479A1 (en) * 2013-10-23 2015-04-23 Pixtronix, Inc. Thin-film transistors incorporated into three dimensional mems structures
CN105446031A (zh) * 2014-09-30 2016-03-30 群创光电股份有限公司 显示面板及显示装置
CN104576754A (zh) * 2014-12-30 2015-04-29 深圳市华星光电技术有限公司 薄膜晶体管及薄膜晶体管的制备方法
CN104867942A (zh) * 2015-04-29 2015-08-26 深圳市华星光电技术有限公司 Tft基板的制作方法及其结构
CN107665057A (zh) * 2016-07-31 2018-02-06 矽创电子股份有限公司 触控显示设备
CN106206611A (zh) * 2016-08-19 2016-12-07 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置

Also Published As

Publication number Publication date
CN109496353B (zh) 2022-08-16
CN109496353A (zh) 2019-03-19

Similar Documents

Publication Publication Date Title
US10797040B2 (en) Method of manufacturing display module using LED
US10410038B2 (en) Optical fingerprint module
CN107256880B (zh) 一种显示器阵列基板、制备方法和显示器
JP2023531340A (ja) 表示基板及び表示装置
WO2022206687A1 (zh) 一种显示面板、显示模组及电子设备
WO2021254264A1 (zh) 指纹识别电路、装置、控制方法和显示装置
US11832498B2 (en) Organic light-emitting display substrate, manufacturing method thereof, and organic light-emitting display device
TWI709797B (zh) 顯示面板
WO2020077538A1 (zh) 具有薄膜晶体管器件的集成装置及其制备方法
US20230214067A1 (en) Display Device
WO2020077499A1 (zh) 具有薄膜晶体管器件的集成装置及其制备方法
CN208848906U (zh) 具有薄膜晶体管器件的集成装置、显示装置及电子设备
CN111223886A (zh) 显示屏及电子设备
US20230343290A1 (en) Display device
US11903280B2 (en) Display device
TWI757036B (zh) 觸控顯示面板
CN113838995B (zh) 显示面板及显示装置
US20230200185A1 (en) Display Device
WO2023151127A1 (zh) Oled显示面板及其制作方法、oled显示模组
US11475804B2 (en) Display panel having an auxiliary layer overlapped with a bendable region
US11824064B2 (en) Display device, method of manufacturing the same, and tiled display device including the same
US20230200186A1 (en) Display device and manufacturing method thereof
US20230320168A1 (en) Display device
WO2023056821A1 (zh) 自发光显示装置和液晶显示装置
KR20240013945A (ko) 표시 장치 및 이의 제조 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18937052

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18937052

Country of ref document: EP

Kind code of ref document: A1