CN107123656B - 一种阵列基板及其制备方法、显示面板 - Google Patents

一种阵列基板及其制备方法、显示面板 Download PDF

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CN107123656B
CN107123656B CN201710536548.1A CN201710536548A CN107123656B CN 107123656 B CN107123656 B CN 107123656B CN 201710536548 A CN201710536548 A CN 201710536548A CN 107123656 B CN107123656 B CN 107123656B
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layer
bare chip
substrate
pin
connecting line
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CN107123656A (zh
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王志东
邱云
曲连杰
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US15/962,066 priority patent/US10777583B2/en
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Abstract

本发明的实施例提供一种阵列基板及其制备方法、显示面板，涉及显示技术领域，可降低显示面板的成本。该阵列基板包括固定于衬底上的裸芯片，裸芯片包括引脚；缓冲层和第一金属层；第一金属层包括与裸芯片的引脚一一对应的外引脚，外引脚与其对应的裸芯片的引脚通过缓冲层上的过孔电连接；其中，外引脚的尺寸大于裸芯片的引脚的尺寸，且外引脚之间相互绝缘；薄膜晶体管、与薄膜晶体管的栅极同层的第一信号线和第一连接线、与薄膜晶体管的源极、漏极同层的第二信号线和第二连接线；第一连接线的一端与第一信号线电连接，另一端与外引脚电连接；第二连接线的一端与第二信号线电连接，另一端与外引脚电连接；其中，第一连接线与第二连接线相互绝缘。

Description

一种阵列基板及其制备方法、显示面板
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法、显示面板。
背景技术
薄膜场效应晶体管(Thin Film Transistor。简称TFT)显示技术已经成为主流显示技术，且该技术已经日趋成熟，因此如何降低TFT显示器件的成本，以提升竞争力，具有重要意义。
目前，TFT显示面板的阵列基板上，除在显示区形成包括TFT、透明电极等显示结构、在非显示区形成金属布线之外，在非显示区的芯片布置区，还需通过绑定工艺，绑定芯片。其中，绑定到阵列基板上的芯片都是已经封装好的芯片。
发明内容
本发明的实施例提供一种阵列基板及其制备方法、显示面板，可降低显示面板的成本。
为达到上述目的，本发明的实施例采用如下技术方案：
第一方面，提供一种阵列基板，包括：固定于衬底上的裸芯片，所述裸芯片包括引脚；依次设置于所述裸芯片远离所述衬底一侧的缓冲层和第一金属层；所述第一金属层包括与所述裸芯片的引脚一一对应的外引脚，所述外引脚与其对应的所述裸芯片的引脚通过所述缓冲层上的过孔电连接；其中，所述外引脚的尺寸大于所述裸芯片的引脚的尺寸，且所述外引脚之间相互绝缘；设置于所述第一金属层远离所述衬底一侧的薄膜晶体管、与所述薄膜晶体管的栅极同层的第一信号线和第一连接线、与所述薄膜晶体管的源极、漏极同层的第二信号线和第二连接线；所述第一连接线的一端与所述第一信号线电连接，另一端与所述外引脚电连接；所述第二连接线的一端与所述第二信号线电连接，另一端与所述外引脚电连接；其中，所述第一连接线与所述第二连接线相互绝缘；设置于所述薄膜晶体管远离所述衬底一侧且覆盖所述衬底的第一钝化层。
优选的，所述衬底包括凹槽；所述裸芯片固定于所述凹槽内。
进一步优选的，一个所述凹槽内固定一个所述裸芯片，且所述凹槽的尺寸与所述裸芯片的尺寸一致。
优选的，固定于所述凹槽中的所述裸芯片的表面与所述衬底的表面平齐。
优选的，所述第一金属层还包括遮光图案；所述薄膜晶体管为多晶硅薄膜晶体管，所述遮光图案在所述衬底上的正投影覆盖所述多晶硅薄膜晶体管的有源层在所述衬底上的正投影。
基于上述，优选的，所述阵列基板还包括依次设置于所述第一钝化层远离所述衬底一侧的平坦层和第一透明电极；所述第一透明电极与所述漏极电连接。
第二方面，提供一种显示面板，包括第一方面的阵列基板。
第三方面，提供一种阵列基板的制备方法，包括：将裸芯片固定于衬底上，所述裸芯片包括引脚；在固定有所述裸芯片的所述衬底上依次形成缓冲层和第一金属层；所述第一金属层包括与所述裸芯片的引脚一一对应的外引脚，所述外引脚与其对应的所述裸芯片的引脚通过所述缓冲层上的过孔电连接；其中，所述外引脚的尺寸大于所述裸芯片的引脚的尺寸，且所述外引脚之间相互绝缘；在形成有所述第一金属层的所述衬底上形成薄膜晶体管、与所述薄膜晶体管的栅极同层的第一信号线和第一连接线、与所述薄膜晶体管的源极、漏极同层的第二信号线和第二连接线；所述第一连接线的一端与所述第一信号线电连接，另一端与所述外引脚电连接；所述第二连接线的一端与所述第二信号线电连接，另一端与所述外引脚电连接；其中，所述第一连接线与所述第二连接线相互绝缘；在形成有所述薄膜晶体管的衬底上形成第一钝化层，所述第一钝化层覆盖所述衬底。
优选的，将裸芯片固定于衬底上，包括：在衬底上形成凹槽，并在凹槽内形成粘结层；将所述裸芯片放入所述凹槽，并通过所述凹槽内的所述粘结层固定。
进一步优选的，一个所述凹槽内固定一个所述裸芯片，且所述凹槽的尺寸与所述裸芯片的尺寸一致。
优选的，固定于所述凹槽中的所述裸芯片的表面与所述衬底的表面平齐。
基于上述，优选的，所述第一金属层还包括遮光图案；所述薄膜晶体管为多晶硅薄膜晶体管，所述遮光图案在所述衬底上的正投影覆盖所述多晶硅薄膜晶体管的有源层在所述衬底上的正投影。
在此基础上，所述制备方法具体包括：在衬底上形成凹槽，并在所述凹槽底部形成粘结层，将裸芯片放置于所述凹槽中通过所述粘结层固定；依次形成缓冲层和第一金属层；所述第一金属层包括外引脚和遮光图案，所述外引脚与其对应的所述裸芯片的引脚通过所述缓冲层上的过孔电连接；其中，所述外引脚的尺寸大于所述裸芯片的引脚的尺寸，且所述外引脚之间相互绝缘；依次形成多晶硅有源层、栅绝缘层、包括栅极、第一信号线和第一连接线的栅金属层；所述多晶硅有源层形成于所述遮光图案的上方，所述第一连接线的一端与所述第一信号线电连接，另一端通过所述栅绝缘层上的过孔与所述外引脚电连接；依次形成层间绝缘层、包括源极、漏极、第二信号线和第二连接线的源漏金属层、以及第一钝化层；所述第二连接线的一端与所述第二信号线电连接，另一端通过所述层间绝缘层和所述栅绝缘层上的过孔与所述外引脚电连接；其中，所述第一连接线与所述第二连接线相互绝缘。
优选的，所述制备方法还包括：在所述第一钝化层上依次形成平坦层和第一透明电极。
本发明的实施例提供一种阵列基板及其制备方法、显示面板，通过先将裸芯片固定于衬底上，之后形成缓冲层和第一金属层，可使缓冲层相当于裸芯片封装的介质层，而第一金属层的外引脚实现对裸芯片引脚的放大，在此基础上，在形成薄膜晶体管的过程中，可使与栅极同层的第一信号线、与源极和漏极同层的第二信号线实现与裸芯片的电连接，而无需进行绑定工艺，之后通过形成第一钝化层，实现对裸芯片的保护。基于此，本发明实施例可在形成薄膜晶体管、第一钝化层的过程中，同步完成对裸芯片的封装，因而可减低芯片成本，从而降低阵列基板所应用的显示装置的成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的一种阵列基板的结构示意图一；
图2为本发明提供的一种衬底上显示区、非显示区、芯片布置区的区域示意图；
图3为本发明提供的一种阵列基板的结构示意图二；
图4为本发明提供的一种阵列基板的结构示意图三；
图5为本发明提供的一种阵列基板的结构示意图四；
图6为本发明提供的一种阵列基板的结构示意图五；
图7为本发明提供的一种阵列基板的制备方法的流程示意图；
图8a-图8i为本发明提供的制备一种阵列基板的过程示意图。
附图标记：
01-显示区；02-非显示区；03-芯片布置区；10-衬底；101-凹槽；20-裸芯片；30-缓冲层；401-外引脚；402-遮光图案；50-薄膜晶体管；501-栅极；502-栅绝缘层；503-有源层；504-源极；505-漏极；601-第一连接线；602-第二连接线；70-第一钝化层；80-粘结层；90-层间绝缘层；100-平坦层；110-第一透明电极；120-第二透明电极；130-第二钝化层。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种阵列基板，如图1所示，包括：固定于衬底10上的裸芯片20，裸芯片20包括引脚；依次设置于裸芯片20远离衬底10一侧的缓冲层30和第一金属层；第一金属层包括与裸芯片20的引脚一一对应的外引脚401，外引脚401与其对应的裸芯片20的引脚通过缓冲层30上的过孔电连接；其中，外引脚401的尺寸大于裸芯片20的引脚的尺寸，且外引脚401之间相互绝缘；设置于第一金属层远离衬底一侧的薄膜晶体管50、与薄膜晶体管50的栅极501同层的第一信号线(图中未标识出)和第一连接线601、与薄膜晶体管50的源极504、漏极505同层的第二信号线(图中未标识出)和第二连接线602；第一连接线601的一端与第一信号线电连接，另一端与外引脚401电连接；第二连接线602的一端与第二信号线电连接，另一端与外引脚401电连接；其中，第一连接线601与第二连接线602相互绝缘；设置于薄膜晶体管50远离衬底10一侧且覆盖衬底10的第一钝化层70。
需要说明的是，第一，本领域技术人员应该知道，如图2所示，阵列基板包括显示区01和非显示区02，薄膜晶体管50等显示元件设置在显示区01，裸芯片20设置于非显示区02的芯片布置区03，当然在非显示区02的其他区域还设置有一些布线。
第二，裸芯片20可通过粘结层80固定于衬底10上。裸芯片20为未封装之前的芯片。
其中，设置于阵列基板上的裸芯片20不限于一个，可以是两个及以上，例如可以是用于驱动的裸芯片20、时序控制的裸芯片20等。
第三，裸芯片20的引脚位于裸芯片20的表面。由于裸芯片20的引脚在纳米量级，因此，通过设置与裸芯片20的每个引脚一一对应的外引脚401，并使外引脚401与其对应的裸芯片20的引脚电连接，可实现裸芯片20引脚的放大，以便后续实现与其他金属线的精度对接。
其中，对于外引脚401的尺寸可根据实际情况进行设定，以能实现与第一连接线601和第二连接线602的电连接即可。
第四，通过第一连接线601，可使裸芯片20向与栅极501同层的第一信号线提供信号；通过第二连接线602，可使裸芯片20向与源极504和漏极505同层的第二信号线提供信号。
其中，本领域技术人员应该明白，第一连接线601和第二连接线602应与不同的外引脚401电连接。当然，第一信号线之间、第二信号线之间、第一信号线和第二信号线之间都是相互绝缘的。
第五，不对薄膜晶体管50的类型进行限定，可以是任意结构类型的薄膜晶体管50。
本发明实施例提供一种阵列基板，通过先将裸芯片20固定于衬底10上，之后形成缓冲层30和第一金属层，可使缓冲层30相当于裸芯片20封装的介质层，而第一金属层的外引脚401实现对裸芯片20引脚的放大，在此基础上，在形成薄膜晶体管50的过程中，可使与栅极501同层的第一信号线、与源极504和漏极505同层的第二信号线实现与裸芯片20的电连接，而无需进行绑定工艺，之后通过形成第一钝化层70，实现对裸芯片20的保护。基于此，本发明实施例可在形成薄膜晶体管50、第一钝化层70的过程中，同步完成对裸芯片20的封装，因而可减低芯片成本，从而降低阵列基板所应用的显示装置的成本。
优选的，如图3所示，衬底10包括凹槽；裸芯片20固定于凹槽内。
通过将裸芯片20设置于衬底10的凹槽中，可使设置有裸芯片20的衬底10表面相对较为平坦，因而可降低后续工艺的难度，提高良率。
进一步的，一个凹槽内固定一个裸芯片20，且凹槽的尺寸与裸芯片20的尺寸一致。这样，可避免凹槽与裸芯片20之间存在间隙，而导致衬底10的表面出现较高的段差。
优选的，如图3所示，固定于凹槽中的裸芯片20的表面与衬底10的表面平齐。
即：粘结层80与裸芯片20的高度和等于凹槽的高度。
通过使固定于凹槽中的裸芯片20的表面与衬底10的表面平齐，可保证设置有裸芯片20的衬底10表面的平坦性，可进一步降低后续工艺的难度，提高良率。
优选的，如图4所示，第一金属层还包括遮光图案402；薄膜晶体管50为多晶硅薄膜晶体管，遮光图案402在衬底10上的正投影覆盖多晶硅薄膜晶体管的有源层503在衬底10上的正投影。
当薄膜晶体管50为多晶硅薄膜晶体管时，通过在衬底10与有源层503之间设置遮光图案402，可避免多晶硅材料的有源层503被光照射而影响多晶硅薄膜晶体管的性能。在此基础上，通过使遮光图案402和外引脚401同层设置，即遮光图案402和外引脚401通过同一次构图工艺形成，可使对裸芯片20的封装不会导致构图工艺次数的增加。
基于上述，优选的，如图5和图6所示，阵列基板还包括依次设置于第一钝化层70远离衬底10一侧的平坦层100和第一透明电极110；第一透明电极110与漏极505电连接。
其中，平坦层100的材料可以为树脂材料，平坦层100可进一步起到保护裸芯片20的作用。
第一透明电极110可以为像素电极，或者阳极。
当第一透明电极110为像素电极时，可选的，如图6所示，阵列基板还可以包括第二透明电极120，即公共电极。第一透明电极110和第二透明电极120之间通过第二钝化层130隔离。
当第一透明电极110为阳极时，阵列基板还应包括依次设置于阳极上方的有机材料功能层和阴极。
本发明实施例还提供一种显示面板，包括上述的阵列基板。
其中，显示面板可以是液晶显示面板，也可以是有机电致发光二极管显示面板。
所述显示面板具有与阵列基板相同的效果，具体在此不再赘述。
本发明实施例还提供一种阵列基板的制备方法，如图1所示，包括：将裸芯20片固定于衬底10上，裸芯片20包括引脚；在固定有裸芯片20的衬底10上依次形成缓冲层30和第一金属层；第一金属层包括与裸芯片20的引脚一一对应的外引脚401，外引脚401与其对应的裸芯片20的引脚通过缓冲层30上的过孔电连接；其中，外引脚401的尺寸大于裸芯片20的引脚的尺寸，且外引脚401之间相互绝缘；在形成有第一金属层的衬底10上形成薄膜晶体管50、与薄膜晶体管50的栅极501同层的第一信号线(图中未标识出)和第一连接线601、与薄膜晶体管的源极504、漏极505同层的第二信号线(图中未标识出)和第二连接线602；第一连接线601的一端与第一信号线电连接，另一端与外引脚401电连接；第二连接线602的一端与第二信号线电连接，另一端与外引脚401电连接；其中，第一连接线601与第二连接线602相互绝缘；在形成有薄膜晶体管50的衬底10上形成第一钝化层70，第一钝化层70覆盖衬底10。
本发明实施例提供一种阵列基板的制备方法，通过先将裸芯片20固定于衬底10上，之后形成缓冲层30和第一金属层，可使缓冲层30相当于裸芯片20封装的介质层，而第一金属层的外引脚401实现对裸芯片20引脚的放大，在此基础上，在形成薄膜晶体管50的过程中，可使与栅极501通过同一次构图工艺形成的第一信号线、与源极504和漏极505通过同一次构图工艺形成的第二信号线实现与裸芯片20的电连接，而无需进行绑定工艺，之后通过形成第一钝化层70，实现对裸芯片20的保护。基于此，本发明实施例可在形成薄膜晶体管50、第一钝化层70的过程中，同步完成对裸芯片20的封装，因而可减低芯片成本，从而降低阵列基板所应用的显示装置的成本。
优选的，如图3所示，将裸芯片20固定于衬底10上，包括：在衬底10上形成凹槽，并在凹槽内形成粘结层80；将裸芯片20放入凹槽，并通过凹槽内的粘结层80固定。
其中，可通过光刻、钻孔、化学腐蚀等方法在衬底10上形成凹槽。
粘结层80的材料可以为粘结剂，可通过涂覆工艺涂覆在凹槽的底部。
需要说明的是，在放置裸芯片20时，应使裸芯片20的引脚朝上，以保证外引脚401能通过缓冲层30上的过孔与裸芯片20的引脚电连接。
通过将裸芯片20放置于衬底10的凹槽中，可使设置有裸芯片20的衬底10表面相对较为平坦，因而可降低后续工艺的难度，提高良率。
进一步的，一个凹槽内固定一个裸芯片20，且凹槽的尺寸与裸芯片20的尺寸一致。这样，可避免凹槽与裸芯片20之间存在间隙，而导致衬底10的表面出现较高的段差。
优选的，如图3所示，固定于凹槽中的裸芯片20的表面与衬底10的表面平齐。
即：粘结层80与裸芯片20的高度和等于凹槽的高度。
通过使固定于凹槽中的裸芯片20的表面与衬底10的表面平齐，可保证设置有裸芯片20的衬底10表面的平坦性，可进一步降低后续工艺的难度，提高良率。
优选的，如图4所示，第一金属层还包括遮光图案402；薄膜晶体管50为多晶硅薄膜晶体管，遮光图案402在衬底10上的正投影覆盖多晶硅薄膜晶体管的有源层503在衬底10上的正投影。
当薄膜晶体管50为多晶硅薄膜晶体管时，通过在衬底10与有源层503之间形成遮光图案402，可避免多晶硅材料的有源层503被光照射而影响多晶硅薄膜晶体管的性能。在此基础上，通过使遮光图案402和外引脚401同层，即遮光图案402和外引脚401通过同一次构图工艺形成，可使对裸芯片20的封装不会导致构图工艺次数的增加。
下面提供一具体实施例以详细说明一种阵列基板的制备方法，如图7所示，该阵列基板的制备方法包括如下步骤：
S10、如图8a和图8b所示，在衬底10上形成凹槽101，并在凹槽101底部形成粘结层80，将裸芯片20放置于凹槽101中通过粘结层80固定。
其中，参照图2所示，裸芯片20设置于非显示区02的芯片布置区03。
S11、如图8c和8d所示，依次形成缓冲层30和第一金属层；第一金属层包括外引脚401和遮光图案402，外引脚401与其对应的裸芯片20的引脚通过缓冲层30上的过孔电连接；其中，外引脚401的尺寸大于裸芯片20的引脚的尺寸，且外引脚401之间相互绝缘。
即：先通过一次构图工艺形成缓冲层30，缓冲层30包括露出裸芯片20引脚的过孔。之后，通过一次构图工艺形成第一金属层。其中，一次构图工艺包括成膜、光刻、刻蚀的工艺。
其中，缓冲层30的材料包括氧化硅(SiOx)、氮化硅(SiNx)中的至少一种。
第一金属层的材料包括钼(Mo)、铝钕、钼铝合金等。
S12、如图8e、8f和8g所示，依次形成多晶硅有源层503、栅绝缘层502、包括栅极501、第一信号线(图中未标识出)和第一连接线601的栅金属层；多晶硅有源层503形成于遮光图案402的上方；第一连接线601的一端与第一信号线电连接，另一端通过栅绝缘层502上的过孔与外引脚401电连接。
即：先通过一次构图工艺形成多晶硅有源层503；之后通过一次构图工艺形成栅绝缘层502，栅绝缘层502包括露出部分外引脚401的过孔；然后，通过一次构图工艺形成栅金属层。
其中，形成多晶硅有源层503，具体可以采用如下方法：采用等离子增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，简称PECVD)在衬底10上沉积一层非晶硅薄膜，采用高温烤箱对非晶硅薄膜进行脱氢工艺处理，以防止在晶化过程中出现氢爆现象以及降低晶化后薄膜内部的缺陷态密度作用。脱氢工艺完成后，进行低温多晶硅(Low Temperature Poly-Silicon，LTPS)工艺过程，采用激光退火工艺(ELA)、金属诱导结晶工艺(MIC)、固相结晶工艺(SPC)等结晶化手段对非晶硅薄膜进行结晶化处理，在衬底10上形成多晶硅薄膜。之后，进行光刻、刻蚀形成多晶硅有源层503。
当然，也可以先对非晶硅薄膜进行光刻、刻蚀形成非晶硅层，之后，对非晶硅层进行LTPS工艺，形成多晶硅有源层503。
本领域技术人员应该知道，多晶硅有源层503和遮光图案402位于衬底10的显示区01。
栅绝缘层502的材料包括SiOx、SiNx中的至少一种。
栅金属层的材料包括Mo、铝钼合金等。
S13、如图8h和8i所示，依次形成层间绝缘层90、包括源极504、漏极505、第二信号线(图中未标识出)和第二连接线602的源漏金属层；第二连接线602的一端与第二信号线电连接，另一端通过层间绝缘层90和栅绝缘层502上的过孔与外引脚401电连接；其中，第一连接线601与第二连接线602相互绝缘。
即，先通过一次构图工艺形成层间绝缘层90，为露出部分外引脚401以及多晶硅有源层503，在刻蚀形成层间绝缘层90时，还对栅绝缘层502进行刻蚀，以在层间绝缘层90和栅绝缘层502上同时形成露出部分外引脚401、用于使源极504和漏极505与多晶硅有源层503接触的过孔；之后通过一次构图工艺形成源漏金属层。
其中，层间绝缘层90的材料包括SiOx、SiNx中的至少一种。
源漏金属层的材料包括钼(Mo)、铝钼合金等。
S14、如图4所示，形成第一钝化层70。
其中，第一钝化层70的材料包括SiOx、SiNx中的至少一种。
在S10-S14的基础上，如图5和图6所示，在第一钝化层70上依次形成平坦层100和第一透明电极110。
其中，平坦层100的材料可以为树脂材料，平坦层100可进一步起到保护裸芯片20的作用。平坦层100可采用旋涂工艺制备形成，以上形成平坦层100后的基板平坦性更好。
第一透明电极110可以为像素电极，或者阳极。
当第一透明电极110为像素电极时，可选的，如图6所示，所述制备方法还包括形成第二透明电极120，即公共电极。第一透明电极110和第二透明电极120之间通过第二钝化层130隔离。
当第一透明电极110为阳极时，所述制备方法还包括依次在阳极上方形成有机材料功能层和阴极。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (14)

1.一种阵列基板，其特征在于，包括：
固定于衬底上的裸芯片，所述裸芯片包括引脚；
依次设置于所述裸芯片远离所述衬底一侧的缓冲层和第一金属层；所述第一金属层包括与所述裸芯片的引脚一一对应的外引脚，所述外引脚与其对应的所述裸芯片的引脚通过所述缓冲层上的过孔电连接；其中，所述外引脚的尺寸大于所述裸芯片的引脚的尺寸，且所述外引脚之间相互绝缘；
设置于所述第一金属层远离所述衬底一侧的薄膜晶体管、与所述薄膜晶体管的栅极同层的第一信号线和第一连接线、与所述薄膜晶体管的源极、漏极同层的第二信号线和第二连接线；所述第一连接线的一端与所述第一信号线电连接，另一端与所述外引脚电连接；所述第二连接线的一端与所述第二信号线电连接，另一端与所述外引脚电连接；其中，所述第一连接线与所述第二连接线相互绝缘；
设置于所述薄膜晶体管远离所述衬底一侧且覆盖所述衬底的第一钝化层。
2.根据权利要求1所述的阵列基板，其特征在于，所述衬底包括凹槽；
所述裸芯片固定于所述凹槽内。
3.根据权利要求2所述的阵列基板，其特征在于，一个所述凹槽内固定一个所述裸芯片，且所述凹槽的尺寸与所述裸芯片的尺寸一致。
4.根据权利要求2或3所述的阵列基板，其特征在于，固定于所述凹槽中的所述裸芯片的表面与所述衬底的表面平齐。
5.根据权利要求1所述的阵列基板，其特征在于，所述第一金属层还包括遮光图案；
所述薄膜晶体管为多晶硅薄膜晶体管，所述遮光图案在所述衬底上的正投影覆盖所述多晶硅薄膜晶体管的有源层在所述衬底上的正投影。
6.根据权利要求1所述的阵列基板，其特征在于，还包括依次设置于所述第一钝化层远离所述衬底一侧的平坦层和第一透明电极；
所述第一透明电极与所述漏极电连接。
7.一种显示面板，其特征在于，包括权利要求1-6任一项所述的阵列基板。
8.一种阵列基板的制备方法，其特征在于，包括：
将裸芯片固定于衬底上，所述裸芯片包括引脚；
在固定有所述裸芯片的所述衬底上依次形成缓冲层和第一金属层；所述第一金属层包括与所述裸芯片的引脚一一对应的外引脚，所述外引脚与其对应的所述裸芯片的引脚通过所述缓冲层上的过孔电连接；其中，所述外引脚的尺寸大于所述裸芯片的引脚的尺寸，且所述外引脚之间相互绝缘；
在形成有所述第一金属层的所述衬底上形成薄膜晶体管、与所述薄膜晶体管的栅极同层的第一信号线和第一连接线、与所述薄膜晶体管的源极、漏极同层的第二信号线和第二连接线；所述第一连接线的一端与所述第一信号线电连接，另一端与所述外引脚电连接；所述第二连接线的一端与所述第二信号线电连接，另一端与所述外引脚电连接；其中，所述第一连接线与所述第二连接线相互绝缘；
在形成有所述薄膜晶体管的衬底上形成第一钝化层，所述第一钝化层覆盖所述衬底。
9.根据权利要求8所述的制备方法，其特征在于，将裸芯片固定于衬底上，包括：
在衬底上形成凹槽，并在凹槽内形成粘结层；
将所述裸芯片放入所述凹槽，并通过所述凹槽内的所述粘结层固定。
10.根据权利要求9所述的制备方法，其特征在于，一个所述凹槽内固定一个所述裸芯片，且所述凹槽的尺寸与所述裸芯片的尺寸一致。
11.根据权利要求9所述的制备方法，其特征在于，固定于所述凹槽中的所述裸芯片的表面与所述衬底的表面平齐。
12.根据权利要求8-11任一项所述的制备方法，其特征在于，所述第一金属层还包括遮光图案；
所述薄膜晶体管为多晶硅薄膜晶体管，所述遮光图案在所述衬底上的正投影覆盖所述多晶硅薄膜晶体管的有源层在所述衬底上的正投影。
13.根据权利要求12所述的制备方法，其特征在于，所述制备方法具体包括：
在衬底上形成凹槽，并在所述凹槽底部形成粘结层，将裸芯片放置于所述凹槽中通过所述粘结层固定；
依次形成缓冲层和第一金属层；所述第一金属层包括外引脚和遮光图案，所述外引脚与其对应的所述裸芯片的引脚通过所述缓冲层上的过孔电连接；其中，所述外引脚的尺寸大于所述裸芯片的引脚的尺寸，且所述外引脚之间相互绝缘；
依次形成多晶硅有源层、栅绝缘层、包括栅极、第一信号线和第一连接线的栅金属层；所述多晶硅有源层形成于所述遮光图案的上方，所述第一连接线的一端与所述第一信号线电连接，另一端通过所述栅绝缘层上的过孔与所述外引脚电连接；
依次形成层间绝缘层、包括源极、漏极、第二信号线和第二连接线的源漏金属层、以及第一钝化层；所述第二连接线的一端与所述第二信号线电连接，另一端通过所述层间绝缘层和所述栅绝缘层上的过孔与所述外引脚电连接；其中，所述第一连接线与所述第二连接线相互绝缘。
14.根据权利要求8所述的制备方法，其特征在于，还包括：在所述第一钝化层上依次形成平坦层和第一透明电极。
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