ATE548756T1 - Einrichtung und verfahren zur herstellung einer doppelseitigen kapselung auf soi-wafermassstab mit durchkontaktierungen - Google Patents

Einrichtung und verfahren zur herstellung einer doppelseitigen kapselung auf soi-wafermassstab mit durchkontaktierungen

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Publication number
ATE548756T1
ATE548756T1 AT05807945T AT05807945T ATE548756T1 AT E548756 T1 ATE548756 T1 AT E548756T1 AT 05807945 T AT05807945 T AT 05807945T AT 05807945 T AT05807945 T AT 05807945T AT E548756 T1 ATE548756 T1 AT E548756T1
Authority
AT
Austria
Prior art keywords
soi wafer
contacts
double
producing
wafer scale
Prior art date
Application number
AT05807945T
Other languages
English (en)
Inventor
Howard Chen
Louis Hsu
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE548756T1 publication Critical patent/ATE548756T1/de

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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    • H01L2224/06181—On opposite sides of the body
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    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Led Device Packages (AREA)
AT05807945T 2004-11-16 2005-11-03 Einrichtung und verfahren zur herstellung einer doppelseitigen kapselung auf soi-wafermassstab mit durchkontaktierungen ATE548756T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/990,252 US7098070B2 (en) 2004-11-16 2004-11-16 Device and method for fabricating double-sided SOI wafer scale package with through via connections
PCT/EP2005/055734 WO2006053832A1 (en) 2004-11-16 2005-11-03 Device and method for fabricating double-sided soi wafer scale package with through via connections

Publications (1)

Publication Number Publication Date
ATE548756T1 true ATE548756T1 (de) 2012-03-15

Family

ID=35677682

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05807945T ATE548756T1 (de) 2004-11-16 2005-11-03 Einrichtung und verfahren zur herstellung einer doppelseitigen kapselung auf soi-wafermassstab mit durchkontaktierungen

Country Status (7)

Country Link
US (3) US7098070B2 (de)
EP (1) EP1851797B1 (de)
JP (1) JP2008521213A (de)
CN (1) CN100481421C (de)
AT (1) ATE548756T1 (de)
TW (1) TWI351727B (de)
WO (1) WO2006053832A1 (de)

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US7489025B2 (en) 2009-02-10
CN101044618A (zh) 2007-09-26
JP2008521213A (ja) 2008-06-19
CN100481421C (zh) 2009-04-22

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